JPH0393317A - Code synchronization circuit - Google Patents

Abstract

PURPOSE:To improve the word synchronization characteristic by adding a means deciding word synchronization with a first syndrome arithmetic value and a syndrome arithmetic value when the word synchronization is established so as to detect mis-synchronization thereby applying synchronization decision again. CONSTITUTION:The presence or absence of 1st and N-th syndromes of a word of a 2nd translation output 14 obtained by inputting an arithmetic result 12 (syndrome) to a memory 3, that is, whether or not the value is '0' is decided by a 2nd word synchronization circuit 7. Then an AND circuit 8 ANDs a 1st word synchronization decision result 15 and a 2nd word synchronization decision result 16. Thus, a word synchronization decision result 19 is at '1' only when word synchronization is attained without deviation of 1 bit after and before a head position of a word and the establishment of the synchronization is decided. Thus, even when a data signal is deviated by one bit before and after a correct synchronization position, no malfunction is caused.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a decoding device that corrects block code errors in a received BCH code data signal.

〔overview〕

The present invention provides a code synchronization circuit that performs word synchronization by performing syndrome calculations on data signals, by adding means for determining word synchronization based on the initial syndrome calculation value and the syndrome calculation value when word synchronization is established. This is intended to improve the word synchronization characteristics by detecting erroneous synchronization that occurs when one bit is shifted before or after the correct synchronization position, and performing synchronization determination again.

[Conventional technology]

A conventional technique will be explained with reference to the drawings.

FIG. 2 is a block diagram of a conventional example. In FIG. 2, a computing unit (FEC) 1 receives a data signal 1l and an initialization signal 20 and calculates a syndrome of the data signal, and a delay circuit 2 receives a data signal 11 and outputs it as a delayed data signal 17. and the calculation result 12 of the calculation unit 1
(syndrome) as input memory 3 and translation output 1
3A, a timing pulse 18, and a delayed data signal 17, an error correction unit 4, a first synchronization circuit 6, which inputs the calculation result 12 (syndrome) and determines word synchronization, and this first synchronization circuit 6. The timing generation section 5 inputs the word synchronization determination result 15 to be output. In this conventional example, word synchronization is established by syndrome. To do this, first, n bits of the block-encoded data signal 11 are input to the arithmetic unit 1, and the syndrome of the code word of the data signal 11 is calculated.

Here, the syndrome is the coefficient of the polynomial that is the remainder obtained by dividing the polynomial whose coefficients are each bit of the code word by the Seikai polynomial. In this case, if there is no error in the code word, the syndrome is 0.
become. The syndrome, that is, the calculation result 12 is input to the first synchronization circuit 6. In the first synchronization circuit 6, when the syndrome is 0 consecutively for N times (N≧1>), it is determined that word synchronization has been established, and word synchronization determination result 15
outputs "l" as On the other hand, if the syndrome is not 0 consecutively M times (M≧1), it is determined that the word synchronization is out, and “0” is output as the word synchronization determination result 15. This word synchronization determination result 15 is input to the timing generation unit 5, and if synchronization is not achieved (“0” is input), the timing generation position is shifted by 1 bit from the previous time and the arithmetic unit 1 is initialized. Subsequently, the arithmetic unit 1 reads n bits of the data signal 11. Maximum such attempts (
If this is repeated n-1) times, code synchronization can be achieved without fail. On the other hand, if the translation output 13 indicating the error position in the error correcting section 4 and the timing pulse 18 sent out by the timing generating section 5 match, the output signal is sent via the delay circuit 2. Error correction is performed on the obtained delayed data signal 17 at the error position.

Here, the error correction value is obtained from the translation output 13, and is input to the error correction section 4 to obtain the error correction result 21.

Further, the reason why the delay circuit 2 is required is because there is an operation delay in the arithmetic unit 1. Let A(X) be the polynomial representing the code word transmitted in the BCH code, and consider a case where the code word obtained on the receiving side is shifted by one bit after the normal bit position, and the polynomial representing this is B.
(x), then A(x) −aoX'+ a I
x'+ +aR-I X'''-1= 0, mod
G(X) − (1) and B(X) = a + )('+...+al,-+
x″-”+ b x″-1l(b+a+x'++a,
-+X''-')X ・-・(2) Here, a1 is the 1st bit signal, b is n-1
The bit-th signal, n is the block length, and G (x) is the raw polynomial. Similarly, if the code word is shifted by one bit before the normal pit position, the syndrome becomes 0 if ao=b or aI, -,=t).

[Problem that the invention seeks to solve]

However, in the above equations (1) and (2), the probability that the coefficients of each equation will be ao-bSa1-1=b is 1/2 in the case of random data. Therefore, in the word synchronization pull-in process, if the word synchronization is at a position shifted by ±1 bit from the normal synchronization position, and assuming that N consecutive syndrome values 0 occur for the word synchronization to be established, the probability is (1/2)'. This will cause incorrect synchronization. That is, in the conventional example, there is a problem that false synchronization occurs due to pseudo pull-in.

SUMMARY OF THE INVENTION An object of the present invention is to solve this problem and provide a code synchronization circuit that does not cause malfunction even if the data signal is shifted by one bit before or after the correct synchronization position.

[Means for solving problems]

The present invention provides a synchronization means including an arithmetic unit that takes in a BCH encoded data signal and performs syndrome calculation, a first synchronization circuit that determines word synchronization based on the calculation result of this arithmetic unit, and an asynchronous a timing generation section that generates a timing pulse based on the judgment output of the above; a memory that receives the calculation result as an address input and generates a translation output; and an error correction section that inputs the timing pulse and the translation output to correct errors in the data signal. In the code synchronization circuit, the synchronization means includes a second synchronization circuit that determines word synchronization based on the initial syndrome calculation value and the syndrome calculation value when word synchronization is established, and the first and second synchronization circuits. It is characterized in that it includes an AND circuit that performs an AND operation of each output.

[Effect] In general, synchronization is determined by N consecutive cases where the computed value of the syndrome is 0 (N≦l). However, if the beginning of the word to be computed is 1 bit before or after If the shift is mistakenly recognized as being synchronized, it will be determined that the syndrome has been synchronized even if there are only N-1 consecutive calculated values.The second synchronization circuit will synchronize the first and Nth Such malfunctions can be prevented by determining the calculated value of the syndrome.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, an arithmetic unit (FEC) 1 receives a BCH encoded data signal l1 and an initialization signal 20, a delay circuit 2 receives a data signal l1, and an operation result 12 (syndrome) is input. and a first translation output 13 from which the information stored in this memory 3 is read out using the calculation result l2 as an address.
and timing pulse l8 and delayed data signal l7
The error correction unit 4 inputs the word synchronization determination result 19
The timing generating section 5 is provided with a timing generating section 5 that uses human power.

Here, the features of the present invention include a first synchronous circuit 6 that uses the calculation result 12 (syndrome) as a human power, and a second synchronous circuit that uses the second translation output 14 sent from the memory 3 as the human power. 7, a first word synchronization determination result 15, and a second word synchronization determination result 16, respectively, are input thereto and an AND circuit 8 is provided to perform an AND operation. The first translation output l3 is related to the error position similar to that of the conventional example, but the second translation output l4 is based on the fact that the first syndrome sent out by the memory 3 is 0 and that word synchronization is established. This is information regarding the Nth syndrome being 0.

In this embodiment, the data signal 11 is a block encoded bit string, and the arithmetic unit (FEC) l is the same as the syndrome arithmetic unit in the conventional example. The first synchronization circuit is also the same as the conventional synchronization circuit, and if it is determined that synchronization is achieved, the first word synchronization determination result 15 becomes "l#", and otherwise becomes "0". There is a possibility that erroneous synchronization occurs when the start position of a word is shifted by 1 bit before or after.

Therefore, by manually inputting the calculation result 12 (syndrome) into the memory 3, the presence or absence of the syndrome between the 1st and Nth words of the second translation output 14 obtained by inputting the calculation result 12 (syndrome) into the memory 3 is determined. This is determined by the word synchronization circuit 7. If the W rate at which the syndrome occurs at the above position is high, it means that the first position of the word is shifted by one bit before or after, and the second word synchronization judgment result 16 is "0°'.When the Isshi syndrome is O, the second word synchronization determination result 16 becomes "1" and it is determined that synchronization is established.The AND circuit 8 determines the first word synchronization determination result. 15 and second word synchronization determination result 16
Take the logical product of This allows for the first position of the word. Only when word synchronization is achieved without one pit shift before and after, the word synchronization determination result 19 becomes "1" and it is determined that synchronization has been achieved. The delay circuit 2, timing generation section 5, and error correction section 4 are the same circuits as in the conventional example.

〔Effect of the invention〕

According to the present invention, even if erroneous synchronization occurs at a position that is l bits before and after the correct synchronization position, this can be detected and word synchronization can be started again to achieve normal code synchronization. This has the effect of realizing a code synchronization circuit having synchronization characteristics.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a block diagram of a conventional example. l... Arithmetic unit, 2... Delay circuit, 3... Memory,
4... Error correction section, 5... Timing generation section, 6.
...first synchronous circuit, 7...second synchronous circuit, . 8・
...AND circuit, 11...Data signal, 12...Computation result, 13, 13A...First translation output sent out by memory, 14...Second translation output sent out by memory,
15... First word synchronization determination result, 15A, 19.
... Word synchronization determination result, 16... Second word synchronization determination result, 17... Delayed data signal, 18... Timing pulse, 20... Initialization signal, 21... Error correction result.

Claims (1)

[Scope of Claims] 1. Synchronization means including a computing unit that takes in a BCH encoded data signal and performs syndrome calculation, and a first synchronization circuit that determines word synchronization based on the calculation result of this computing unit; a timing generator that generates a timing pulse based on the asynchronous determination output of the synchronization means; a memory that takes the calculation result as an address input and generates a translation output; and a memory that inputs the timing pulse and the translation output to detect errors in the data signal. In the code synchronization circuit, the synchronization means includes a second synchronization circuit that determines word synchronization based on an initial syndrome calculation value and a syndrome calculation value when word synchronization is established; A code synchronization circuit comprising: an AND circuit that performs an AND operation of each output of the first and second synchronization circuits.