JPH0393312A - Pll digital synthesizer - Google Patents

Abstract

PURPOSE:To increase a bit number of a channel setting data without using plural IC memories by outputting data of a single memory storing the channel setting data in time division and latching the data. CONSTITUTION:When a channel is set by a channel setting switch 31, a code conversion circuit 32 gives an address data to an 10 memory 33 in response to a switch signal. In this case, part of the address of the 1C memory 33 is given from a latch control circuit 35 to switch the address of the IC memory 33 in steady-state. Thus, the data of the IC memory 33 is outputted in time division and the data of the IC memory 33 is given in parallel with inputs of plural latch circuits 36a, 36b.... Thus, bit number of a channel setting data is increased without using the plural IC memories.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PLL digital synthesizer used as a tuning circuit for, for example, a satellite broadcasting transceiver.

[Prior Art] As a known synthesizer using a PLL, there is a synthesizer as shown in FIG. In FIG. 2, l1 is a reference oscillator, l2 is a phase comparator, 13 is a low-pass filter, l4 is a voltage controlled oscillator, l5 is a brise scaler, and 1B is a programmable frequency divider. In such a configuration, the desired frequency is set by applying frequency division data to the data input of the variable frequency divider.

By the way, if the setting frequency is made more accurate, the number of bits of the channel setting data increases. Furthermore, the number of bits of one data required for each channel setting such as band switching, CH display, etc. tends to increase more and more. Recently, it has become common sense to provide such data from a microcomputer, but in small-scale systems or unmanned systems where runaway programs are not allowed, data is provided directly from IC memory (ROM). is often given.

The problem in this case is that the maximum number of bits of data that can be read by setting an address in one IC memory is 8 bits, and anything larger than that is not versatile or marketable.
There are things that are impossible to do manually at low cost.

Here, FIG. 3 shows a conventional method when data of 8 bits or more is required. In FIG. 3, 2l is a channel setting switch, 22 is a cord replacement circuit, and 23a and 23b are IC memories (ROM). That is, conventionally, data of 8 bits or more was obtained by increasing the number of IC memories.

[Problems to be Solved by the Invention] As described above, conventionally, multiple IC memories have been used to increase the number of bits of channel setting data. However, in such a configuration using multiple IC memories, one set of synthesizers requires a set of IC memories written with multiple different data, which makes IC memory management complicated and complicated. , there have been problems such as poor usage efficiency of IC memory and cost performance.

The present invention has been made in view of the above points, and an object of the present invention is to provide a PLL digital synthesizer that can increase the number of bits of channel setting data without using multiple IC memories.

[A Thousand Steps to Solve the Problem] That is, the PLL digital synthesizer according to the present invention causes a single memory that stores channel setting data to output data in this memory in a time-division manner, and outputs data in this memory in a time-division manner. It is designed to latch the data.

[Operations] According to the above configuration, memory data is outputted in a time-division manner by the clock signal, and the desired number of data pits can be obtained by the latch.

[Embodiment] A PLL digital synthesizer according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the circuit configuration thereof.

In FIG. 1, the channel setting switch 31 is
This is a switch for setting the channel of the L digital synthesizer. The code conversion circuit 32 outputs address data for accessing the IC memory 33 in response to a switch signal from the channel setting switch 3l. The IC memory 31 stores channel setting data.
It's OM.

A clock generator 34 generates a clock signal.

The latch control circuit 35 includes a plurality of latch circuits 36a1.3
[It is a circuit that controls ib..., and it is a clock signal!
．． -iJ period and outputs a latch pulse. Latch circuit.
{6a, 3Gb, . . . under the control of the latch control circuit 35, latches the output data of the IC memory 33 in synchronization with the latch pulse. In addition, filters 37a, 37b...
・When the latch circuits 36a, 38b... are latched,
This is to remove glitches that appear in the data.

Next, the operation of this embodiment will be explained.

When a channel is set by the channel setting switch 3l, the code conversion circuit 32 provides address data to the IC memory 33 in accordance with the switch signal. At this time, part of the address of the IC memory 33 is given from the latch control circuit 35, and the address of the IC memory 33 is constantly switched. As a result, the data in the IC memory 33 is output in a time-division manner.

The data in this IC memory 33 is stored in a plurality of latch circuits 36.
a. 36b... in parallel. The latch circuits 36a, 36b, . . . latch data in the IC memory 33 at the rising edge (or falling edge) of the latch pulse. In this case, the memory data is time-divisionally outputted by the latch pulse of the latch control circuit 35, so from the latch circuits 36'a, 3 (ib...),
The latch data is constantly passed through the filters 37a and 37 in parallel.
b... is output. Filter 37a137b...
represents glitches that appear in the data when latched.

In this way, memory data is outputted in a time-division manner using the clock signal, and the desired number of data pits can be obtained using the latch. Therefore, one PLL synthesizer can be supported with only I11-IC memory, and compared to the conventional system which requires multiple IC memories, it is a PLL synthesizer that has easier memory management, higher memory usage efficiency, and higher cost performance. can be realized.

[Effects of the Invention] As described above, according to the present invention, the number of bits of channel setting data can be increased without using a plurality of IC memories.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention, and FIGS. 2 and 3 are block diagrams showing the circuit configuration of a conventional PLL synthesizer, respectively. 31... Channel setting switch, 32... Code conversion circuit, 33... IC memory, 34... Clock generator, 35... Latch control circuit, 36a. 36b・
...Latch circuit, 37a, 37b...filter.

Claims (1)

[Claims] A single memory storing channel setting data, a data output control means for outputting data in this memory in a time-division manner, and a data output control means for outputting data in a time-division manner from the memory by the data output control means. A PLL digital synthesizer characterized by comprising a latch means for latching.