JPH0393220A - Formation of crystalline thin film and manufacture of semiconductor device - Google Patents

Formation of crystalline thin film and manufacture of semiconductor device

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Publication number
JPH0393220A
JPH0393220A JP22915489A JP22915489A JPH0393220A JP H0393220 A JPH0393220 A JP H0393220A JP 22915489 A JP22915489 A JP 22915489A JP 22915489 A JP22915489 A JP 22915489A JP H0393220 A JPH0393220 A JP H0393220A
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JP
Japan
Prior art keywords
film
crystal
amorphous
epitaxial growth
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP22915489A
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Japanese (ja)
Inventor
Masahiro Shigeniwa
昌弘 茂庭
Kikuo Kusukawa
喜久雄 楠川
Toru Kaga
徹 加賀
Mitsunori Ketsusako
光紀 蕨迫
Eiji Takeda
英次 武田
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Hitachi Ltd
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Hitachi Ltd
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Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP22915489A priority Critical patent/JPH0393220A/en
Publication of JPH0393220A publication Critical patent/JPH0393220A/en
Pending legal-status Critical Current

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  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To prevent crystalline defects due to seed crystals and to acquire a high quality Si crystalline film by forming a crystalline film on an insulating film and by further forming a crystalline film thereon having a lower crystalline defect density than the crystalline film and the same crystal orientation as that of the crystalline film. CONSTITUTION:A pattern of an SiO2 film 2 is formed on a single crystalline Si substrate 1 and an amorphous Si film 3 is formed on the substrate through electron beam heating evaporation method. Then, heat treatment is applied in super high vacuum to produce solid epitaxial growth. The amorphous Si film 3 is single- crystallized on the film 2 ranging over a width of about 6mum from an end of the film 2. An amorphous Si film on the film 2 which is 6mum or more apart from an end of the film 2 becomes a polycrystalline Si 9. Similarly, electron beam heating evaporation is carried out in super high vacuum; the amorphous Si film 3 is formed on an Si film 10 which is deposited previously; heat treatment is carried out; and solid epitaxial growth is caused which proceeds in a longitudinal direction using an Si film 7 as seed crystals, which is crystallized in a preceding process. Thereby, a high quality Si crystal which is free from crystal defects can be obtained on an SiO2 film.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置(単体素子,集積回路)の基板と
して用いるS01 (シリコン オン インシュレータ
: Si1icon−On−1nsulafor.広義
ではセミコンダクタ オン インシュレータ:Sesl
conducfor−On−1nsulafor )結
晶の形成方法,および、Sol結晶を用いた半導体装置
の製造方法に関する. 〔従来の技術〕 絶縁摸の上に単結晶Si膜を形成したSOI構造は、将
来のLSIおよび高耐圧デバイスにおける基本構造とし
て期待され、研究されている.いくつかあるSOI形成
技術のうち、固相エピタキシャル或長法は、均一性・再
現性に優れ,最終的に主流となるポテンシャルが高い. このプロセスを第2図を用いて簡単に説明する.単結品
Si基板1上に、部分的に穴をあけた絶縁膜2を形成し
,その上に超高真空蒸着法もしくは化学気相堆積法(C
VD法)を用いて非晶質Si膜3を形成する.これを電
気炉を用い低温(600℃程度)で熱処理すれば、基&
silに接した所から非晶質Si3の単結晶化(同相エ
ピタキシャル成長4)が生じる。成長は絶縁膜2上にま
で及ぶのでSol構造が得られる訳である.戒長に際し
、絶縁臆2の影響で或長端は特殊な結晶面(ファセット
11)で形成される.このファセット11は,或長の速
度や得られる納品の品質を左右する.固相エピタキシャ
ル或長においては,(100)而での戒長、(110)
面での成長,(111)面での或長,の順で結品性が良
いので.(100)ファセットで或長させるのが最も好
ましい訳である.しかし、絶縁膜上では(100)ファ
セットは生じず、その為,次碑の策として(1 1 0
}ファセットで結晶成長させる事になる.その為、基板
面方位に(100)、絶縁吸2開口部の辺の方向に<1
 0 0>を選んでいるのが通常である. この技術のバリエーションとして、第3図に示すような
.P(あるいはAs,B等、単結晶Si中で電気的に活
性な不純物)を高濃度に含んだ非晶[Si5とこれら不
純物を含まない非晶質Si6との2層膜を使う技術があ
る.これは,同相或長Sol領域の面積を拡張する為に
考案された手法である. 固相或長SQLの面積は,固相エピタキシャル或長速度
と非晶質Si3の多結晶化時間との兼合いで決まる.即
ち,ある熱処理時間がたつと,未だ結晶化していない非
晶質Si3が多結晶化し、固相エピタキシャル或長が停
止してしまう.したがって,多結晶化時間までの間にど
れだけ固相成長の横方向成長距離を稼ぐか(=或長の加
速)、が鍵となる*P,As.B等のドーパントを約3
X 1 0”cm−”の濃度で非晶質Siに混入してや
れば,固相成長は速くなるので,広い血積のSOIが得
られる.しかし,不純物濃度が高すぎてLSIには使え
ない.そこで考案されたのが2層膜法で,高不純物濃度
層5で速い成長を実現し.LSI応用にはノン・ドープ
層6を使うというものである(第3図 参照).この場
合も(1 1 0)ファセットで成長する. この手法に係る報告として、特開昭60−245211
号公報、電子情報通信学会技術研究報告81)M87−
163.マテリアルズ・リサーチ・ソサエテイ(Mat
arials I{esearch Society)
のフォール●ミーティング(ト’all Meafin
g)のエクステンデイド・アブストラクツ・セレクテツ
ド・トピックス・イン・エレクトロニツク・マテリアル
ズ 第121頁から第128頁(l{xtended 
AbstractsSelected Topics 
in l(lectronic Materials,
PP.121−128)がある. 従来技術の2層膜法を用いてSONを作り、そこにMO
SFITを作製した我々の実験結果を以下に述べる. 面方位(0 0 1)の単結晶Si基板上に.通常最も
一般的に用いられているLOGOS (ローカルオキシ
デーション オブ シリコン: LocalOxida
tion of Si)法を用いて、厚さ500人のS
iO怠膜パターンを形成した.パターンの辺は[0 1
 0]方向に沿って形成した.この試料を湿式洗浄した
後,背圧1 0”Torrの超高真空室へ導入し、そこ
で900℃、30分間の熱処理をする事により、表向ク
リーニングを行なった.基板温度を100℃にまでドげ
、ただちに電子ビーム加熱蒸着法で基板上にSiを蒸着
し、非晶膜Si膜(厚さ0.2μm)を形成した.その
際、非晶質Si膜の堆積厚さが0−0.05μmの間は
ボロン(H)濃度を3 X 1 0 ”cs−”に、次
の0.05〜0.2μmの間はB濃度を2X10”とす
るように、Bのイオン化ドーピングを併用した.この後
,同じく超高真空中で、450℃、1時間の熱処理を施
し、非晶[Siを緻密化した.この試料を超高真空室よ
り取り出し,電気炉で600℃の熱処理をして固相エピ
タキシャル成長を行なったa S x O x膜パター
ン・エッジに沿って幅5〜8μmのSQLが得られた.
ファセットを調べる為に成長途中の試料をへき関し,ラ
イト(Vrighr)エッチング液(結晶欠陥の選択エ
ッチング液)で軽くエッチングしく非晶質Siの方が速
くエッチングされるので、非晶質Siと結晶化したSi
の境界が顕在化する〉、走査型電子顕微鏡で観察した. 断面を観察すると、第3図(Q)に示すように,成長端
は、低B濃度層,高B濃度層をまたいだ単一のファセッ
トでできている事がわかった.即ち、前記論文と同様に
,上下両肘で同時に横方向威長が生じた. また、試料表面で[0 1 0]方向に45″を威し,
(110)断面で基板表向((001)而)と55゜を
成している事から、或長端は(111)ファセットより
戒っている事がわかる. この後、Sol領域にゲート長1.2μmのnチャネル
MOSFIfT (ソース,ドレイン領域をAsドーピ
ングで形成)を作製し,その電気的特性を評価した.チ
ャネルにおける電子の電界効果移動度が230aj/v
−Sで、通常の一層膜の(1 1 1)ファセット成長
領域に作製したMOSf/HTと同等の結果であった. なお,最近.SiMの厚さを1000人以下に薄くした
SOIにMOS型トランジスタを作製すれば、駆動能力
が向上する等、従来のSiウエハに直接作製したものに
比べて大幅な性能向上が達成できる、との報告があいつ
いでいる.これらの報告においては,試料の作製にあた
り,一旦、電子ビーム・アニール法やレーザ・ビーム・
アニール法,あるいは酸素イオン打込み法などで通常の
厚さ(0.3 pm 〜1 μm)のSQLを作り、こ
れを研磨やドライエッチングなどで削って1000人以
ドに薄くする,という手法がとられている.初めからI
OOOA以下の薄い501を作った例はない. 〔発明が解決しようとする*M3 成長が絶縁膜2上を横方向に進行する501形成は,ウ
エハ全面で縦方向に進行する通常の固相エピタキシャル
成長(第4図参照)とは異なり,成長が局在している.
したがって,結晶化に伴うストレスがここに集中し,結
晶中に結晶欠陥(転位)ができやすい.即ち、完全結晶
を作るのが難しい. 完全結晶の形成を考える時、もう一つ,やはり(100
)面での或長ができないという点が問題となる.結晶性
の一指標として、不純物(Ag)の電気的活性化率を例
にとれば、{工00}面で成長した結晶中では100%
近い値(95%)が得られるのに対し、(1 1 0)
面、(111)面で成長した結晶中では,それぞれ、約
84%,約68%の小さな値しか得られない,もちろん
,ここでは、活性化率の低い方が結晶性が悪い.このデ
ータから、(110)成長は(1 1 1)戊長に比べ
れば結晶性がかなり良いが,しかしまだ、完全とも言え
ない事がわかる.やはり(100)で成長させるのが一
番良い. 本発明の目的は,局在せず、かつ(100}ファセット
で進行する固相エピタキシャル成長を絶縁膜上で実現し
、これにより、高品質な結晶のSQLを均一性・再現性
良く形成する技術を提供する事にある. ところで、Si厚さ1000λ以ドのSOI(超薄膜S
oI)の形成に用いられている手法,即ち,膜を削って
所望の厚さとする手法は、膜厚の制御精度・ウエハ面内
均一性が悪い為、LSI用プロセスとしては現実的でな
い.しかし、初めから超薄膜でSOIができればよいが
,現在のところ,このような技術がない.Iii相エピ
タキシャル成長法では,非晶質Siを0.2μm以下に
薄くすると、戊長様式が(1 1 1)ファセット成長
になってしまう.理想的には(1 0 0)ファセット
或長、少なくとも(1 1 0)ファセット或長でなけ
ればLSIには適用できない. 本発明の他の目的は、削らずに超薄膜Solを形成でき
るプロセス技術を提供する事にある.〔課題を解決する
ための手段〕 上記二つの目的を達或する為に、本発明では、一旦、絶
縁膜2上に単結晶膜7を形成し、これを種結晶として縦
方向の同相エビタキシャル成長を行なう(第l図参照)
. このSOIにデバイスを作製すれば,リーク電流は,1
回目の戒長で作った結晶kII7を流れる成分と、2回
目の成長で作った結晶層8を流れる成分とに分類できる
.前者を低減する為に、P,A s g B等の電気的
に活性な不純物、もしくは,F,Cなどの高い電気陰性
度の元素を一層目7に導入する. 第1回目の成長は(100)ファセット以外のファセッ
トで生じるので,結晶性は完全とは言えない.第2回目
の戒長は(100)ファセットで進行するので,良質な
結晶が得られる.しかし,第一回目の結晶を種結晶に用
いているので、そこでの欠陥がある確率で21!!l目
の結品に侵入してくる.S01に多数の素子を形成すれ
ば、そのうちの何個かがこれと遭偶する事になる.この
欠陥の侵入を止め、完全な結晶を得る為に、Ge,Sn
等のSiより原子半径の大きな原素を第二層目8に導入
する. 〔作用〕 本発明は,第1図に示すように,絶縁膜2上に形成した
種結晶層7を種として,縦方向成長でSolを形成する
.縦方向成長はウエハ全面で同時に起こるため,結晶化
に伴うストレスが分散され,結晶欠陥(転位)が発生し
にくい.また,種結晶7表面を(100)面(即ち、基
板工面方位を(100)にした縦方向成長は、(100
)面での成長が生ずる.(100)面での成長は,最も
高品質な結晶が得られる或長様式である.ストレスの分
散と.(100)様式成長の2つの実現により、極めて
高品質なSolが形成できる.高品質結晶にデバイスを
作れば、動作が速く、リーク電流の少ない高性能デバイ
スを得る事ができる.即ち,本発明で高性能SOIデバ
イスを得る事ができる.しかし、動作にかかわる領域が
ド地の種結晶層′1に達するデバイスでは,横方向成長
で形成されている為ここを流れる分だけリーク電流が若
干増える.特に少ないリーク電流で動作させたいデバイ
ス応用の場合にま、種結晶層7中の電流或分を減にした
い.そこで,P,As.B等の電気的に活性な不純物,
もしくは.F,Cなどの電気陰性度の高い元素を種結晶
層7に導入する.電気的に活性な不純物の導入は種結晶
層7の静電ポテンシャルを変え(リーク電流の担体電待
が正の場合は高く、負の場合は低くする)、リーク電流
の担体電荷がここへ流れ込むのを防ぐ F,Cなどの導
入は、結晶欠陥における電気的に活性な未結合手とこれ
ら不純物との結合で,欠陥の不活性化を実現し,種結晶
層7中でのリーク電流或分の発生(電子・正孔対の発生
)を阻止する.また,欠陥の運動・成長を抑制する. 材料に母材原子(Si)より大きな原子(Os,Sn等
)を混入してやる事は、原子rl!1距IIl′!(格
子,間隔)を平均的に増加させる事を意味している.結
晶に結晶欠陥があるという状況は、局所的に(結晶欠陥
部において)原子間距離が増加している状況である.し
たがって,結晶欠陥を有する稙結晶7上により原子半径
の大きな不純物を導入した結晶或長を行なえば、欠陥に
凝集していた原子間距離の増加分が威長層における平均
的・全体的な原子間距離の増加に転化され,結晶欠陥は
消失する. 〔実施例〕 以下、本発明の実施例を説明する. (実施例1) 面方位(100)の単結晶Si基板1(第1図(a)参
照)上に、厚さ1500人のSins膜2パターンをt
ocos法により形成した.通常の湿式洗浄後、超高真
空中(〜1 0−@P a )で900’C.’30分
の熱処理を行なう事により基板表面を洗浄化し、その後
,ただちに電子ビーム加熱蒸着法により基板上に厚さ3
000人の非晶質Si膜3を形成した.続いて.超高真
空中で600℃、8時間の熱処理を行なった.この熱処
理で周相エピタキシャル成長が生じ、SiOz膜2上、
Sins1!I2端から幅約6μmにわたって非晶質S
i膜3が単結晶化した(第1図(b)).SiOztl
#2端から6μm以上はなれたSiOa膜2上の非晶9
1 S i wAハ8結M S i 9 ニftツタ.
次に、同じく超高真空中で電子ビーム加熱蒸着を行ない
,第1図(c)に示すように、先に堆積したSi膜10
の上に厚さ5000人の非晶質Si膜3を形成した.こ
れを600℃で熱処理する事により,先工程で結品化さ
せたSi膜7を種結品とした縦方向に進行する固相エピ
タキシャル成長を起こした(第1図(d)).これによ
り,結晶欠陥のない高品質なSi結晶をSiOzn%上
に得た(第1圓(e)). (実施例2) 第1図の如き向方位(100)の単結晶Si基板1上に
,厚さ1800人のS i Ox PIA2パターンを
LOCOS法により形成した。これにレジストをかけ,
ドライ・エッチング法でエッチ・バックするという一般
的な平担化技術で基板表面を平粗にした.これに実施例
1にて述べたように,通常の湿式の洗浄を施した後、超
^真空中加熱クリーニングを行ない,清浄化した.この
上に、超^真空中電子ビーム加熱蒸着法で厚さ300λ
の非晶質Si膜3を形成し(第5図(a)).600℃
、10時間の熱処理を行なう事により固相エピタキシャ
ル成長で上記非晶質Si膜3を単結品化(7)した(第
5図(b)). 引き続き、超烏真空中で電子ビーム加熱蒸着を行ない、
厚さ700λの非晶質Si膜3を形成し(第5図(c)
).再zsoo℃の熱処理(30分間)を行ない,先工
程で結晶化させたSi膜7を種結晶とした縦方向或長の
固相エピタキシャル成長を起こし(第5図(d)).S
i[3の単結晶化を完遂した.これにより、結晶欠陥の
ない高品質な超薄[Si結晶をSi(la膜上に得た(
第5圓(e)). (実施例3) 第1111の如き曲方位(100}の単結晶Si基板1
上に厚さ1500人のSing膜2のパターンをLoc
us法により形成した.通常の湿式洗浄後、超高真空中
熱処理で基板表面清浄化を行ない.電子ビーム加熱蒸着
法で厚さ2000人の非晶質Si[3を堆積した. これに、40keV・l.75X10”aa″″280
keV  ・ 3.25XIO 五”cm−”,160
keV− 9.5 X 1 0”ai−”(F)条件テ
P(’J ン) ヲイytン打込みし,膜中のP濃度を
5XIO▲7国″″8とした(加速エネルギーをかえて
複数目のイオン打込みをしているのは、膜中のp4度を
一定にする為である.).なお、イオン打込みの為に、
試料を超高真空室から取り出さねばならないが、この際
不用意に取り出せば、大気中の酸素や水分子が非晶質S
 i @ 3中へ侵入してくる.これらは,固相エビタ
キシャル威長の阻害因子であるので,本実施例では、S
i蒸着の直後にそのまま超島真空中で低温(450℃)
の熱処理を行ない(1時間)、非晶質Si膜3を緻密化
して(0,HzOの拡散を無視できるくらいにまで遅く
する)この問題を解決している. この試料を電気炉で、600℃、8時間の熱処理(Na
雰囲気中)し、横方向固相エピタキシャルで非晶質Si
膜3を単結品化した(この単結晶化の後でPイオン打込
みとPの活性化の為の950℃、30分間の熱処理を行
なってもよい.)。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a silicon-on-insulator (S01) used as a substrate for a semiconductor device (single element, integrated circuit).
(conductfor-on-1nsulafor) relates to a method of forming a crystal and a method of manufacturing a semiconductor device using a Sol crystal. [Prior Art] An SOI structure in which a single-crystal Si film is formed on an insulator is expected to be a basic structure for future LSIs and high-voltage devices, and is being studied. Among several SOI formation techniques, the solid-phase epitaxial growth method has excellent uniformity and reproducibility, and has a high potential to eventually become mainstream. This process will be briefly explained using Figure 2. An insulating film 2 with holes partially formed is formed on a single-crystalline Si substrate 1, and ultra-high vacuum evaporation method or chemical vapor deposition method (C
An amorphous Si film 3 is formed using the VD method. If this is heat treated at a low temperature (about 600℃) using an electric furnace, the base &
Single crystallization (in-phase epitaxial growth 4) of amorphous Si3 occurs from the point in contact with sil. Since the growth extends to the top of the insulating film 2, a Sol structure is obtained. During lengthening, some long ends are formed with special crystal planes (facets 11) due to the influence of the insulation layer 2. This facet 11 influences the speed of a certain length and the quality of the delivery obtained. In solid phase epitaxial growth, (100) and (110)
Growth on the surface and a certain length on the (111) surface are good in that order. It is most preferable to lengthen it with a (100) facet. However, (100) facets do not occur on the insulating film, so as a next step, (1 1 0
}Crystals will grow with facets. Therefore, (100) in the direction of the substrate surface and <1 in the direction of the side of the insulating suction 2 opening.
0 0> is usually selected. A variation of this technique is shown in Figure 3. There is a technology that uses a two-layer film of amorphous [Si5] containing a high concentration of P (or impurities that are electrically active in single crystal Si, such as As and B) and amorphous Si6 that does not contain these impurities. .. This is a method devised to expand the area of the in-phase long Sol region. The area of the solid phase long SQL is determined by the balance between the solid phase epitaxial growth rate and the polycrystallization time of amorphous Si3. That is, after a certain heat treatment time elapses, amorphous Si3, which has not yet been crystallized, becomes polycrystalline, and solid phase epitaxial growth stops. Therefore, the key to *P,As. About 3 dopants such as B
If it is mixed into amorphous Si at a concentration of However, the impurity concentration is too high to be used in LSI. Therefore, a two-layer film method was devised, which achieved fast growth in the high impurity concentration layer 5. For LSI applications, a non-doped layer 6 is used (see Figure 3). In this case as well, it grows with (1 1 0) facets. As a report related to this method, JP-A-60-245211
No. Publication, Institute of Electronics, Information and Communication Engineers Technical Research Report 81) M87-
163. Materials Research Society (Mat
arials I {esearch Society)
's Fall ●Meafin
g) Extended Abstracts Selected Topics in Electronic Materials pages 121 to 128 (l{extended
AbstractsSelected Topics
in l(electronic Materials,
PP. 121-128). SON is made using the conventional two-layer film method, and MO is added thereto.
The experimental results of our fabrication of SFIT are described below. on a single crystal Si substrate with plane orientation (0 0 1). The most commonly used LOGOS (Local Oxidation of Silicon)
Using the tion of Si method, the thickness of 500
An iO laziness pattern was formed. The sides of the pattern are [0 1
0] direction. After this sample was wet-cleaned, it was introduced into an ultra-high vacuum chamber with a back pressure of 10" Torr, where it was heat-treated at 900°C for 30 minutes to perform surface cleaning. The substrate temperature was raised to 100°C. Immediately, Si was deposited on the substrate by electron beam heating evaporation to form an amorphous Si film (thickness: 0.2 μm). B ionization doping was used in conjunction with boron (H) concentration of 3 x 10 ``cs-'' for 0.05 μm and 2 x 10'' for the next 0.05 to 0.2 μm. .. Thereafter, heat treatment was performed at 450°C for 1 hour in the same ultra-high vacuum to densify the amorphous [Si]. This sample was taken out of the ultra-high vacuum chamber and heat-treated at 600°C in an electric furnace to obtain an SQL with a width of 5 to 8 μm along the pattern edge of the aS x Ox film that was subjected to solid phase epitaxial growth.
To examine the facets, separate the sample during growth and lightly etch it with a Vright etching solution (selective etching solution for crystal defects). converted into Si
The boundaries of Observation of the cross section revealed that the growth edge was made up of a single facet that spanned the low B concentration layer and the high B concentration layer, as shown in Figure 3 (Q). In other words, similar to the previous paper, lateral height was generated at both the upper and lower elbows at the same time. Also, by applying 45″ in the [0 1 0] direction on the sample surface,
Since the (110) cross section forms an angle of 55° with the surface of the substrate ((001)), it can be seen that the long end is more sensitive than the (111) facet. Thereafter, an n-channel MOSFIfT (source and drain regions formed by As doping) with a gate length of 1.2 μm was fabricated in the Sol region, and its electrical characteristics were evaluated. The field effect mobility of electrons in the channel is 230aj/v
-S, the results were comparable to those of MOSf/HT fabricated in the (1 1 1) facet growth region of a normal single-layer film. In addition, recently. By fabricating MOS transistors on SOI with a SiM thickness of less than 1,000 nm, it is possible to achieve significant performance improvements, such as improved drive capability, compared to those fabricated directly on conventional Si wafers. Reports are coming in. In these reports, electron beam annealing or laser beam annealing is used to prepare the sample.
A common method is to create an SQL with a normal thickness (0.3 pm to 1 μm) using an annealing method or an oxygen ion implantation method, and then reduce it to a thickness of 1,000 or more by polishing or dry etching. It is being done. I from the beginning
There is no example of a thin 501 made below OOOA. [The invention seeks to solve *M3 501 formation in which growth progresses horizontally on the insulating film 2 is different from normal solid-phase epitaxial growth (see Figure 4) in which growth progresses vertically over the entire wafer surface. Localized.
Therefore, the stress associated with crystallization is concentrated here, and crystal defects (dislocations) are likely to occur in the crystal. In other words, it is difficult to make perfect crystals. When considering the formation of a perfect crystal, there is another thing to consider: (100
) The problem is that it is not possible to make a certain length on the surface. Taking the electrical activation rate of an impurity (Ag) as an example of an index of crystallinity, it is 100% in a crystal grown on the {00} plane.
While a close value (95%) is obtained, (1 1 0)
In crystals grown on the (111) plane and (111) plane, only small values of about 84% and about 68% are obtained, respectively.Of course, here, the lower the activation rate, the worse the crystallinity. This data shows that (110) growth has much better crystallinity than (1 1 1) extrusion, but it is still not perfect. As expected, it is best to grow at (100). The purpose of the present invention is to realize solid-phase epitaxial growth on an insulating film that is non-localized and proceeds with (100} facets, and thereby to develop a technology for forming high-quality crystalline SQL with good uniformity and reproducibility. By the way, SOI (ultra-thin film SOI) with a Si thickness of 1000λ or less
The method used to form oI, that is, the method of scraping the film to achieve the desired thickness, is not practical as an LSI process because the control accuracy and uniformity of the film thickness within the wafer surface are poor. However, it would be better if SOI could be made from an ultra-thin film from the beginning, but there is currently no such technology. In the III-phase epitaxial growth method, when amorphous Si is thinned to 0.2 μm or less, the elongated pattern becomes (1 1 1) facet growth. Ideally, it cannot be applied to LSI unless it has (1 0 0) facets or at least (1 1 0) facets or length. Another object of the present invention is to provide a process technology that can form an ultra-thin film of Sol without cutting. [Means for Solving the Problems] In order to achieve the above two objects, in the present invention, a single crystal film 7 is once formed on the insulating film 2, and this is used as a seed crystal to generate vertical in-phase epitaxial Growth (see Figure 1)
.. If a device is fabricated on this SOI, the leakage current will be 1
It can be classified into a component flowing through the crystal kII7 formed in the second growth and a component flowing through the crystal layer 8 formed in the second growth. In order to reduce the former, electroactive impurities such as P, A s g B, or elements with high electronegativity such as F and C are introduced into the first layer 7. Since the first growth occurs on facets other than the (100) facet, the crystallinity cannot be said to be perfect. The second Kaicho process proceeds with the (100) facet, so high-quality crystals can be obtained. However, since the first crystal is used as a seed crystal, the probability of a defect occurring there is 21! ! It invades the first product. If a large number of elements are formed in S01, some of them will encounter this element. In order to prevent this defect from entering and obtain a perfect crystal, Ge, Sn
An element with a larger atomic radius than Si, such as Si, is introduced into the second layer 8. [Function] As shown in FIG. 1, the present invention forms Sol by vertical growth using the seed crystal layer 7 formed on the insulating film 2 as a seed. Because vertical growth occurs simultaneously over the entire surface of the wafer, the stress associated with crystallization is dispersed and crystal defects (dislocations) are less likely to occur. Further, vertical growth with the surface of the seed crystal 7 set to the (100) plane (that is, the substrate plane orientation is set to the (100)
) growth occurs. Growth on the (100) plane is a certain elongated mode that yields the highest quality crystals. Dispersion of stress. The two realizations of (100) modal growth allow the formation of extremely high quality Sol. By making devices using high-quality crystals, it is possible to obtain high-performance devices that operate quickly and have low leakage current. That is, a high-performance SOI device can be obtained with the present invention. However, in devices where the region involved in operation reaches the seed crystal layer '1, which is formed by lateral growth, the leakage current increases slightly by the amount of current flowing there. Particularly in the case of device applications where operation with small leakage current is desired, it is desirable to reduce the current in the seed crystal layer 7 by a certain amount. Therefore, P.As. electrically active impurities such as B,
or. Elements with high electronegativity such as F and C are introduced into the seed crystal layer 7. The introduction of electrically active impurities changes the electrostatic potential of the seed crystal layer 7 (it becomes higher when the leakage current carrier potential is positive, and lower when it is negative), and the leakage current carrier charge flows into it. The introduction of F, C, etc. achieves the inactivation of defects by coupling electrically active dangling bonds in crystal defects with these impurities, and reduces leakage current in the seed crystal layer 7. (generation of electron-hole pairs). It also suppresses the movement and growth of defects. Mixing atoms (Os, Sn, etc.) larger than the base material atom (Si) into the material is an atom rl! 1 distance IIl'! It means to increase (lattice, spacing) on average. A situation where a crystal has a crystal defect is a situation where the interatomic distance locally increases (at the crystal defect area). Therefore, if an impurity with a larger atomic radius is introduced onto the base crystal 7 that has crystal defects and the crystal is lengthened, the increase in the distance between atoms aggregated in the defects will increase the average and overall atomic distance in the Icho layer. This is converted into an increase in the distance between crystals and the crystal defects disappear. [Examples] Examples of the present invention will be described below. (Example 1) On a single crystal Si substrate 1 (see FIG. 1(a)) with a plane orientation of (100), two patterns of Sins films with a thickness of 1500 μm were deposited.
It was formed by the ocos method. After normal wet cleaning, 900'C. in an ultra-high vacuum (~10-@Pa). The substrate surface was cleaned by heat treatment for 30 minutes, and then a 3-thickness layer was immediately deposited on the substrate by electron beam heating evaporation.
000 amorphous Si film 3 was formed. continue. Heat treatment was performed at 600°C for 8 hours in an ultra-high vacuum. This heat treatment causes circumferential epitaxial growth, and on the SiOz film 2,
Sins1! Amorphous S over a width of about 6 μm from the I2 end
The i-film 3 became a single crystal (Fig. 1(b)). SiOztl
#2 Amorphous 9 on SiOa film 2 separated by 6 μm or more from the edge
1 S i wAha 8 knots M S i 9 Nift ivy.
Next, electron beam heating evaporation was performed in the same ultra-high vacuum, and as shown in FIG. 1(c), the previously deposited Si film 10 was
An amorphous Si film 3 with a thickness of 5,000 wafers was formed on top of the wafer. By heat-treating this at 600°C, vertically progressing solid-phase epitaxial growth occurred using the Si film 7 crystallized in the previous step as a seed crystal (Fig. 1(d)). As a result, a high-quality Si crystal without crystal defects was obtained on SiOzn% (first circle (e)). (Example 2) A Si Ox PIA2 pattern with a thickness of 1800 wafers was formed by the LOCOS method on a single crystal Si substrate 1 with the (100) orientation as shown in FIG. Apply resist to this,
The substrate surface was made flat and rough using a common flattening technique called etch-back using dry etching. As described in Example 1, this was subjected to normal wet cleaning and then heated cleaning in an ultra-vacuum to clean it. On top of this, a layer with a thickness of 300λ was deposited using an ultra-vacuum electron beam heating evaporation method.
An amorphous Si film 3 is formed (FIG. 5(a)). 600℃
By performing heat treatment for 10 hours, the amorphous Si film 3 was made into a single crystal by solid phase epitaxial growth (7) (FIG. 5(b)). Subsequently, electron beam heating evaporation was performed in a super-vacuum,
An amorphous Si film 3 with a thickness of 700λ was formed (Fig. 5(c)).
). Heat treatment (30 minutes) at 30° C. is performed again to cause solid phase epitaxial growth in the vertical direction using the Si film 7 crystallized in the previous step as a seed crystal (FIG. 5(d)). S
Completed single crystallization of i[3. As a result, a high quality ultra-thin [Si crystal with no crystal defects was obtained on a Si(la film)].
Fifth circle (e)). (Example 3) Single crystal Si substrate 1 with a curved orientation (100} such as 1111)
Loc the pattern of Sing film 2 with a thickness of 1500 people on top.
It was formed by the US method. After normal wet cleaning, the substrate surface is cleaned using heat treatment in an ultra-high vacuum. Amorphous Si [3] was deposited to a thickness of 2000 nm by electron beam heating evaporation. In addition, 40 keV・l. 75X10"aa""280
keV ・3.25XIO 5"cm-", 160
keV-9.5 The reason why multiple ion implantations are performed is to keep the p4 degree in the film constant.) In addition, for ion implantation,
The sample must be taken out of the ultra-high vacuum chamber, but if you take it out carelessly, oxygen and water molecules in the atmosphere may turn into amorphous S.
i @ 3 invades inside. These are factors that inhibit the solid-phase epitaxial growth, so in this example, S
Immediately after the i-evaporation, low temperature (450°C) is carried out in a super island vacuum.
This problem was solved by performing heat treatment (for 1 hour) to densify the amorphous Si film 3 (slowing down the diffusion of 0, HzO to a negligible level). This sample was heat-treated in an electric furnace at 600°C for 8 hours (Na
atmosphere) and amorphous Si in lateral solid-phase epitaxial
The film 3 was formed into a single crystal product (after this single crystal formation, heat treatment at 950° C. for 30 minutes may be performed for P ion implantation and P activation).

再度,基板表面の清浄化を行なった後、超高真空中での
電子ビーム加熱蒸着法により厚さ7000λの非晶[S
i3を堆積した.次いで,600℃,30分間の熱処理
を行ない、ド地の単結晶SiW47を種結晶とした、縦
方向に進行する固相エピタキシャル威長を第1図(d)
に示す如く起こし、高品質なSi結晶ISI8をSin
s膜2上に得た.なお,Pにかえて、As,Bで同様の
実験を行ない,本発明の有効性をAs,Bでも確認した
.(実施例4) 第1図の如き面方位(100)の単結晶Si基板l上に
厚さ1800λのS i Ox膜2パターンをLOCO
S法により形成した.通常の湿式洗浄後.超高真空中で
Arスパッタ・エッチングと800’C.30分の熱処
理を行なって基板表面を清浄化した.ただちに、超高真
空中での電子ビーム加熱蒸着を行ない、基板上に厚さ2
000人の非晶質Si膜3を形成した.これに、4 0
 k e V−1.05X10”as−”,80kaV
−1.95X10”z−”160keV・5.7X10
”(!1″″エの条件でP(リン)をイオン打込みし、
膜中のP濃度を3X10”Oam−’とした. 本実施例においても、実施例3と同様,試料を大気中に
取り出す前に緻密化の為の低温熱処理(450℃,1時
1ffl)を行なっている.イオン打込み後,電気匁i
で600℃、10時間の熱処理(N2#囲気中)シ,横
方向固相エピタキシャル成長を行なった* P g A
 !! y H等のSiにとってドーバントになる不純
物が約IXIO”’(Jl−”以上入った場合は,固相
エピタキシャル或長が促進されるので、本実施例でも約
20μmと長い横方向成長が得られた. 再度.基板表面の清浄化を行なった後,超高真空中での
電子ビーム加熱蒸着法により厚さ8000人の非晶質S
i3を堆積した.次いで,600℃.40分間の熱処理
を行ない、ド地の単結品Si膜7を種結晶とした縦方向
に進行する固相エピタキシャル成長を第115!I (
d)に示す如く起し、^品質なSi結晶膜8をSing
膜2上に得た.なお、P,Hでも同様に本発明が有効で
ある事を実験で確認した. (実施例5) 面方位(100)の単結晶Si基板1上に、第5図の如
く厚さ1 700λのSift膜2ノ1ターンをLOC
OS法により形成した.一般的な平坦化技術を用い,こ
の基板表面を平坦にした.基板表面の清浄化を行なった
後、Pのイオン化ドーピングを併川した超^真空中での
電子ビーム加熱蒸着を行ない、基板上に厚さ200人で
Pを3X10”3−a含んだ非晶質Si膜3を形成した
(第5図(a)).これを600℃で10時間熱処理し
,固相エピタキシャル或長で膜3の単結晶化を行なった
(第5図(b)). ひき続き、超高真空中で電子ビーム加熱蒸着を行ない,
厚さ600人の非晶貿Si膜3を形成した(第5図(c
)).これを再び600℃で熱処理(30分間)して第
5図(d)に示す如く、上記の工程で結晶化させたSi
膜7を種結晶とした縦方向或長の同相エビタキシャル成
長を起こし、2度目に堆積した非晶質Si膜3を結晶化
した.これにより高品質なSi超薄膜結晶8をSins
膜上に得た(第5図(a)). なお,Pに替えて.As,Bでも同様の実験を行ない,
本発明が問様に有効である事を確認した.(実施例6) 実施例5と同様のプロセスをPIA度3XlO”03−
J1で行ない,高品質なSi超薄膜結晶8をSi021
!112上に得た.さらに、Pに替えてAs,Bでも同
様の実験を行ない,同様にして高品質なSi超薄膜結晶
8をSiOxlM2上に得た.(実施例7) 面方位(100)の単結晶Si基板1上に、第1図の如
く厚さ1500人のSing膜2パターンをLOCOS
法により形成した.通常の湿式洗浄後、超高真空中熱処
理で基板表面清浄化を行なった.その後,Siをソース
とした超高真空中での電子ビーム加S#着により厚さ2
000人の非晶質Si膜3を堆積した.これを600℃
で7時間の熱処理し,横方向固相エピタキシャル或長を
おこして単結晶化した.これにイオン打込みする事によ
りF(フッ素)をIXIO”elm″″a導入した.ト
゛を固相エピタキシャル成長層7の納品欠陥に充分行き
渡tfる為に900℃で30分の熱処瑚をし、第一層目
Siloの欠陥の不活性化処理を施した.この後、基板
表面の清浄化を行ない,続いて超高真空中での電子ビー
ム加熱蒸着で厚さ7000人の非晶’IYSi3を堆積
した.これを600℃で30分間の熱処理(超高真空中
)を行なう事により、第1図(d)に示す要領で、縦方
向の固相エビタキシャル成長をおこし,単結晶化した.
これにより、Sift膜2上に高品質なSi結晶膜8を
得た. (実施例8) 第5図,第61l!Iを参照して説明する.面方位(1
00)の単結晶Si基板1の上に,厚さ1500人のS
iOz膜2パターンをLOCOS法により形成し、これ
を一般的な平坦化技術で平坦化した.通常の湿式洗浄後
、超高真空中熱処理により基板表面を清浄化し,超高真
空中の電子ビーム加熱蒸着により厚さ300Aの非晶g
tSi膜3を堆積した(第5図(a)).600℃,1
0時間の熱処理による固相エピタキシャル成長でこれを
単結晶化した(第5図(b)).次にここにFをイオン
打込みで導入するが、300人のごく表面層に直接打ち
込むのは難しい.そこで、一旦、CvL)法でこの上に
厚さ1700λのSift膜13を形成し、これを通し
てFイオンを打込んだ(第6図).Si膜7中のF濃度
は5×10五’ Cal − ”である.これを900
℃で30分間の熱処理し、FをSi膜7中の結晶欠陥に
充分行き渡らせた(第IMISilo中の欠陥の不活性
化). HF水溶液に浸してCVD−SiOafl!J13を除
去した後、通常の湿式洗浄を超高真空中加熱の組みあわ
せによる基板表面清浄化を行なった。この基板の表而に
,超高真空中の電子ビーム加熱蒸着で厚さ700人の非
晶質Si3を堆積した(第51pl(c)).600℃
で30分間の熱処理を行なう事により、第1図(d)に
示す如く,縦方向の固相エビタキシャル成長をおこし(
第5図(d)).SiOx膜2上に高品質なSi超薄膜
結晶8を得た(第5図(e)). (実施例9) 面方位(Zoo)の単結晶Si基板l上に、厚さ150
0λの5iOx膜2パターンをLOCOS法で形成し、
これを一般的で平坦化技術で平坦にした.その後,通常
の湿式洗浄と超高真空中加熱の組み合せによる基板表面
洗浄化を行なった.そして直ちに、Fのイオン化ドーピ
ングを併用した超高真空中の電子ビーム加熱蒸着を行な
い、基板上に厚さ22OAでFを8X10”cm一8含
んだ非晶質Si膜3を形成した(第5図(a)).これ
を,600℃で10時間の熱処理で横方向の園相エビタ
キシャル成長をおこさせ(第5図(b)).単結晶化し
た. この上に、再度、超高真空中の電子ビーム加熱蒸着で非
晶質Si(厚さ700λ)3を堆積した(第5図(C)
.これを600℃で20分間の熱処理し.第1図(d)
に示す如き要領で縦方向の固相エビタキシャル成長をお
こさせ(第5図(d))、Sins膜2上に高品質な超
薄膜結晶8を得た(第5図(e)). なお,Fには固相エピタキシャル成長を抑制する(成長
速度の減少)効果がある.しかし,本実施例のようにF
濃度がl X 1 0 ”cs−”以ドの場合は,この
効果は小さく,事実上の影響はない.(実施例10) 面方位(l00)の単結晶SiMI板1上に厚さ150
0AのSiOz Ili2パター ンヲLOCOS 法
テ形成した.通常の湿式洗浄と超高真空中加熱の組み合
わせによるクリーニング技術で基板表面を清浄化し、超
高真空中の電子ビーム加熱蒸着により厚さ3000人の
非晶質Si膜3を堆積した.これを、600℃,10時
間の熱処理で誘起した横方向固相エピタキシャル成長で
結晶化した.この上に,11子ビーム蒸着法で厚さ60
00人の非晶IMS i fJ 3を形成し,低温の熱
処理(450℃,1時間)で緻密化した後、イオン打込
み装置へ導入した. 実施例3あるいは4で行なったような多重イオン打込み
により,先工程で結晶化させたSi膜7にほぼ均一にU
e(ゲルマニウム)を導入し,その濃度をIXIO”5
m−δとした.これを600℃で1時間の熱処理する事
により,第7図に示す如く縦方向の固相エピタキシャル
成長で第2回目に堆積したSi層15を結晶化した.こ
の縦方向或長で作った結晶8はGeを含む為、下地種結
晶層7の結晶欠陥を全く引きつがず、極めて高品質な結
晶となった. (実施例11) 而方位(100)の単結晶Si基板1上に厚さ1500
λのSiOz膜2パターンをLO(:OS法で形成した
.通常の湿式洗浄と超高真空中加熱の組み合わせによる
クリーニング技術で基板表面を清浄化し、超高真空中の
電子ビーム加熱蒸着によりpメさ2700人の非晶Jl
¥Si膜3を堆積した.これを,600℃,10時間の
熱処理で誘起した横方向固相エピタキシャル成長で結晶
化した.この上に、電子ビーム蒸着法で厚さ4000λ
の非晶質Si膜3を形成し,低温の熱処理(450℃,
1時間)で緻密化した後、イオン打込み装置へ導入した
.プロジェクト レンジ(Projected1{an
ga (Rp))がΔRpだけ一層目Si7と2層目S
i3との界面より浅くなるように打込みエネルギーを設
定して、Geイオン打込みを行なった(第8図). ここで、上記第8図のGe濃度プロファイルNGeにお
けるピーク濃度を2 X 1 0 ’!’ex−8とし
た.これを600℃で1時間、熱処理する事により、先
に結晶化したS i wj4 7を種結晶とした縦方向
の固相エピタキシャル成長をおこし、2回目に堆積した
非晶質Sij%3を結晶化した,この際,成長に伴って
種結晶から伸びてきた結晶欠陥はGoドープJl15に
ブロツクされてそれより上に行けず、それより上では無
欠陥のSi結晶層となった. Geイオン打込みが一度で済む,実施例10の簡便法で
あ、る.但し,実施例10に比べると若干熱的安定性が
弱いので、高めの熱工程をあまり通さない応用に使うの
が好ましい. (実施例12) 面方位(100)の単結晶Si基板1上に,犀さl50
0人(1) S i O 2wI4ハ9 − ン’t−
 t,acos法t” K)或し,これを一般的な平坦
化技術で平坦にした.その後,通常の湿式洗浄と超高真
空中加熱の組み合わせによる基板表面清浄化を行なった
.この基板上に,超高真空中の電子ビーム加熱蒸着法で
厚さ300人の非晶質Si膜3を形成した(第5図(a
)).600℃の熱処理(10時間行なった)で横方向
固相エビタキシャル成長をおこし,非晶質Si[3を結
晶化シタ(第5図(b)).この後.Gaのイオン化ド
ーピングを併用した超高真空中の電子ビーム加熱蒸着法
で厚さ700λの非晶貿Si膜3を基板上に形成した(
第5図(c)).ae濃度は1.3XIO五〇3″″8
である.この試料を600℃で熱処理(30分間)する
事により、第7図に示すように、縦方向の固相エピタキ
シャル成長をおこし,第5図(d))、2回目に堆積し
た膜15を結晶化した.これにより、結晶欠陥のない超
薄膜Si結品をSift膜2上に得ることができた(第
5図Ce)). (実施例13) 面方位(100)の単結晶Si基板1上に,厚さ160
0人のSiOz膜2パターンをLOCOS法で形成し,
これを一般的な平坦化技術で平坦にした.その後,通常
の湿式洗浄と超高真空中加熱の組み合わせによる基板表
面清浄化を行なった.この基板上に,Hのイオン化ドー
ピングと、Fのイオン化ドーピングを併用したSiの電
子ビーム加熱蒸着を超高真空中で行ない、厚さ270A
の非晶質S i f4 3を形成した(第5図(a))
.このときB濃度、FWA度は、それぞれ,2×10五
7cm−” ( 2 X 1 0 l73″″a),5
×10173−8である.続いて600℃の熱処理(1
0時間)を行ない、横方向同相エピタキシャル成長でこ
れを結晶化した(第5図(b)). この上に、Geのイオン化ドーピングを併用した超高真
空中の電子ビーム加熱蒸着法で,厚さ700人の非晶質
Si膜3を形成したsGa濃度はI X 1 0 ”国
−″6である.この試料を600℃で熱処理(30分間
)する事により、第7L!!4にホす要領で縦方向の固
相エピタキシャル或長をおこし、二回目に堆積した(i
eを含むSiNII15を結晶化し,た.これにより,
結晶欠陥の不活性化されたS i [7を介して,結晶
欠陥のない高品質な超薄膜Si結晶8をSins膜2上
に得る事ができた.HにかえてPでも実験を行ない,有
効性を確認した. (実施例14〉 固相エビタキシー以外の方法で2層目のSi結晶を作っ
た例を述べる.面方位(100)の単結晶Si基板1上
に、厚さ1500AのSiOz*パターンをLOCOS
法で形成した.通常の湿,式洗浄と超高真空中加熱の組
み合せによる基板表面清浄化を行なった.この基板上に
,超高真空中での電子ビーム加熱蒸着により、厚さ27
00Aの非晶質Si膜3を形成した.同じく超高真仝中
で600℃の熱処理(8時間)を行なう事により横方向
固相エピタキシャル成長をおこし,非晶[Si膜3を結
晶化した. この基板の温度を750℃にまであげ,Siの電子ビー
ム加熱蒸着を行なった.基板加熱をしながら超高真空中
で蒸着する技術は分子線エビタキシーと呼ばれ、Siの
堆積と結晶化が同時に進行する.これで,ノ事さ430
0人の単結晶sikI17を基板上に形成した(第9図
). (実施例15) 固相エピタキシー以外の方法で2周目のSi結晶を作製
したもう一つの例を述べる.即ち、2屑目を気相エビタ
キシャル成長で形成した.面方位(100)の単結晶S
i基板1上に、犀さ1500人のSiO怠膜2パターン
をLOCOS法で形成した.通常の湿式洗浄と超高真空
中加熱の組み合せによる基板表面洗浄化を行なった。こ
の基板上に,超高真空中での電子ビーム加熱蒸着法で厚
さ2500入の非晶質81膜3を形成した.同じく超高
真空中で、600℃の熱処理(8時間)を行ない,Wt
方向同相エビタキシャル成長をおこし.非晶質Si膜3
を結晶化した。
After cleaning the substrate surface again, a 7000λ thick amorphous [S
i3 was deposited. Next, heat treatment was performed at 600°C for 30 minutes, and the solid-phase epitaxial growth progressing in the vertical direction using solid single-crystal SiW47 as a seed crystal was shown in Figure 1(d).
The high quality Si crystal ISI8 was prepared as shown in the figure below.
Obtained on S membrane 2. In addition, instead of P, similar experiments were conducted with As and B, and the effectiveness of the present invention was also confirmed with As and B. (Example 4) Two patterns of SiOx films with a thickness of 1800λ were deposited by LOCO on a single crystal Si substrate l with a plane orientation (100) as shown in Fig. 1.
It was formed by the S method. After normal wet cleaning. Ar sputter etching in ultra-high vacuum and 800'C. The substrate surface was cleaned by heat treatment for 30 minutes. Immediately perform electron beam heating evaporation in an ultra-high vacuum to deposit a 2-thick layer on the substrate.
000 amorphous Si film 3 was formed. To this, 40
k e V-1.05X10"as-", 80kaV
-1.95X10"z-"160keV・5.7X10
Ion implanted P (phosphorus) under the conditions of ``(!1''d),
The P concentration in the film was set to 3×10"Oam-'. In this example, as in Example 3, a low-temperature heat treatment (450°C, 1 ffl for 1 hour) for densification was performed before taking the sample out into the atmosphere. After ion implantation, electric momme i
Lateral solid-phase epitaxial growth was performed by heat treatment at 600°C for 10 hours (in an N2# atmosphere) * P g A
! ! If an impurity such as yH that becomes a dopant for Si is present in a length of about IXIO"'(Jl-" or more), solid phase epitaxial growth is promoted, so in this example, a long lateral growth of about 20 μm can be obtained. After cleaning the substrate surface again, amorphous S with a thickness of 8000 nm was deposited using electron beam heating evaporation in an ultra-high vacuum.
i3 was deposited. Then, 600℃. Heat treatment was performed for 40 minutes, and solid phase epitaxial growth proceeding in the vertical direction using the solid single-crystalline Si film 7 as a seed crystal was performed in the 115th! I (
As shown in d), a high quality Si crystal film 8 is formed by Singing.
Obtained on membrane 2. It was also confirmed through experiments that the present invention is equally effective for P and H. (Example 5) On a single crystal Si substrate 1 with a plane orientation (100), two turns of a Sift film with a thickness of 1700λ were LOCized as shown in FIG.
It was formed by the OS method. The surface of this substrate was made flat using a common planarization technique. After cleaning the substrate surface, electron beam heating evaporation in an ultra-vacuum with ionization doping of P was performed to form an amorphous layer containing 3x10"3-a of P with a thickness of 200 mm on the substrate. A quality Si film 3 was formed (FIG. 5(a)). This was heat-treated at 600° C. for 10 hours, and the film 3 was made into a single crystal by solid phase epitaxial growth (FIG. 5(b)). Subsequently, electron beam heating evaporation was performed in an ultra-high vacuum.
An amorphous silicon film 3 with a thickness of 600 mm was formed (Fig. 5(c)
)). This was heat-treated again at 600°C (30 minutes), and as shown in Figure 5(d), the Si crystallized in the above step was
Using the film 7 as a seed crystal, in-phase epitaxial growth with a certain length in the vertical direction was caused, and the amorphous Si film 3 deposited for the second time was crystallized. This allows high-quality Si ultra-thin film crystal 8 to be
was obtained on the membrane (Fig. 5(a)). In addition, instead of P. Similar experiments were conducted with As and B,
We have confirmed that the present invention is effective for the customer. (Example 6) The same process as in Example 5 was carried out using PIA degree 3XlO”03-
J1, high-quality Si ultra-thin film crystal 8 was formed on Si021.
! Obtained on 112. Furthermore, a similar experiment was conducted using As and B instead of P, and a high quality Si ultra-thin film crystal 8 was similarly obtained on SiOxlM2. (Example 7) Two patterns of Sing films with a thickness of 1500 mm were deposited on a single crystal Si substrate 1 with a plane orientation of (100) by LOCOS as shown in Fig. 1.
Formed by law. After normal wet cleaning, the substrate surface was cleaned using heat treatment in an ultra-high vacuum. After that, the thickness of
,000 amorphous Si films 3 were deposited. This is heated to 600℃
After heat treatment for 7 hours, lateral solid-phase epitaxial growth occurred and single crystals were formed. F (fluorine) was introduced into this by ion implantation. In order to sufficiently distribute the fluorine into the defects in the solid phase epitaxial growth layer 7, heat treatment was performed at 900° C. for 30 minutes. The defects in the first layer of Silo were inactivated.After this, the substrate surface was cleaned, and then amorphous 'IYSi3 with a thickness of 7000 nm was deposited by electron beam heating evaporation in an ultra-high vacuum. By heat-treating this at 600°C for 30 minutes (in an ultra-high vacuum), vertical solid-phase epitaxial growth occurred as shown in Figure 1(d), resulting in single crystallization.
As a result, a high quality Si crystal film 8 was obtained on the Sift film 2. (Example 8) Figure 5, 61l! This will be explained with reference to I. Surface orientation (1
00) on a single-crystal Si substrate 1 with a thickness of 1500 nm.
Two patterns of iOz film were formed using the LOCOS method, and this was planarized using a general planarization technique. After normal wet cleaning, the substrate surface is cleaned by heat treatment in an ultra-high vacuum, and amorphous g
A tSi film 3 was deposited (FIG. 5(a)). 600℃, 1
This was made into a single crystal by solid phase epitaxial growth using heat treatment for 0 hours (Figure 5(b)). Next, F will be introduced here by ion implantation, but it is difficult to implant it directly into the surface layer of 300 people. Therefore, a Sift film 13 with a thickness of 1700λ was formed on this film using the CvL method, and F ions were implanted through this film (Fig. 6). The F concentration in the Si film 7 is 5 x 105' Cal -''.
A heat treatment was performed at ℃ for 30 minutes to sufficiently distribute F to the crystal defects in the Si film 7 (inactivation of defects in the IMI Silo). CVD-SiOafl by soaking in HF aqueous solution! After removing J13, the substrate surface was cleaned by a combination of normal wet cleaning and heating in an ultra-high vacuum. On the surface of this substrate, amorphous Si3 was deposited to a thickness of 700 nm by electron beam heating evaporation in an ultra-high vacuum (51st pl(c)). 600℃
By performing heat treatment for 30 minutes at
Figure 5(d)). A high quality Si ultra-thin film crystal 8 was obtained on the SiOx film 2 (Fig. 5(e)). (Example 9) A film with a thickness of 150 mm was deposited on a single crystal Si substrate l with a plane orientation (Zoo).
Two patterns of 0λ 5iOx film are formed by LOCOS method,
This was flattened using common flattening technology. Afterwards, the substrate surface was cleaned using a combination of conventional wet cleaning and heating in an ultra-high vacuum. Immediately, electron beam heating evaporation was performed in an ultra-high vacuum using F ionization doping to form an amorphous Si film 3 containing 8 x 10 cm of F with a thickness of 22 OA on the substrate (No. 5 Figure (a)).This was heat-treated at 600℃ for 10 hours to cause horizontal phase epitaxial growth (Figure 5(b)).It was made into a single crystal. Amorphous Si (thickness 700λ) was deposited by electron beam heating evaporation in vacuum (Fig. 5(C)).
.. This was heat treated at 600°C for 20 minutes. Figure 1(d)
Vertical solid-phase epitaxial growth was caused in the manner shown in Figure 5 (d), and a high quality ultra-thin film crystal 8 was obtained on the Sins film 2 (Figure 5 (e)). Note that F has the effect of suppressing solid phase epitaxial growth (reducing the growth rate). However, as in this example, F
If the concentration is less than l x 10 ``cs-'', this effect is small and has no practical effect. (Example 10) A film with a thickness of 150 mm was deposited on a single crystal SiMI plate 1 with a plane orientation (l00).
A 0A SiOz Ili2 pattern was formed using the LOCOS method. The substrate surface was cleaned using a cleaning technique combining conventional wet cleaning and heating in an ultra-high vacuum, and an amorphous Si film 3 with a thickness of 3000 nm was deposited by electron beam heating evaporation in an ultra-high vacuum. This was crystallized by lateral solid-phase epitaxial growth induced by heat treatment at 600°C for 10 hours. On top of this, a thickness of 60 mm was applied using the 11-beam evaporation method.
After forming an amorphous IMS i fJ 3 and densifying it by low-temperature heat treatment (450°C, 1 hour), it was introduced into an ion implanter. By performing multiple ion implantation as in Example 3 or 4, U is almost uniformly implanted into the Si film 7 crystallized in the previous step.
Introducing e (germanium) and increasing its concentration to IXIO”5
It was set as m−δ. By heat-treating this at 600° C. for 1 hour, the Si layer 15 deposited for the second time by vertical solid-phase epitaxial growth was crystallized as shown in FIG. Since this crystal 8 made with a certain length in the vertical direction contains Ge, it does not carry any crystal defects of the underlying seed crystal layer 7, resulting in an extremely high quality crystal. (Example 11) A film with a thickness of 1500 mm was deposited on a single crystal Si substrate 1 with an orientation of (100).
Two patterns of SiOz films with a wavelength of 2,700 amorphous Jl
¥Si film 3 was deposited. This was crystallized by lateral solid-phase epitaxial growth induced by heat treatment at 600°C for 10 hours. On top of this, a thickness of 4000λ was applied using the electron beam evaporation method.
An amorphous Si film 3 of
After being densified for 1 hour), it was introduced into an ion implantation device. Project range (Projected1{an
ga (Rp)) is ΔRp between the first layer Si7 and the second layer S
Ge ion implantation was performed by setting the implantation energy to be shallower than the interface with i3 (Figure 8). Here, the peak concentration in the Ge concentration profile NGe shown in FIG. 8 above is 2 X 10'! 'ex-8. By heat-treating this at 600°C for 1 hour, vertical solid-phase epitaxial growth occurs using the previously crystallized S i wj4 7 as a seed crystal, and the second deposited amorphous Sij%3 is crystallized. However, at this time, the crystal defects that had extended from the seed crystal during growth were blocked by the Go-doped Jl15 and could not go above it, resulting in a defect-free Si crystal layer above it. This is a simple method of Example 10, in which Ge ion implantation is done only once. However, it has slightly lower thermal stability than Example 10, so it is preferable to use it in applications that do not require high heat treatment. (Example 12) Rhinoceros 150
0 people (1) S i O 2wI4ha9 - N't-
This was then flattened using a general flattening technique.Then, the substrate surface was cleaned by a combination of ordinary wet cleaning and heating in an ultra-high vacuum. Then, an amorphous Si film 3 with a thickness of 300 nm was formed by electron beam heating evaporation in an ultra-high vacuum (see Fig. 5(a)).
)). A heat treatment at 600°C (performed for 10 hours) caused lateral solid-phase epitaxial growth, and amorphous Si[3 was crystallized (Fig. 5(b)). After this. An amorphous Si film 3 with a thickness of 700λ was formed on the substrate by electron beam heating evaporation in an ultra-high vacuum using Ga ionization doping (
Figure 5(c)). ae concentration is 1.3XIO503″″8
It is. By heat-treating this sample at 600°C (30 minutes), vertical solid phase epitaxial growth occurs as shown in Figure 7, and as shown in Figure 5(d)), the second deposited film 15 is crystallized. did. As a result, an ultra-thin Si crystal without crystal defects could be obtained on the Sift film 2 (FIG. 5C)). (Example 13) On a single-crystal Si substrate 1 with a plane orientation of (100),
Two patterns of SiOz film were formed using the LOCOS method.
This was flattened using general flattening technology. Afterwards, the substrate surface was cleaned using a combination of conventional wet cleaning and heating in an ultra-high vacuum. On this substrate, electron beam heating evaporation of Si using a combination of H ionization doping and F ionization doping was performed in an ultra-high vacuum to a thickness of 270A.
Amorphous Si f4 3 was formed (Fig. 5(a)).
.. At this time, the B concentration and FWA degree are 2×1057cm-” (2×10173″a), 5, respectively.
×10173-8. Subsequently, heat treatment at 600°C (1
0 hours) and crystallized by lateral in-phase epitaxial growth (Fig. 5(b)). On top of this, an amorphous Si film 3 with a thickness of 700 mm was formed using an electron beam heating evaporation method in an ultra-high vacuum using Ge ionization doping. be. By heat treating this sample at 600°C (30 minutes), the 7th L! ! A vertical solid-phase epitaxial elongation was performed as described in step 4, and the second deposition was carried out (i
SiNII15 containing e was crystallized, and As a result,
A high-quality ultra-thin Si crystal 8 free of crystal defects could be obtained on the Sins film 2 through Si[7 with crystal defects inactivated. We conducted an experiment with P instead of H and confirmed its effectiveness. (Example 14) An example in which a second layer of Si crystal was made by a method other than solid-phase epitaxy is described.A SiOz* pattern with a thickness of 1500A was formed by LOCOS on a single crystal Si substrate 1 with a plane orientation of (100).
Formed by law. The substrate surface was cleaned by a combination of conventional wet cleaning and heating in an ultra-high vacuum. A thickness of 27 cm was deposited on this substrate by electron beam heating evaporation in an ultra-high vacuum.
An amorphous Si film 3 of 00A was formed. The amorphous Si film 3 was crystallized by lateral solid-phase epitaxial growth by heat treatment at 600°C (8 hours) in the same ultra-high temperature environment. The temperature of this substrate was raised to 750°C, and Si was deposited by electron beam heating. The technique of vapor deposition in an ultra-high vacuum while heating the substrate is called molecular beam epitaxy, in which Si deposition and crystallization proceed simultaneously. Now it's 430
A single-crystal sikI17 of 0.00% was formed on the substrate (Fig. 9). (Example 15) Another example in which a second round of Si crystal was produced by a method other than solid phase epitaxy will be described. That is, the second scrap was formed by vapor phase epitaxial growth. Single crystal S with plane orientation (100)
On the i-substrate 1, 2 patterns of SiO thin film of 1500 rhinoceros were formed using the LOCOS method. The substrate surface was cleaned by a combination of conventional wet cleaning and heating in an ultra-high vacuum. On this substrate, an amorphous 81 film 3 with a thickness of 2500 μm was formed by electron beam heating evaporation in an ultra-high vacuum. Similarly, heat treatment at 600°C (8 hours) was performed in an ultra-high vacuum, and Wt
In-phase epitaxial growth occurs. Amorphous Si film 3
was crystallized.

この試料を石英製の反応管に入れ、気相エビタキシャル
成長を行なった.まず初めに,横方向成長で結晶化させ
たSi膜7の表面を洗浄化するために,試料の温度を1
100℃にまヤあげ.Hzガスに30分間さらした.次
に試料温度を1000℃に下げ、反応管中にSiH4ガ
スを流し、SiHaの分解・反応により結晶膜7上にS
iを堆積(1μm)Lた.この条件のもとではSiの堆
積と併行して結晶或長がおこる(気相エピタキシャル成
長)。こうして、横方向成長膜7上に縦方向成長で結晶
換18を得た(第10図). (実施例16) 実施例1にて作製したSol基板上に,多結晶Siゲー
ト、ソース・ドレイン形成にA3もしくはBイオン打込
み,を用いた通常のM O S (Metal−Oxi
de−Semiconductor )   型 ?’
  E  T   (Field−Hffect−Tr
ansisfor :電界効果トランジスター)作製プ
ロセスで,nチャネルMOS − FE’r,Pチャネ
ルM O S − F’ E ’rを作製した(第11
図、それぞれ(a),(b))−ゲート長1.2μmの
ものと、2,4.8μmのものを作った.いずれも、チ
ャネル内電子移動度600d/v−s以上、正孔移動度
200aJ/V−s以上,リーク電流I X 1 0’
″l3A/μm以下の良好な特性を得た. (実施例17) 実施例l3にて作製した超薄膜Sol基板上に,通常の
MOS・?’ E ’r作製プロセスでnチャネルMO
S − Fk:T(8打込み基板),PチャネルMOS
 − 1/E’r(P打込み基板)を作製した(第12
図、それぞれ(a),(b)).ゲート長1.2pmの
もの,4μmのもの,8μmのものを作った.いずれか
らも、チャネル内電子移動度1200aJ/V−s以上
、正孔移動度400a#/V・s以上、リーク電流I 
X 1 0−lsA/μm以ドの良好な索子特性が得ら
れた. (実施例18) 面方位(1 1 0)の単結晶Si基板1を(100)
基板に替えて、実施例1のプロセスを行なった.(10
0)而での縦方向或長のかわりに(1 1 0)面での
縦方向戊長がおき,第工図と同様に横方向成長S i 
M ’/の上に縦方向或長Si層8を得た.(1 1 
0)面での成長であるから,(100)面で成長した実
施例1の縦方向成長M8よりも結晶性の点で弱干見劣り
するが,縦方向成長で成長が,局在していない分.(1
10)ファセットの横方向或長で形成した結晶よりも欠
陥の少ない結晶紛8が得られた. なお、実施例1〜18のいずれにおいても,非晶質Si
膜3の形成に際し,超高真空中蒸着法に替えて,他の非
晶質Si形成法、例えばCvL)法を用いても良い事を
ここに記す. 〔発明の効果〕 本発明によれば、以ドに記載されるような効果を得るこ
とができる. 縦方向の成長、(100)面での成長時、種結晶からの
結晶欠陥侵入が阻止できる事により,高品質なSi結晶
膜を形成できる. さらに、電気的に活性な不純物の導入による種結晶層の
ポテンシャル・コントロール、ド等の導入による種結晶
中の欠陥の不活性化により、種結晶対中の欠陥を実効的
に除去する事ができ、実効的に高品質なSol結晶を形
成できる.上記の効果は,Siの膜厚に無関係に得られ
るので、高品質な超薄1!!I!SOI結晶を得る事が
できる.
This sample was placed in a quartz reaction tube and vapor phase epitaxial growth was performed. First, in order to clean the surface of the Si film 7 that has been crystallized by lateral growth, the temperature of the sample is lowered to 1.
Raised to 100℃. Exposure to Hz gas for 30 minutes. Next, the sample temperature was lowered to 1000°C, SiH4 gas was flowed into the reaction tube, and S was formed on the crystal film 7 by the decomposition and reaction of SiHa.
i was deposited (1 μm). Under these conditions, crystal growth occurs concurrently with Si deposition (vapor phase epitaxial growth). In this way, a crystal 18 was obtained by vertical growth on the horizontally grown film 7 (FIG. 10). (Example 16) On the Sol substrate produced in Example 1, ordinary MOS (Metal-Oxi
de-Semiconductor) type? '
E T (Field-Heffect-Tr
n-channel MOS-FE'r and P-channel MOS-F'E'r were fabricated using the fabrication process (field effect transistor) (11th
Figures (a) and (b)) - Gate lengths of 1.2 μm and 2 and 4.8 μm were made, respectively. In all cases, the in-channel electron mobility is 600 d/v-s or more, the hole mobility is 200 aJ/V-s or more, and the leakage current is IX10'.
Good characteristics of less than 13A/μm were obtained. (Example 17) On the ultra-thin Sol substrate fabricated in Example 13, an n-channel MOS was fabricated using a normal MOS/?'E'r fabrication process.
S-Fk:T (8 implanted board), P channel MOS
- 1/E'r (P implanted substrate) was produced (12th
Figures (a) and (b), respectively). We made gate lengths of 1.2 pm, 4 μm, and 8 μm. In-channel electron mobility is 1200 aJ/V-s or more, hole mobility is 400 a#/V-s or more, and leakage current I
Good cord characteristics of less than X 10-lsA/μm were obtained. (Example 18) Single-crystal Si substrate 1 with (1 1 0) plane orientation is (100)
The process of Example 1 was performed in place of the substrate. (10
Instead of a certain length in the vertical direction at 0), there is a length in the vertical direction on the (1 1 0) plane, and the lateral growth S i
A vertically elongated Si layer 8 was obtained on M'/. (1 1
Since the growth was on the (0) plane, the crystallinity was slightly inferior to the vertically grown M8 of Example 1, which was grown on the (100) plane, but the growth was not localized in the vertical direction. Minute. (1
10) A crystal powder 8 with fewer defects than a crystal formed with a certain length of facets in the lateral direction was obtained. In addition, in any of Examples 1 to 18, amorphous Si
It is noted here that when forming the film 3, other amorphous Si formation methods, such as the CvL method, may be used instead of the ultra-high vacuum vapor deposition method. [Effects of the Invention] According to the present invention, the following effects can be obtained. During growth in the vertical direction or on the (100) plane, it is possible to form a high-quality Si crystal film by preventing crystal defects from entering from the seed crystal. Furthermore, defects in the seed crystal pair can be effectively removed by controlling the potential of the seed crystal layer by introducing electrically active impurities, and by inactivating defects in the seed crystal by introducing doping. , it is possible to effectively form high-quality Sol crystals. The above effects can be obtained regardless of the thickness of the Si film, resulting in a high quality ultra-thin film! ! I! SOI crystals can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図,第5L!fl,第6Ij4,第8図は本発明の
実施例のSQL構造の作或工程を示す断面図、第2図は
横方向固相エビタキシャル成長の状態を示す斜視図、第
3図は従来の2相法によるS01構造の作戒工程を示す
断面図および横方向固相エピタキシャル或長の状態を示
す斜視図,第4図は縦方向固相エビタキシャル成長の状
態を示す断rM!!4、第7図,第9図,第10図はそ
れぞれ本発明の実施例のSOI構造の断面図,第11図
,第12図は本発明の実施例の半導体装置の断面図であ
る.1・・・単結晶Si基板、2・・・絶縁膜、3・・
・非晶質Si、4・・・固相エピタキシャル或長、5・
・・高小純物濃度層,6・・・ノンドープ層,7・・・
種結品として用いる単結晶wIi(横方向成長で作った
結晶膜)、8・・・縦方向成長で作ったSQL結晶,9
・・・多結晶Si、10・・・一回目に堆積したSi層
、11・・・ファセット,12・・・縦方向或長で作っ
たSi結晶,13・・・CVL)で堆積したSiOz.
14・・・フツ索イオン打込み,15・・・Geを導入
したSi層,l6・・・Gaイオン打込み,17・・・
分子線エビタキシーで形成したSi結晶膜,18・・・
気相エビタキシーで形成したSi結晶膜、19・・・ソ
ース電極,20・・・ゲート電極,21・・・ドレイン
電極,22・・・A s A濃度領域,23・・・B高
濃度領域.第 l 口 奉 l 凹 率 3 目 <C) 早 4 町 早 5 口 不 5 會 (e) 3 竪 6 日 弔 7 會 亭 8 口 弔 9 詔 弟 /O 凶 l7 早 1/ 日
Figure 1, 5L! fl, 6Ij4, FIG. 8 is a cross-sectional view showing a process of creating an SQL structure according to an embodiment of the present invention, FIG. 2 is a perspective view showing the state of lateral solid phase epitaxial growth, and FIG. 3 is a conventional A cross-sectional view showing the growth process of the S01 structure by the two-phase method and a perspective view showing the state of lateral solid-phase epitaxial growth, and Figure 4 is a cross-sectional view showing the state of vertical solid-phase epitaxial growth. ! 4, FIG. 7, FIG. 9, and FIG. 10 are sectional views of SOI structures according to embodiments of the present invention, and FIGS. 11 and 12 are sectional views of semiconductor devices according to embodiments of the present invention. 1... Single crystal Si substrate, 2... Insulating film, 3...
・Amorphous Si, 4...Solid phase epitaxial, 5.
... High and small purity concentration layer, 6... Non-doped layer, 7...
Single crystal wIi (crystal film made by lateral growth) used as a seed product, 8...SQL crystal made by vertical growth, 9
... Polycrystalline Si, 10... Si layer deposited for the first time, 11... Facet, 12... Si crystal made with a certain length in the vertical direction, 13... SiOz deposited by CVL).
14...Full ion implantation, 15...Si layer into which Ge is introduced, l6...Ga ion implantation, 17...
Si crystal film formed by molecular beam epitaxy, 18...
Si crystal film formed by vapor phase epitaxy, 19...source electrode, 20...gate electrode, 21...drain electrode, 22...A s A concentration region, 23...B high concentration region. 1st Kuchibōl Concave rate 3<C) Haya 4 Machihaya 5 Kuchibashi 5 Kai (e) 3 Tate 6 Nissho 7 Kaitei 8 Kuchisou 9 Imperial brother/O Kyōl 7 Haya 1/day

Claims (1)

【特許請求の範囲】 1、絶縁膜の上に結晶膜、さらにその上に該結晶膜と同
じ結晶方位で該結晶膜よりも結晶欠陥密度が低い結晶膜
を有することを特徴とする多層膜。 2、上記結晶膜が半導体であることを特徴とする請求項
1記載の多層膜。 3、単結晶基板上に開口部を有する絶縁体膜を形成し、
その上に非晶質膜を形成し、熱処理により該非晶質膜の
一部もしくは全部を単結晶化し、この単結晶膜を種結晶
としたエピタキシャル成長で、該単結晶膜上に結晶薄膜
を形成することを特徴とする結晶薄膜の形成方法。 4、上記単結晶および非晶質材料が半導体であることを
特徴とする請求項3記載の結晶薄膜の形成方法。 成長の方法として、固相エピタキシャル成長法5、上記
単結晶膜を種結晶としたエピタキシヤル成長の方法とし
て、固相エピタキシヤル成長法を用いたことを特徴とす
る請求項3記載の結晶薄膜の形成方法。 6、上記種結晶に用いた半導体に対して電気的に活性化
しうる不純物を該種結晶中に1×1016〜1×10Z
2al−3の濃度で含むことを特徴とする請求項4記載
の結晶薄膜の形成方法。 7、上記種結晶として用いる単結晶薄膜中に、該膜を構
成する元素よりも電気陰性度が高い元素を1×101〜
1×10Z1cs−3の濃度で含有せしめたことを特徴
とする請求項4記載の結晶薄膜の形成方法。 8、上記単結晶半導体膜を種結晶としたエピタキシャル
成長膜中に、該成長膜の構成元素より原子半径の大きな
元素を1X101〜5×10111の濃度で含有せしめ
たことを特徴とする請求項4記載の結晶薄膜の形成方法
。 9、上記請求項4記載の結晶膜を基板として用いたこと
を特徴とする半導体装置の製造方法。 10、面方位(111)±10°以外の単結晶半導体基
板を用いたことを特徴とする請求項4記載の結晶薄膜の
形成方法。
[Claims] 1. A multilayer film comprising a crystal film on an insulating film, and a crystal film on top of the crystal film having the same crystal orientation as the crystal film and lower crystal defect density than the crystal film. 2. The multilayer film according to claim 1, wherein the crystal film is a semiconductor. 3. Forming an insulating film with an opening on a single crystal substrate,
An amorphous film is formed thereon, part or all of the amorphous film is made into a single crystal by heat treatment, and a crystal thin film is formed on the single crystal film by epitaxial growth using this single crystal film as a seed crystal. A method for forming a crystal thin film characterized by the following. 4. The method of forming a crystalline thin film according to claim 3, wherein the single crystal and amorphous materials are semiconductors. Formation of a crystal thin film according to claim 3, characterized in that a solid phase epitaxial growth method 5 is used as a growth method, and a solid phase epitaxial growth method is used as an epitaxial growth method using the single crystal film as a seed crystal. Method. 6. Adding an impurity that can electrically activate the semiconductor used in the seed crystal to 1×1016 to 1×10Z in the seed crystal.
5. The method for forming a crystalline thin film according to claim 4, wherein the crystal thin film is contained at a concentration of 2al-3. 7. In the single crystal thin film used as the seed crystal, an element having a higher electronegativity than the elements constituting the film is added at 1×10
5. The method for forming a crystalline thin film according to claim 4, wherein the crystal thin film is contained at a concentration of 1×10Z1cs-3. 8. The epitaxially grown film using the single crystal semiconductor film as a seed crystal contains an element having a larger atomic radius than the constituent elements of the grown film at a concentration of 1×101 to 5×10111. A method for forming crystalline thin films. 9. A method for manufacturing a semiconductor device, characterized in that the crystal film according to claim 4 is used as a substrate. 10. The method for forming a crystalline thin film according to claim 4, wherein a single crystal semiconductor substrate having a plane orientation other than (111)±10° is used.
JP22915489A 1989-09-06 1989-09-06 Formation of crystalline thin film and manufacture of semiconductor device Pending JPH0393220A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22915489A JPH0393220A (en) 1989-09-06 1989-09-06 Formation of crystalline thin film and manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22915489A JPH0393220A (en) 1989-09-06 1989-09-06 Formation of crystalline thin film and manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0393220A true JPH0393220A (en) 1991-04-18

Family

ID=16887626

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22915489A Pending JPH0393220A (en) 1989-09-06 1989-09-06 Formation of crystalline thin film and manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0393220A (en)

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