JPH0391314A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To prevent the combination with a logical value, to which an input is prohibited, and to prevent an abnormal output from being generated by connecting a prelogic circuit and controlling both inputs to an RS type. CONSTITUTION:A prelogic circuit 4 is connected to an RS type FF 3 and the closing of AND circuits 7 and 9 is controlled through a NAND circuit 6a of the circuit 4. Even when two input signals 5a and 5b are respectively same, logic input signals 2a and 2b going through the circuits 7 and 8 to the FF 3 are not changed so as to be same and the signals 2a and 2b are not the same values as a state that prohibited combination of the FF 3 is executed. Then, the FF 3 is prevented from generating the abnormal output.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a flip-flop circuit (hereinafter, this circuit may simply be referred to as an FF circuit) used for signal processing such as logical operations, and in particular to a flip-flop circuit used for signal processing such as logical operations, and in particular, a flip-flop circuit (hereinafter, this circuit may be simply referred to as an FF circuit). The present invention relates to a circuit that does not cause an abnormal phenomenon in an output signal regardless of the combination of logical values.

[Conventional technology]

FIG. 5 shows four NAND circuits 1ae, lb, and Ic.

6 is a circuit diagram of a conventional R8711 tube 70 tube circuit 2 using 1d, and FIG. 6 is a diagram showing a truth table of the FF circuit 2. In the FF circuit 2, the input terminal S.

There are two logic signals 2a in R due to the combination of logic values shown in each row except the bottom row of FIG.

2b (hereinafter, these signals may be referred to as input signals of the FF circuit 2), output signals 2c and 2d having the logical values shown in FIG. 6 are output to the output terminals Q and Q. In this case, as shown in the bottom row of FIG. 6, the input terminals 8. Logic value b”- on both sides of FL
When the signal 23゜2b, which is r I J, is input, the logical values of the signals 2C and 2d output from the output terminals Q and Q are uncertain, and the output from the terminals Q and Q is uncertain. Since the respective logic values of the signals 2C and 2d are unstable as they fluctuate over time, the signal 2a whose logic values are both "IJ"
It is also known that inputting l2b to the FF circuit 2 is prohibited.

[Problem to be solved by the invention]

When using the R8/F11 block circuit 2 shown in FIG. Since the condition is imposed,
Traditionally, F
Although it is intended to use F circuit 2, as a practical matter, F circuit 2 is intended to be used.
Due to a malfunction of the input circuit of the circuit 2 connected to the front stage of the F circuit 2, carelessness of the engineer in handling the FF circuit 2, etc., both terminals S and R have a logic value due to the I#1 connection. 1. Signals 2a and 2b of 1.1 may be input simultaneously. Therefore, each logical value b1 of output signal 2C92d may change uncertainly or change over time due to the above-mentioned causes. There is a problem that abnormal phenomena such as fluctuations may occur.

An object of the present invention is to prevent both input signals of an RS flip 70-tub circuit from combining logical values prohibited in the 711-tub 70-tub circuit.

No abnormal phenomenon occurs in the output signal regardless of the combination of the respective logical values of the two input signals.

The object of the present invention is to obtain an FF circuit using an R8'71-tube 70-tube circuit.

[Means to solve the problem]

In order to achieve the above object, 1 the present invention includes a two-input, two-output prelogic circuit that inputs both wheel drive signals to the R1S7 rib 70 tube circuit and the RS 71 rib 70 tube circuit, and The circuit outputs the two-wheel logic signal so that when the two input signals have the same logical value, the respective logic values of the two output signals of the R87I + shoes one-foot circuit do not change,
and when the two input signals have different logical values, the R8
The operation of outputting the two wheel control signals is performed such that the combination of the respective logical values of the two output signals of the 7-rib 70-1 circuit is in a manner corresponding to the combination of the respective logical values of the both input signals. 7 constitutes a lip-flop circuit.

[Effect]

With the above configuration, when both input signals input to the front logic circuit have the same logical value, this logic value is "1" and the front logic circuit outputs RS 711917071 due to the action of the -cffiff path. A logical value that does not cause a change in the logical value of the output signal of the circuit, for example, the above-mentioned FF circuit 2 outputs a double wheel control signal with a logical value rOJ, so regardless of the combination of the logical values of the single input signal, one wheel control signal is output. The combination of each logical value of the logical signal is R87I + Tsubu 70
5- R is not in a prohibited manner for the loop circuit, and therefore does not cause an abnormal phenomenon in the output signal regardless of the combination of the logical values of the two input signals.
This means that an FF circuit using 70 S flips in one circuit can be obtained.

〔Example〕

Fig. 1 is a circuit diagram of the first embodiment 30 of the present invention, and Fig. 2 is a circuit diagram of the first embodiment of the present invention.
This is a diagram showing a state transition table of the 7+1 tube 70 tube circuit 3 shown in the figure.
The logic signals 2a and 2 described above are applied to the 711 and 70 circuits 2.
A two-input, two-output pre-logic circuit 4 is provided which inputs the signal b, and this circuit 4 and the FF circuit 2 form an FF circuit 36''-
It is configured. Then, in this case, the logic circuit 4 is.

Input terminal S. , Ro, and terminal S. , Ro, both input signals 5a, 5b6; and a NAND circuit 6 inputted thereto.

The output signal 6a of the circuit 6 outputted from the output terminal F of the NAND circuit 6 and the input signal 5a are input to the logic 411.
AND circuit 7 which outputs logic signal 2a, and AND circuit 8 which receives output signal 6a output from output terminal F and input signal 56-b and outputs logic signal 2b.
It is made up of.

Since the FF circuit 3 is configured as described above.

It is clear that the logical values of the signals at each terminal become as shown in FIG. 2 depending on the combination of the logical values of the input signals 5a and 5b. From figure 2, the 6 balls are
When the input signals 5a and 5b have different logical values, the logical signals 2a and 2b also have different logical values,
The combination of each logic box of these two signals 2a and 2b is
Signal 5a.

The four combinations of each logical value of 5b are rl, 1. ro, I
Dearka rO,I, rlJ Tearkano signal 5a
, 5b, depending on the combination of the respective logical values.

In the FF circuit 3, if the signals 5a and 5b have different logical values, the combination of the respective logical values of the output signals 2c*2d will be in a manner corresponding to the combination of the respective logical values of the input signals 5a and 5b. Logic circuit 4 outputs logic signals 2a and 2b
It can be said that the input signal 5a,
, 5b are the same, even if these logical values are rOJ and 1.1, the logic signals 2a,
As a result, each logical value of 2b becomes "0", and as a result, the FF circuit 3 outputs the signal 5a.

If 5b has the same logical value, the front logic circuit 4 outputs the signals 2a and 2b so that the logical values of the output signals 2C and 2d do not change.
This means that it is possible to output .

According to the configuration of the FF circuit 3, the front logic circuit 4
Because of this action, both logic signals 2a and 2b in combinations of logic values that are prohibited in the FF circuit 2 are not input to the FF circuit 2.

This means that no abnormal phenomenon will occur in the output signals 2C, 2d regardless of the combination of the logical values of both input signals 5a, 5b.

FIG. 3 is a circuit diagram of the second embodiment 90 of the present invention, and FIG. 4 is a circuit diagram of the third embodiment.
FIG. 3 is a diagram showing a state transition table of the 7-request 70-tub circuit 9 shown in the figure. The difference between FIG. 3 and FIG. 1 is that the NAND circuit 1a shown in FIG. 1 and the AND circuit 7 and 01 are integrated to form the NAND circuit 10. The NAND circuit 1b and the AND circuit 8 are integrated to form a NAND circuit 11, and the input circuit that inputs the input signal 5a to the NAND circuit 10 is provided with a signal delay circuit 12 that delays the signal 5a by a predetermined time. and
In this case, the input circuit that inputs the input signal 5b to the NAND circuit 11 is provided with a signal delay circuit 13 that delays the signal 5b by a predetermined period of time.

The delay circuit 12 outputs the signal 5a outputted from the circuit and the output signal 6a of the NAND circuit 6 at almost the same time.
The delay circuit 13 is provided to ensure that the signal 5b output from the circuit and the output signal 6a are input to the NAND circuit 11 at approximately the same time. It is set in. Then, S in FIG. 3 is a terminal provided between the NAND circuit 10 and the NAND circuit 1c, R is a terminal provided between the NAND circuit 11 and the NAND circuit 1d, and in this case, the terminal S, R.

It is clear that the R8FF circuit is composed of Q, Q and the NAND circuits 1c, ld, and in FIG.
It is also clear that the signal 0 logic value at each terminal becomes as shown in FIG. 4 depending on the combination of each logic value of a+5b.

That is, in the FF circuit 9 of FIG. 3, the logical values of the signals at each terminal are as shown in FIG.
, Ro constitute a prefix logic circuit 15 having the same function as the above-mentioned prefix logic circuit 4, and
Due to the action of this circuit 15, the combination of the respective logical values of the output signals 10a and lla of the NAND circuit 10 and 11 as both logical signals outputted from the circuit 15 and inputted to the terminals S and R is Since the combination ``Oj, rOJ'' that was prohibited in the circuit 14 is no longer possible, the FF circuit 9 also has input signals 5a, 5.
Output signal 2C regardless of the combination of each logical value of b
, 2d, no abnormal phenomenon occurs.

In the second embodiment 9 described above, the signal delay circuit 12.1
However, in the present invention, these delay circuits 1
2.13 may be omitted depending on the case, and in the present invention, the delay circuit 12.13 may be provided in the first embodiment 3 described above, and the length of the upper L opening 54a is 6°. ga5L'? ：、Gare、Each Example 3
．． In 9, both the R8FF circuits 2 and 14 were configured using NAND circuits, but in the present invention, the R8FF circuits may also be configured using NOR circuits.

〔Effect of the invention〕

As mentioned above, one aspect of the present invention is R87 Lip 7.
0 to 1 circuit and a two-input, two-output front logic circuit that inputs both ring signals to this R87 lip flow knob circuit.
Each logical value b''- of both output signals of the 87 resob 70 tube circuit
- If the two input signals are output with different logical values, the combination of the logical values of the two output signals of the R8711 knob 70 knob circuit will be the combination of the logical values of the input signals. The flip-flop circuit was configured to perform an operation of outputting a double ring signal in a manner depending on the aspect.

Therefore, with the above configuration, if the input signals input to the prefix logic circuit have the same logical value, the prefix logic circuit will be A logic value that does not cause a change in the logic value of the output signal of the prefix logic circuit 6;
'', so regardless of the combination of each logical value of the 1-car input signal, the combination of the logical values of the 1-car input signal is prohibited for the R87 resobuflotz 7 circuit b'' -Not, therefore.

The present invention has an R87 that does not cause abnormal phenomena in the output signal regardless of the combination of logical values of the input signal.
There is an effect that an FF circuit using an 11-tube to 70-tube circuit can be obtained.

[Brief explanation of drawings]

The first figure is a circuit diagram of the first embodiment of the present invention. FIG. 2 is a diagram showing a state transition table of the first embodiment shown in FIG. FIG. 3 is a circuit diagram of a second embodiment of the present invention. FIG. 4 is a diagram showing a state transition table of the second embodiment shown in FIG. 3. FIG. 5 is a circuit diagram of a conventional R871J knob 70 knob circuit. FIG. 6 is a diagram showing a truth table of the FF circuit shown in FIG. 5. 2.14...R, 8 flip-flop circuit, 2
a+2b, 1oal lla... logic signal,
2CI2d...Output signal, 3.9...
Flip-flop circuit, 4.15...- Pre-logic circuit, 5a, 5b... Input signal. 13-

Claims (1)

[Scope of Claims] 1) An RS flip-flop circuit and a two-input, two-output pre-logic circuit that inputs both logic signals to the RS flip-flop circuit, the pre-logic circuit having both input signals that are the same. If the logic values are the same, the logic signals of the RS flip-flop circuit are outputted so that the logic values of the output signals of the RS flip-flop circuit do not change, and if the input signals are different logic values, the RS flip-flop circuit A flip-flop circuit that outputs both of the logic signals in such a manner that a combination of the logic values of the output signals corresponds to a combination of the logic values of the input signals. 2) In the flip-flop circuit according to claim 1, the front logic circuit includes a two-input NAND circuit to which both input signals input to the front logic circuit are input; The first signal output from the NAND circuit and the second signal output from the delay circuit are input, and both logic signals output from the pre-logic circuit are input. A flip-flop circuit comprising two output logic circuits that output one signal.