JPH0391260A - Cmos integrated circuit device - Google Patents

Abstract

PURPOSE:To remove the occurrence of latch-up by incorporating an overvoltage breakdown circuit including a protective diode in a chip in common for plural pieces of unit circuits inside an integrated circuit device, and besides setting this breakdown voltage higher than the regular value of the voltage between a pair of power source potential points and lower than the lowest breakdown voltage within plural pieces of unit circuits. CONSTITUTION:A unit circuit being output circuit consisting of complementary field effect transistors Tp and Tn and a unit circuit 11 being the signal circuit are constituted, and a protective diode D for an overvoltage breakdown circuit and its serial resistance R are built in being annexed to the field effect transistor inside the output circuit 10. Furthermore, the protective diode D is built in making use of the well 2 of the n-channel field effect transistor Tn inside this output circuit 10. For this reason, a p-type diode layer 6 is built, out of a circular pattern, in the marginal surface part of a p-type well 2 in common with a substrate connection layer, and the peripheral part is extended to the surface of an adjacent n-type semiconductor region 1, a little going over the margin of the well 2. This p-type diode layer 6 is built in by simultaneous diffusion with a p-type source and drain layer 4 for the p-channel field effect transistor Tp.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a CMOS integrated circuit which is formed by integrating a plurality of unit circuits each consisting of complementary field effect transistors, and which has improved latch/tube resistance against overvoltage invasion due to static electricity, etc. Regarding equipment.

[Conventional technology]

As is well known, in a CMOS integrated circuit device, complementary field effect transistors, that is, p-channel type and n-channel type field effect transistors are connected in series with each other and are alternately opened and closed, thereby reducing power consumption. Various advantages can be obtained, such as a larger operating temperature range and a larger operating margin against noise intrusion into signals.

Hereinafter, although it is well known, a basic configuration example of this CMOS integrated circuit device will be briefly explained with reference to FIG.

Figure 2 (@ shows an enlarged part of the chip showing an example of the structure of the semiconductor layer, and the part shown in the figure shows a pair of complementary field effect transistors in the n-type semiconductor region l, such as an epitaxial layer). Two unit circuits 10 and 11 consisting of Tp and Tn are built in, and in this example, the unit circuit 10 outputs an output signal V, like the corresponding circuit in FIG.

The unit circuit 11 is a signal circuit that receives an input signal Vi. Note that, generally, one output circuit is provided with a plurality of signal circuits.

In this example, the output circuits 10 and 11 connect a pair of complementary p-channel field effect transistors Tp and n-channel field effect transistors Tn, both of which are connected in common to a power supply potential point Vd, as shown in FIG. The same structure is connected in series between the p-type well 2 and the p-type well for the n-channel field effect transistor Tn, as shown in FIG. Gate 3° for each field effect transistor; Pair of p-type source/drain layers 4+ for p-channel field effect transistor mill;
A p-type substrate connection layer 5 and a pair of n-type source/drain layers 7 for an n-channel field effect transistor Tn.
．． and an n-type substrate connection layer 8 for a p-channel field effect transistor Tp.

[Problem to be solved by the invention]

However, while CMOS integrated circuit devices have the above-mentioned advantages, they inherently have the disadvantage of being prone to so-called latch-up when overvoltage surges due to static electricity etc. The challenge is to improve latch-up resistance.

The cause of this latch-up is that, as mentioned above, there are four pnpn transistors in each unit circuit consisting of complementary field effect transistors.
This is because a parasitic thyristor risk is unavoidably built into the layered structure, and this is likely to cause conduction when an overvoltage enters the integrated circuit device.This four-layer thyristor structure For each of 10 and 11,
Source of p-channel field effect transistor TpOp type
Drain layer 4°n-type semiconductor region 1. It also includes a p-type well 2 and an n-type source/drain layer 7 for an n-channel field effect transistor Tn.

In order to facilitate understanding of the conduction operation of such a parasitic thyristor structure when an overvoltage enters, FIG. 2(C) shows an equivalent circuit that combines a parasitic transistor, a parasitic diode, etc. This equivalent circuit is of course both unit circuits 10 and 1.
1, which includes a pnp parasitic transistor tp and an npn parasitic transistor tn, both of which are bipolar transistors, and a parasitic circuit with a parasitic diode and a resistor is configured as shown in the figure. .

As shown by the thin line in Figure (a), one of these
! ) The run risk tp is composed of the source/drain layer 4 of the p-channel field effect transistor TpOP type, the n-type semiconductor region 1, and the p-type well 2 of the p-channel field effect transistor Tn, npn) The run risk tn is the n-type source of the n-channel field effect transistor Tn.
It is composed of a drain layer 7, a p-type well 2, and an n-type semiconductor region 1.

Further, a parasitic diode d is located between the p-type well 2 and the n-type semiconductor region 1, a parasitic diode dp is located between the p-type source/drain layer 4 and the semiconductor region 1, and a parasitic diode dn is located between the p-type well 2 and the n-type semiconductor region 1. well 2 and n-type source/drain layer 7
and are formed as shown in the figure. The interconnection point of the parasitic diode dn (!: dp corresponds to the interconnection point of the field effect transistors Tp and Tn, as can be seen from the figure (a), and these are indicated by symbols Vg and Vo in the figure.Furthermore, The resistance rp is the internal resistance of the semiconductor region 1 which is the base of the pnp transistor tp, and the resistance rp is npn)
This is the internal resistance of well 2, which is the base of run risk tn.

Now, if an overvoltage is applied, for example, in the positive direction between a pair of power supply potential points Vd and Vs, the potential of the semiconductor region 1 to which the power supply potential point Vd is connected increases, so that the parasitic diodes dp and dn first break down. Then, a current flows from one power supply potential point Vd to the other power supply potential point Vs via resistor rp + parasitic diodes dp and dn, and resistor rn, and as a result, a current flows between the base and emitter of parasitic transistors tp and tn. A voltage is applied across the resistors rp and rn, respectively. However, as can be seen from FIG. 2(a), the parasitic transistor tp is horizontal, and the parasitic transistor tn is vertical, and the current amplification factor of the latter is much higher than that of the former.
turns on first. As a result, the power supply potential point V
A larger current flows from d through the resistor rp and the parasitic transistor tn to the power supply potential point Vs, and the resistor rp
As the voltage across the terminal increases, the parasitic transistor tp which receives this as the voltage between the base and the terminal also turns on, short-circuiting the two power supply potential points Vd and Vs, and a very large current flows.

As will be seen, the parasitic transistors tp and tn form the aforementioned parasitic thyristor, and when this becomes conductive due to overvoltage, latch-up occurs and a large current flows between the two power supply potential points, causing the unit circuits 10 and 11 to Not only will there be a complete loss of functionality, but the semiconductor junctions in this high current path may be destroyed within a short period of time, and this latch-up condition will not be resolved unless the power supply is removed. is assumed to be positive, but latch-up will occur in the same way even if it is negative.

Various solutions to such latch-up have been devised in the past. For example, although it is possible to increase the impurity concentration of the substrate connection layers 5 and 8 as much as possible, it is not very effective in improving latch-up resistance. There are also measures to lower the breakdown voltage of the parasitic diode d, which is a so-called substrate diode, but it is extremely difficult to increase the impurity concentration in the semiconductor region 1 and well 2 without adversely affecting the characteristics of the field effect transistor. However, it cannot be the fundamental solution to the problem.

In order to solve this problem, the present invention uses simple means to prevent overvoltage from entering from the power supply potential point as described above.
The purpose is to improve the latch-up resistance of an OS integrated circuit device.

[Means to solve the problem]

According to the present invention, this object is achieved by incorporating an overvoltage breakdown circuit that includes a protection diode in common for a plurality of unit circuits incorporated into a CMOS integrated circuit device into a chip of the integrated circuit device, and connecting this protection diode to a pair of unit circuits. The voltage between the two power supply potential points is built horizontally on the chip surface between the connection points of the power supply potential points to the chip with the opposite polarity, and the breakdown voltage is calculated from the normal value of the voltage between a pair of power supply potential points. is distantly related by setting it to be high and lower than the lowest value among the breakdown voltages of each unit circuit.

Note that it is usually sufficient for the above-mentioned overvoltage breakdown circuit to consist of a protection diode and a low resistance connected in series with the protection diode. Furthermore, when the unit circuit includes an output circuit, it is desirable to incorporate the overvoltage breakdown circuit along with this output circuit.

When the protection diode is provided laterally on the surface of the chip as in the above structure, it is advantageous in terms of saving the chip area to build it using the well of the field effect transistor. For example, one diode layer for a protection diode is formed on the surface of the periphery of the well of a field effect transistor with the same conductivity type, and the other diode layer is formed on the surface of the semiconductor region surrounding the well. It is most desirable that one of these diode layers be provided in common with the substrate connection layer.

In addition, in order to eliminate the need for an additional process to fabricate this protection diode, it is recommended that the diffusion of the pair of diode layers for it be performed at the same time as the diffusion of the source/drain layer for the field effect transistor. It's advantageous. Further, in order to improve latch-up resistance, it is desirable to increase the current capacity of the protection diode, and for this purpose, it is advantageous to form a pair of diode layers in a concentric ring pattern.

[Effect]

As described in the above structure, the present invention incorporates an overvoltage breakdown circuit including a protection diode into a chip in common in a plurality of unit circuits in an integrated circuit device, and causes the protection diode to breakdown when an overvoltage due to static electricity or the like enters. By absorbing overvoltage and setting this breakdown voltage higher than the normal value of the voltage between a pair of power supply potential points and lower than the lowest breakdown voltage in a plurality of unit circuits, it is possible to This is to prevent breakdown or latch-up from occurring in the unit circuit.

Furthermore, as described in the above structure, the present invention provides protection when absorbing the above-mentioned overvoltage by building a protection diode laterally in the chip surface area □ between the connection points of a pair of power supply potential points to the chip. Even if a large current flows through the diode, the effect is limited to the surface of the chip and does not reach the semiconductor layer for the field effect transistor of the unit circuit, making the latch-up prevention effect described above even more reliable. It was made so that it could be obtained.

〔Example〕

The embodiment of the present invention shown in FIG. 1 will be explained in detail below. This FIG. 1 shows an enlarged cross-section of the main part of the chip, its circuit, and equivalent circuits such as parasitic transistors in the same way as FIG. 2 described above, and corresponding parts are given the same reference numerals.

FIG. 1(a) shows a unit circuit 10 which is an output circuit and a unit circuit 11 which is a signal circuit as described above, both of which are composed of complementary field effect transistors Tp and Tn. A protection diode D and its series resistance R are built in conjunction with the field effect transistor in the output circuit 10 in this embodiment. A plurality of signal circuits 11 are normally provided for one output circuit 10, and the field effect transistors used therefor are often fabricated with minute patterns in order to reduce the required chip area as much as possible, so the protection diode D is For example, it is advantageous to fabricate the field effect transistors in the output circuit, which are common to them and formed in a relatively large pattern.

Furthermore, in this embodiment, the protection diode D is fabricated using the well 2 of the n-channel field effect transistor Tn in the output circuit 10. For this reason, in this example, a p-type diode lI6 is formed in a circular pattern on the peripheral surface of the p-type well 2 to serve as the substrate connection layer, and its outer periphery slightly touches the peripheral edge of the well 2 as shown in the figure. It extends beyond the surface to the surface of the adjacent n-type semiconductor region 1. It is advantageous to form this p-type diode layer 6 by simultaneous diffusion with the p-type source/drain layer 4 for the p-channel field effect transistor Tp in order to simplify the process. Further, on the surface of the n-type semiconductor region l, an n-type diode layer 9 is formed in a ring-shaped pattern surrounding the diode layer 6 from the outside in this example, and in the case of this diode layer 9, an n-channel field effect transistor Tn is also formed. It is advantageous to form the layer by simultaneous diffusion with the n-type source/drain layer 7.

A protective diode D is formed by the p-type and n-type diode layers 6 and 9 and the n-type semiconductor region 1 between them. Note that both of these diode layers 6 and 9 are source/drain layers of a field effect transistor. For example, 0.
The protective diode D may have a high impurity concentration layer of 1020 atoms/d or more with a depth of 5 to 1 mm, and the mutual spacing thereof may be set to several micrometers or less, for example, 2 μ. It can have a voltage value.

Of these two diode layers, the p-type diode layer 6 has a power supply potential point νS on the ground side, similar to the conventional substrate connection layer, and the n-type diode layer 9 has a power supply potential point Vd on the positive side. Each is connected as shown. In addition,
In this example, the series resistance R to the protection diode D is determined by the internal resistance of the p-type diode layer 6, and is less than several ohms that can pass the current necessary to absorb the overvoltage to the protection diode D and protect it. For example, it can have a resistance value of about 2Ω.

The circuit of FIG. 1(b), which corresponds to FIG. 1(a), shows an overvoltage breakdown circuit 20 comprising such a protection diode D and a series resistor R.

FIG. 1C shows an equivalent circuit of a parasitic transistor, a parasitic diode, and a resistor including this overvoltage breakdown circuit 20. Note that in this figure, there is also a parasitic diode d, which is a substrate diode, on the side of the unit circuit 10, which is the output circuit, but in the present invention, the protection diode D is connected in parallel to this and can be ignored, so it is omitted from this equivalent circuit. There is.

According to the measurement results for the integrated circuit device implementing the present invention,
The current amplification factor of the horizontal pnp parasitic transistor tp on the unit circuit 10 side, which is the output circuit, is 0.05, and the current amplification factor of the vertical npn parasitic transistor tn is 200.
The p and rnO values are 200Ω and 300Ω, respectively. On the other hand, on the unit circuit 11 side, which is a signal circuit, the current amplification factors of parasitic transistors tp and tn are 1 and 200, respectively, and the resistance values of resistors rp and rn are 500Ω and 600Ω, respectively.
The breakdown voltage of the parasitic diode d is 100V. Also,
For both unit circuits 10 and 11, the parasitic diode d
p1! -dn breakdown voltage is 25V.

Furthermore, the breakdown voltage of the protection diode D is 13V, and the resistance R
The value of was 2Ω.

In this way, the resistance rp and rnO value on the unit circuit 11 side and the current amplification factor of the parasitic transistor tp are the same as that of the unit circuit 1.

Since latch-up is particularly likely to occur on the unit circuit ll side, which is a signal circuit, when the charging voltage of a 2009F capacitance is applied to an integrated circuit device that operates under Latch-up occurred on the unit circuit 11 side due to an overvoltage of about 120μ. On the other hand,
CMOS incorporating overvoltage breakdown circuit 20 according to the invention
In the integrated circuit device, when the breakdown voltage of the protection diode D was 13V as mentioned above, latch-up did not occur in any of the unit circuits even if an overvoltage of 400V entered.

This is a unit circuit 10 in which an overvoltage breakdown circuit 20 is incorporated.
Looking at polarization, the resistance R at breakdown of the protective diode D
Since the value of is much smaller than the resistance rp+rn, even if the parasitic diodes dp and dn break down, the resistance rp, the parasitic diodes dp and dn, and the resistance rn will be removed from the power supply potential point Vd.
It is thought that this is because the current flowing to the power supply potential point v3 via the current is much smaller than before, and the parasitic diode tn does not turn on.

The effect of the overvoltage breakdown circuit 20 is of course the same for the unit circuit ll side which is a signal circuit, but the wiring for the power supply potential points Vd and VS has some effects as shown in Fig. 1(C). Since leakage inductance Ls always exists,
It is considered that after breakdown of the protection diode D on the unit circuit 10 side, the overvoltage is not applied to the unit circuit 11 side so much, which contributes to latch-up prevention. When the unit circuits constituting an integrated circuit include an output circuit and a signal circuit, if an overvoltage breakdown circuit is built into the output circuit side as in this embodiment, the field effect transistor can be used to connect a protection diode as described above. In addition to being advantageous for manufacturing, it also has the advantage of suppressing overvoltage applied to signal circuits, which are normally provided in multiple numbers.

Note that a fairly large current may flow through the protection diode during the above-mentioned latch-up prevention and overvoltage suppression functions of the overvoltage breakdown circuit, but since the overvoltage is the charging voltage of a small capacitance, the current time is very short, and the overvoltage is quite high. There is no risk of damage or deterioration of the protection diode junction or series resistance.

In addition to the embodiments described above, the present invention can be implemented in various embodiments to obtain the above-mentioned effects. The pattern can be selected as appropriate depending on the capacity.

〔Effect of the invention〕

As described above, in the present invention, an overvoltage breakdown circuit including a protection diode is commonly incorporated into a chip for a plurality of unit circuits incorporated in an integrated circuit device, and this protection diode is connected to a pair of power supply potential points. The voltage between the two power supply potentials is built horizontally on the chip surface □ between the connection points to the chip with the opposite polarity, and the breakdown voltage is calculated from the normal value of the voltage and voltage between the power supply potentials of one pair □. By setting the voltage to be high and lower than the lowest breakdown voltage of each unit circuit, it is possible to effectively prevent conduction caused by overvoltage entering from the power supply potential point of the parasitic thyristor or bipolar transistor in the complementary field effect transistor of each unit circuit. As described in the embodiment, the latch-up resistance of the integrated circuit device can be improved several times compared to the conventional one.

In particular, in the present invention, the protection diode of the overvoltage breakdown circuit is built horizontally on the chip surface between the connection points of a pair of power supply potential points to the chip. Even if a large current flows, the effect is limited to only a small part of the chip surface and there is no risk of it reaching the semiconductor for the field effect transistor of the unit circuit, which greatly improves the latch-up prevention effect of the overvoltage breakdown circuit. You can definitely get □.

In addition, when a unit circuit constituting an integrated circuit includes an output circuit and a plurality of signal circuits corresponding to the output circuit, according to a mode in which the overvoltage breakdown circuit is incorporated in the output corridor side, it is possible to allocate the overvoltage breakdown circuit to the field effect transistor for the output circuit. The present invention can be easily implemented by only slightly increasing the chip area, and the overvoltage applied to the signal circuit can be effectively suppressed to further improve the latch-up resistance of the integrated circuit device.

The present invention having such features can be applied to CMOS integrated circuit devices in general and contribute to improving their operational reliability.

[Brief explanation of drawings]

FIG. 1 is an enlarged sectional view of a main part of a chip of an embodiment of a CMOS integrated circuit device according to the present invention, and a circuit diagram thereof. and an equivalent circuit diagram of parasitic transistors and the like. FIG. 2 is an enlarged sectional view of a main part of a chip and a circuit diagram thereof corresponding to FIG. 1 of a conventional CMOS integrated circuit device. and an equivalent circuit diagram of parasitic transistors and the like. In the figure, 1: semiconductor region within the chip, 2: well, 3: gate,
4: Source/drain layer, 5: Substrate connection layer,
6: Diode layer, 7: Source/drain layer, 8: Substrate connection layer, 9: Diode layer, 10: Unit circuit or output circuit, 11: Unit circuit or signal circuit, 20
8 overvoltage breakdown circuit, D: protection diode, d, dn, d
p: parasitic diode, R: series resistance of protection diode,
rn, rp: resistance, Tarn channel field effect transistor, Tp: P channel field effect transistor, tn
r npn type parasitic transistor ps pnp type parasitic transistor d one power supply potential point, vl: input signal, Vm: unit quantity line signal, vO: output signal, vS: other power supply potential point,

Claims (1)

[Claims] A CMOS integrated circuit device formed by integrating a plurality of unit circuits made of complementary field effect transistors, wherein an overvoltage breakdown circuit including a protection diode in common for the plurality of unit circuits is built into the chip of the integrated circuit device, This protection diode is built horizontally on the chip surface between the connection points of a pair of power supply potential points to the chip, with the polarity opposite to the voltage between both power supply potential points, and the breakdown voltage is set to A CMO characterized in that the voltage between potential points is set higher than the normal value and lower than the lowest value among the breakdown voltages of each unit circuit.
S integrated circuit device.