JP2005268379A - Low-capacitance esd protective circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize an electrostatic discharge protective circuit in which an I/O circuit can be operated at high speed without deteriorating characteristics of LVTSCR, with regard to a problem in which parasitic capacity caused by connection of a protective circuit is suppressed in a conventional switching element for turning the protective circuit into conducted state by electrostatic stress. <P>SOLUTION: A trigger NMOS transistor is connected between a signal input/output terminal and a p gate of an SCR, and such an integrated circuit is configured using a triple n-well structure. In the configuration, the area of a protective circuit is reduced by directly configuring the trigger NMOS on a p-sub substrate. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a protection circuit for an input / output circuit in a semiconductor integrated circuit, and more particularly to an electrostatic discharge protection circuit (hereinafter referred to as an ESD protection circuit).

  A basic circuit configuration conventionally used for an ESD protection circuit for an input / output circuit of a semiconductor integrated circuit will be described with reference to FIG. Various structures and circuits have been proposed for the ESD protection circuit in the CMOS process, but the common thing in any ESD protection circuit is that the protection circuit is low due to the input of electrostatic stress (surge). It is a point that becomes a conductor of impedance. In order to protect the internal circuit 2, the surge input voltage suppresses a voltage rise at the I / O pad that is a signal input / output terminal as much as possible, and a large current is supplied to the protection circuit.

  As an element having such a function, a PNPN junction element called a thyristor or SCR (Silicon Controlled Rectifier) has been applied for a long time. However, in general, the SCR has a high trigger voltage, that is, a voltage required to bring the element into a conducting state as high as several tens of volts, and is not suitable for protecting a sub-micron class fine IC. Therefore, in the following Non-Patent Document 1, a protection circuit as shown in FIG. 4 has been proposed. The circuit shown in FIG. 4 is called LVTSCR (Low-Voltage Triggering SCR). For example, it is assumed that a positive surge is applied to the I / O pad with respect to the VSS pad serving as the low potential side power supply terminal.

  The trigger NMOSFET 3 normally breaks down at about 4 to 8 V in a fine device of 0.5 μm or less process, and a surge current flows to the VSS pad 23 via the N-well resistor 4 and the trigger NMOS 3. When the current flows through the N-well resistor 4, the drain potential of the trigger NMOSFET 3 becomes lower than that of the I / O pad 21, and the trigger NMOSFET 3 becomes conductive, so that the body potential of the NMOSFET 3 is less than the VSS pad. Rise. As a result, the SCR 1 becomes conductive, and the main surge flows through the SCR 1 having a low on-resistance and suppresses the increase in the potential of the I / O pad 21.

  Since the conductive SCR 1 has a very low resistance, the ESD resistance with respect to the element area is extremely high. For this reason, many studies have been made, and several circuit structures that can be said to be developed types of LVTSCR have been reported. FIG. 5 shows the following (Non-patent Document 2) as an improvement example of a typical LVSCR reported in recent years. A feature of this circuit is that a circuit called an RC trigger network composed of a capacitor 9 and a resistor 8 is introduced between the I / O pad 21 and the VSS pad 23, a surge input is detected, and the trigger NMOSFET 3 is turned on. It is to actively promote. In addition, in the conventional example of FIG. 4, it is necessary to separately provide protection between power supply lines, and the network for connecting the power supply line protection circuit and the I / O pad 21 is insufficient. In the example, the trigger NMOSFET 3 also serves as a power line protection circuit. For example, even when a positive surge is applied with reference to the VDD pad 22, the trigger NMOSFET 3 is easily surged via the PN junction diode of the PNP transistor constituting the SCR 1. It is possible to flow. 4 uses a P-sub substrate as a VSS potential and uses it as a part of the circuit, but the conventional circuit of FIG. 5 uses a triple well structure to enclose the entire circuit in a deep N-well. Therefore, the substrate and the circuit are completely separated. For this reason, the circuit of FIG. 5 can be improved with respect to the influence of noise.

However, in the signal input / output operation (I / O operation) exceeding 10 GHz in recent years, it is necessary to make the pad capacitance, that is, the pad area as small as possible, and the protection circuit is avoided as a presence of parasitic capacitance. One of the advantages of the ESD protection circuit using the SCR is that the circuit area can be reduced, so that there is a possibility that the parasitic capacitance of the protection circuit can be reduced. However, the biggest problem in the SCR is that the trigger voltage is extremely high and cannot be put into practical use as it is. The conventional circuit shown in FIG. 4 was epoch-making as a technique for reducing the trigger voltage of the SCR to a practical range. However, structurally, since the I / O pad is connected to both the P + diffusion layer and the N + diffusion layer in the N-well, an N-well capacitance having a large area is added to the I / O pad as a parasitic capacitance. There is a drawback that it will be. This drawback becomes a problem when high speed operation is required in an I / O circuit connected to an I / O pad. With respect to such parasitic capacitance, the conventional circuit shown in FIG. 5 is more advantageous. The capacity 9 required for the RC trigger network is about 10 pF, which is sufficiently small. However, since the RC trigger network in FIG. 5 is only a trigger device, it cannot be expected to serve as a surge path. It is reported in the following (Non-patent Document 3) that the PN junction area corresponding to 10 pF is about 4 μm ² or less, and the HBM (Human Body Model) -ESD resistance of the diode having this junction area reaches about 800V. Yes. When the allowable parasitic capacitance is limited, it is desirable that the structure related to all the parasitic capacitance functions as a surge path.

  Furthermore, since the capacitor 9 of the RC trigger network is connected to the I / O pad, there is a risk that the impedance of the capacitor 9 is lowered in an I / O circuit that operates at high speed. Also has the disadvantage of giving a trigger.

  Further, the conventional circuit of FIG. 5 is not provided with a protection mechanism when a negative surge is applied to the I / O pad, so that the internal circuit cannot be protected against a negative surge.

Chattergee and T. Polgreen, “A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads,” IEEE Electron Device Lett., Vol.12 pp.21-22, 21-22, 1991 T. Nikolaidis and C. Papadas, “A Novel SCR ESD Protection for Triple Well CMOS Thechnologies,” IEEE Electron Device Lett., ”Vol.22, pp. 185-187, 2001 C. Richier, et al “Investigation on Different ESD Protection Starategies Devoted to 3.3V RF Applications (2GHz) in a 0.18μm CMOS MOS Process,” Proc. EOS / ESD Symp. 2000, pp.251-259, 2000.

  As described above, in the ESD protection circuit using the conventional circuit, the characteristics of the I / O pad serving as the input / output terminal are not sufficient in terms of high-speed operation, and it cannot be protected depending on the polarity of the surge. There was a problem. Therefore, an object of the present invention is to provide a low parasitic capacitance protection circuit that realizes high speed without damaging high breakdown voltage in ESD protection of input / output terminals in an analog / digital mixed LSI.

  In order to achieve the above object, in claim 1 of the present invention, in an electrostatic discharge protection circuit in a semiconductor integrated circuit, an SCR (Silicon Controlled Rectifier) constituted by a triple well structure is caused to function as a main protection circuit. The SCR is connected between an input / output terminal (I / O pad) and a ground terminal which is a low potential side power supply terminal (VSS), and a base electrode of a PNP bipolar transistor which is one transistor constituting the SCR is connected. An NMOS transistor connected to a diode is connected between the base electrode of the NPN transistor, which is the other transistor constituting the SCR, and the input / output terminal, connected to the high potential side power supply terminal (VDD), The power supply line protection circuit is provided between the high potential side power supply terminal and the low potential side power supply terminal. Stomach has been defined.

  According to a second aspect of the present invention, in the ESD protection circuit according to the first aspect, a configuration is provided in which a resistance element is provided between the source of the NMOS transistor connected to the input / output terminal side and the base electrode of the NPN transistor. ing.

  According to a third aspect of the present invention, in the ESD protection circuit according to the first or second aspect, the NMOS transistor connected between the input / output terminal and a base electrode of the NPN transistor forming the SCR is provided. In addition to the elements constituting the protection circuit by being configured in the triple well structure, the base electrode is the low potential power source, the collector electrode is the high potential power source, and the emitter electrode is the input / output terminal. It defines a configuration in which another parasitic NPN bipolar transistor different from the above is connected.

  According to a fourth aspect of the present invention, in the ESD protection circuit according to any one of the first to third aspects, a configuration using an NMOS transistor in which the power line protection circuit is diode-connected is defined.

  5. The ESD protection circuit according to claim 1, wherein the SCR is formed in a P well included in a deep N well in the triple well structure. And a second PN junction diode formed in the deep N well, and an anode of the first PN junction diode is connected to a gate electrode of the diode-connected NMOS transistor connected to an input / output terminal. , Connected to the source of the NMOS transistor through a resistance element, the cathode of the first PN junction diode is connected to the low potential side power supply terminal, the anode of the second PN junction diode to the input / output terminal, The SCR is configured parasitically by connecting the cathode of the second PN junction diode to the high potential side power supply terminal. It has been defined for that occupies.

  According to the first embodiment of the present invention, the parasitic capacitance added to the I / O pad can be controlled by the drain area of the trigger NMOS and the anode area of the SCR, and a protection circuit with low parasitic capacitance and high withstand capability is constructed. it can. Further, the SCR using the triple well structure, the power line protection circuit, and the trigger NMOS may be combined to promote the turn-on of the SCR by energizing the surge path via the power line protection circuit and energizing the trigger NMOS. it can.

Furthermore, since the N gate of the SCR is connected to the VDD pad during normal operation, there is no risk of malfunction unless a potential higher than the potential of the VDD pad is input or output to the I / O pad. Even if the SCR is turned on during the normal operation due to the above, the SCR recovers the cut-off state if the potential level of the I / O pad falls below the power supply voltage.
In the present invention, it is possible to secure a surge path for protecting the internal circuit in the case of a surge of either positive or negative polarity with respect to each power supply terminal. According to the second and third embodiments of the present invention, the basic structure of the present invention can be realized by a plurality of different diffusion layer structures. Therefore, depending on the circuit area, protection capability, restrictions on design rules in the process, and the like. Flexible layout is possible.

  As described above, the protection circuit of the present invention is extremely effective for protecting an I / O circuit that requires a high-speed operation of GHz or higher in a high-speed analog LSI represented by a communication LSI or a high-speed analog / digital mixed LSI.

  First, a basic configuration of an ESD protection circuit which is a feature of the present invention will be described with reference to FIG. 1A, and a cross section of the integrated circuit will be described with reference to FIG. The ESD protection circuit of the present invention uses a triple well structure generally used in a mixed analog / digital CMOS process, and between the I / O pad 21 and the P gate of SCR1 (PG7 in FIG. 1A). The first feature is that the trigger NMOS 3 is diode-connected to the first conventional NMOS. The N gate of SCR1 (NG6 in FIG. 1A) is connected to the VDD pad 22 as in the conventional circuit.

  The second distinguishing feature is that a parasitic NPN transistor 9 is formed between the VDD pad 22 and the I / O pad 21 by configuring the trigger NMOS 3 in the triple well structure and connecting them as described above. It is a feature. A third point different from the prior art is that a protection circuit is provided between the power supply lines (between VDD and VSS) in addition to the trigger NMOS 3. Although the diode-connected NMOS 10 is shown in FIG. 1A, a sufficiently large size can be selected for the protection element between power supply lines because it is not restricted by parasitic capacitance.

With such a structure, the ESD protection circuit of the present invention secures an effective surge path for both positive and negative surges applied to the I / O pad 21 with respect to the potential of the VDD pad 22 and the VSS pad 23. Can do.
In FIG. 1B, the diffusion layer region (the anode 17 and the drain 24) connected to the I / O pad 21 is a P + layer (a source / drain layer in a PMOS transistor) in the deep-N-well (13). ) And the N + layer (corresponding to the source / drain layer in the NMOS transistor) in the P-well (12), the parasitic capacitance connected to the I / O pad 21 is independent of the well capacitance. According to the patent application “Japanese Patent Application No. 2003-359656 electrostatic discharge protection circuit (unpublished)” by the inventor, if the area of the diffusion layer region connected to the I / O pad 21 is 4 μm ² or less, The total parasitic capacitance is about 22 fF or less. By appropriately selecting the area of the diffusion layer region connected to the I / O pad 21, it can be easily suppressed to a parasitic capacitance or less allowed for the I / O circuit.

  The present invention is also characterized by an SCR trigger mechanism. A case where a positive surge is applied to the I / O pad 21 with respect to the VSS pad 23 will be described. In the conventional circuit shown in FIGS. 4 and 5, when the drain electric field reaches a certain level due to the rise of the drain voltage of the trigger NMOS 3 due to the surge input, the current breaks down and the current flows. As a result, the potential of NG6, which is the N gate, falls below the potential of the I / O pad 21, and the potential of the body of the trigger NMOS 3, that is, the PG7, which is the P gate, rises from the VSS pad 23 due to the breakdown of the trigger NMOS 3. As a result, SCR1 is turned on. In the conventional circuit shown in FIG. 5, the capacitor 9 and the resistor 8 are used to positively raise the potential of the PG 7 immediately after the surge is input, thereby further ensuring the turn-on of the SCR 1.

  Furthermore, the present invention is also characterized by having an independent two-path trigger mechanism. That is, the trigger NMOS 3 and the power supply line protection NMOS 10 first break down with respect to the surge input. The breakdown timing can be adjusted by adjusting the gate length of each NMOS, for example. Assume that there is a positive surge input to the I / O pad 21 with respect to the VSS pad 23. As in the conventional circuit, the trigger NMOS 3 and the power line protection NMOS 10 break down at the same time or before and after the increase of the terminal potential. Due to the breakdown of the NMOS 3, the potential of the PG7 of the SCR1 rises from the potential of the VSS pad 23, and by the breakdown of the power supply line protection NMOS10, the potential of the NG6 of the SCR1 falls below the potential of the I / O pad. As a result, the SCR 1 is turned on to protect the internal circuit 2.

If the power supply line protection NMOS 10 or NMOS 3 is preceded by the breakdown of the SCR 1, the SCR 1 is turned on. However, if the SCR 1 is not sufficiently turned on and the SCR 1 has a reduced current carrying capability, the potential of the I / O pad 21 is reduced. Rises and the other non-yield NMOS yields to facilitate SCR1 turn-on.
Thus, by using two independent trigger mechanisms, SCR1 can be turned on reliably.

  When a negative surge is input to the I / O pad 21 with respect to the VSS pad 23, the body of the NMOS 3, that is, the PN junction diode from the P-well 12 to the drain of the NMOS 3 serves as a surge path, and the internal circuit 2 is Protect. When a positive surge is input with reference to the VDD pad 22, a PN junction diode from the I / O pad 21 to NG 6 of the SCR 1 serves as a surge path. In the conventional surge path, as disclosed in the above-mentioned “Non-Patent Document 3”, a typical diode protection circuit (a diode is connected in a reverse bias direction between a power supply and an I / O pad, and 2), the PN junction diode from the VDD pad 22 to the I / O pad 21 through the power line protection circuit NMOS 10 is used as a main surge path.

On the other hand, the present invention is characterized in that a PN junction diode in the parasitic NPN transistor 9 that is parasitically formed in addition to the surge path also works as a surge path. A current flowing through the PN junction diode of the parasitic NPN transistor 9 corresponds to a base current flowing through the parasitic NPN transistor 9. Therefore, the parasitic NPN transistor 9 is turned on. This path is a path that directly flows from the VDD pad 22 to the I / O pad 21, and therefore has a lower resistance than the surge path that flows through the power supply line protection NMOS 10, which is advantageous for protecting the internal circuit 2.
Thus, in the present invention, the internal circuit can be strongly protected against surges of either positive or negative polarity with respect to either the power supply terminal of the VDD pad 22 or the VSS pad 23.

(Example 1)
A first embodiment of the present invention will be described with reference to FIG. FIG. 1B schematically shows a cross-sectional configuration of the circuit of the present invention described in the previous section. As described above, in the protection circuit of the present invention, the diode-connected trigger NMOS 3 is connected between the I / O pad 21 and PG 7, and SCR 1 in which NG 6 is connected to the VDD pad 22 is connected between the I / O pad 21 and the VSS pad 23. And a power line protection NMOS 10 is connected between the VDD pad 22 and the VSS pad 23. In FIG. 1B, the power supply line protection NMOS 10 is omitted. The resistor 8 is a resistor for preventing an excessive current from flowing through the trigger NMOS 3, and a resistance value is selected so that the trigger NMOS 3 is not destroyed during the ESD event, based on the energizing capability of the SCR 1 and the energizing capability of the trigger NMOS 3. Is desirable.

  Since the deep-N-well 13 and the deep-N-well 14 are both connected to the VDD pad 22, it is not always necessary to separate them as shown in FIG. Here, they are separated for convenience of description of the configuration. A P-well 11 is formed in the deep-N-well 13, and a PN junction diode is formed in each of the deep-N-well 13 and the P-well 11. The anode 17 of the first PN junction diode configured in the deep-N-well 13 is connected to the I / O pad 21, the cathode (NG6) is connected to the VDD pad 22, and the second PN junction in the P-well 11 is connected. The cathode 16 of the diode is connected to the VSS pad 23, and the anode (PG 7) is connected to the resistor 18 connected to the gate 18 and the source 25 of the trigger NMOS 3.

  With this structure, an SCR having the anode 17 of the first PN junction diode as the anode, the cathode as the N gate (NG6), the anode of the second PN junction diode as the P gate (PG7), and the cathode 16 as the N gate. Is generated parasitically. On the other hand, a P-well 12 is provided inside the deep-N-well 14, and a trigger NMOS 3 is formed inside the P-well 12. Here, the deep-N-well 14 is connected to the VDD pad 22, and the P-well 12 is connected to the VSS pad 23.

  With such a configuration, a circuit as shown in FIG. 1 (a) is constructed. The trigger NMOS 3 in FIG. 1 (b) is shown as a single gate, but if the gate is made up of two fingers and the region sandwiched between the gates is used as the drain and connected to the I / O pad, the trigger NMOS 3 is shown. Since the gate length is doubled with the same drain area, the allowable current of the trigger NMOS 3 can be increased. However, since the gate overlap capacitance is also doubled, care must be taken in estimating the parasitic capacitance.

(Example 2)
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 2A is an equivalent circuit of an ESD protection circuit according to the second embodiment of the present invention, and FIG. 2B is a diagram schematically showing a cross-sectional configuration of the protection circuit. Also in FIG. 2B, the description of the power supply line protection NMOS 10 is omitted. In the second embodiment, the trigger NMOS 3 shown in the first embodiment is not formed inside the deep-N-well 14 but directly formed on the P-sub 15 substrate. In this case, the parasitic vertical (vertical) NPN transistor 9 between the VDD pad 22 and the I / O pad 21 existing in the first embodiment does not exist, but the effect of the trigger NMOS 3 is the first embodiment. It can be realized in the same way as the example. Since the trigger NMOS 3 is not formed in the deep-N-well 14, the circuit area can be reduced.

(Example 3)
A third embodiment of the present invention will be described with reference to FIG. The present embodiment is a case where the configuration of the SCR 1 in the first and second embodiments is changed, and the configuration method of the SCR 1 is described with reference to schematic sectional views. Therefore, the trigger NMOS 3 can be combined with the method shown in the first or second embodiment. FIG. 3A is an equivalent circuit of the SCR 1, and FIG. 3B is a reproduction of the configuration of the SCR 1 shown in the first and second embodiments, which can be called a diode type. FIG. 3C is an example in which the PNP transistor portion 30 constituting the SCR 1 is a lateral transistor configured in the N-well (26), and FIG. 3D is a diagram of FIG. This is an example in which the N-well (26) including the lateral PNP transistor 30 is shared with the deep-N-well 13 including the NPN transistor 31 constituting the SCR1. The SCR 1 in FIG. 3C and FIG. 3D is different from the SCR 1 in FIG. 3B, and realizes the SCR structure by wiring-connecting the independent PNP transistor 30 and the NPN transistor 31.

1A is an equivalent circuit diagram of a first embodiment of an ESD protection circuit according to the present invention, and FIG. (A) Equivalent circuit diagram (b) Cross-section block diagram in 2nd Example of ESD protection circuit by this invention. FIG. 3 is a structural example of an SCR according to the present invention, (a) an equivalent circuit, (b) a diode-type cross-sectional view, and (c) a cross-sectional view of a lateral / vertical mixed type 1. (D) The cross-sectional block diagram of the lateral / vertical mixed type 2. The equivalent circuit diagram which shows the prior art example of the ESD protection circuit of SCR use. The equivalent circuit diagram which shows the prior art example of the ESD protection circuit which is the improved type of the said FIG.

Explanation of symbols

1: SCR 2: Internal circuit 3: Trigger NMOS
4: N-well resistance 5: P-well resistance 6: N-gate 7: P-gate 8: Resistance 9: Capacitance 10: Power line protection NMOS 11, 12: P-well 13, 14: Deep-N-well 15: P- sub
16: Cathode 17: Anode 18: Gate 19: Body 20: N-sub contact 21: Input / output pad 22: High potential side power supply terminal 23: Low potential side power supply terminal 24: Drain 25: Source 26: N-well 30: PNP transistor 31: NPN transistor

Claims (5)

In an electrostatic discharge protection circuit in a semiconductor integrated circuit, an SCR composed of a triple well structure is used as a main protection circuit,
The SCR is connected between an input / output terminal and a ground terminal which is a low potential side power supply terminal,
A base electrode of a PNP bipolar transistor which is one of the transistors constituting the SCR is connected to a high potential side power supply terminal;
A diode-connected NMOS transistor is connected between a base electrode of an NPN transistor, which is the other transistor constituting the SCR, and the input / output terminal;
An ESD protection circuit comprising a power line protection circuit between the high potential side power supply terminal and the low potential side power supply terminal. The ESD protection circuit according to claim 1,
An ESD protection circuit comprising a resistance element between a source of an NMOS transistor connected to the input / output terminal side and a base electrode of the NPN transistor. The ESD protection circuit according to claim 1 or 2,
The NMOS transistor connected between the input / output terminal and the base electrode of the NPN transistor forming the SCR is configured in the triple well structure to add to the element constituting the protection circuit. ,
Another parasitic NPN bipolar transistor different from the above is provided, in which a base electrode is connected to the low potential power source, a collector electrode is connected to the high potential power source, and an emitter electrode is connected to the input / output terminal. An ESD protection circuit. The ESD protection circuit according to any one of claims 1 to 3,
An ESD protection circuit, wherein the power supply line protection circuit is constituted by a diode-connected NMOS transistor. The ESD protection circuit according to any one of claims 1 to 4,
The SCR is composed of a first PN junction diode created in a P well included in a deep N well in the triple well structure, and a second PN junction diode created in the deep N well,
An anode of the first PN junction diode is connected to a gate electrode of the diode-connected NMOS transistor connected to an input / output terminal and a source of the NMOS transistor via a resistance element;
Connecting the cathode of the first PN junction diode to the low potential side power supply terminal;
The ESD is characterized in that the SCR is configured parasitically by connecting the anode of the second PN junction diode to an input / output terminal and connecting the cathode of the second PN junction diode to a high potential side power supply terminal. Protection circuit.

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