JP2002043533A - Esd protection device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ESD protection device wherein there is realized such a characteristic that its current and electric-field concentrations to its junction portions are generated hardly even when it is miniaturized and it is triggered at a low voltage. SOLUTION: The ESD protection device is interposed between an input terminal 6 of a semiconductor integrated circuit chip and its CMOS transistor 100, and has a triggering element 310 having diodes 311, 312 broken down by an overvoltage applied to the input terminal 6, and has an ESD protection element 210 having vertical type bipolar transistors 211, 212 for discharging the accumulated charge of the input terminal 6 by their continuities caused by the breakdowns of the diodes 311, 312.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an electrostatic discharge (ES)
The present invention relates to an ESD protection device provided in a semiconductor integrated circuit chip to protect the semiconductor integrated circuit from D (electrostatic discharge) and a method of manufacturing the same.

[0002]

2. Description of the Related Art ESD in a conventional CMOS process
The protection device generally uses a lateral parasitic bipolar transistor of a MOSFET to protect the silicon substrate by escaping a current in a lateral direction with respect to a silicon substrate. Meanwhile, ESD
As the number of pins mounted on one chip increases rapidly as the miniaturization of semiconductor integrated circuits progresses rapidly, the protection device is required to be further reduced in size.

[0003]

However, as the miniaturization progresses, the current concentration and the electric field concentration at the junction increase, so that the ESD protection device may be destroyed by heat generation. Therefore, there is a limit in further improving the ESD protection ability. In recent years, since the thickness of the gate insulating film of the CMOS transistor has been reduced, the gate insulating film may be broken before the ESD protection device operates (see FIG. 33). Therefore, there is a need for an ESD protection device that triggers at a lower voltage.

[0004]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an ESD protection device which does not easily cause current concentration and electric field concentration at the junction even when the device is reduced in size, and which can trigger at a lower voltage, and a method of manufacturing the same. is there.

[0005]

An ESD protection device according to the present invention is provided between a pad of a semiconductor integrated circuit chip and an internal circuit of the semiconductor integrated circuit chip. A trigger element having a diode that breaks down due to an overvoltage applied to the pad; and an ESD protection element having a vertical bipolar transistor that conducts due to the breakdown of the diode to discharge accumulated charge in the pad. Item 1).

A vertical bipolar transistor has a larger junction area if it has the same occupied area as compared with a horizontal bipolar transistor. Therefore, even if the bipolar transistor is reduced in size, current concentration and electric field concentration at the junction are less likely to occur. On the other hand, a diode can easily set a desired breakdown voltage by changing an impurity concentration or the like. Therefore, by using the breakdown voltage of the diode as a trigger of the vertical bipolar transistor, it is possible to obtain an ESD protection device that hardly causes current concentration and electric field concentration at the junction even when the size is reduced, and triggers at a low voltage.

A first specific example of the ESD protection device according to the present invention is as follows (claim 3). The pad is an input terminal or an output terminal. The trigger element comprises first and second diodes and first and second resistors. ES
The D protection element includes first and second NPN vertical bipolar transistors. The first diode has a cathode connected to the pad and an anode connected to the base of the first vertical bipolar transistor. The second diode has a cathode connected to the power supply terminal and an anode connected to the base of the second vertical bipolar transistor. A first resistor is connected between the anode of the first diode and the ground terminal. A second resistor is connected between the anode of the second diode and the pad. The first vertical bipolar transistor has a collector connected to a pad and an emitter connected to a ground terminal. The second vertical bipolar transistor is
The collector is connected to the power supply terminal, and the emitter is connected to the pad. In addition, at least one of the first diode, the first resistor and the first vertical bipolar transistor, and the second diode, the second resistor and the second vertical bipolar transistor may be provided. The same applies to the claims.)

A second specific example of the ESD protection device according to the present invention is as follows (claim 5). The pad is a power supply terminal. The vertical bipolar transistor is an NPN type. The diode has a cathode connected to the pad and an anode connected to the base of the vertical bipolar transistor. A resistor is connected between the anode of the diode and the ground terminal. In the vertical bipolar transistor, the collector is connected to the pad, and the emitter is connected to the ground terminal.

[0009] The ESD protection device according to the present invention may have the following configuration. The trigger element has a first vertical bipolar transistor whose collector and base operate as a diode that breaks down due to an overvoltage applied to the pad, and which discharges accumulated charge in the pad by conducting when the diode breaks down.
The ESD protection element has a second vertical bipolar transistor that conducts due to breakdown of the diode, thereby discharging the accumulated charge in the pad.

Specific examples in this case are as follows (claims 12 and 13). Pads are input terminals or output terminals. The trigger element includes an NPN-type vertical bipolar transistor A and a vertical bipolar transistor B that operate as a first vertical bipolar transistor, and first and second resistors. The ESD protection element includes an NPN-type vertical bipolar transistor C and a vertical bipolar transistor D that operate as a second vertical bipolar transistor. Vertical bipolar transistors A and C
Has a collector connected to a pad, a base connected to each other, and an emitter connected to a ground terminal. A first resistor is connected between the bases of the vertical bipolar transistors A and C and the ground terminal. The collectors of the vertical bipolar transistors B and D are connected to a power supply terminal, the bases are connected to each other, and the emitters are connected to pads. A second resistor is connected between the bases of the vertical bipolar transistors B and D and the pad (claim 12).

The pad is a power supply terminal. The first and second vertical bipolar transistors are of the NPN type, and have a collector connected to a pad, a base connected to each other, and an emitter connected to a ground terminal. A resistor is connected between the bases of the first and second vertical bipolar transistors and the ground terminal.

The conductivity types P and N may be N and P, respectively, of the opposite conductivity type (claims 4, 6, 14, and 15).
Even if P and N are reversed, only the type of carrier is changed, so that the same function can be realized as a matter of course. When the vertical bipolar transistor is a PNP type, the positions of the diode and the resistor are interchanged.

The diode may be a single or a plurality of diodes connected in series, the overvoltage may be a forward voltage for the diode, and the breakdown may be a substantial breakdown due to conduction. Item 2, 7-1
0). The forward voltage drop of the diode is less dependent on the impurity concentration and lower than the breakdown voltage. Therefore, by selecting the number of diodes connected in series, a desired substantial breakdown voltage can be accurately set.

The ESD protection device according to claim 11, 12, 13, 14, or 15, wherein the collector layers of the first vertical bipolar transistor and the second vertical bipolar transistor are formed at the same time. (Claim 16).

The ESD protection device according to claim 11, 12, 13, 14, or 15, wherein the collector layers of the first vertical bipolar transistor and the second vertical bipolar transistor are shared and the same. (Claim 17).

Claims 1, 2, 3, 5, 7, 9, 11, 1
The ESD protection device according to 2 or 13, wherein the vertical
Transistor or diode is a P-type silicon substrate
First N formed on the surface⁻Mold well and this first N
⁻Formed on the surface of the P-type silicon substrate in contact with the mold well
Second N⁻Mold well and this second N⁻On the surface of the mold well
The second N formed⁺Layer and the first N⁻On the surface of the mold well
P formed⁻Mold well and this P⁻On the surface of the mold well
P formed far apart⁺Layer and first N⁺Layers and this
Our P⁺Layer and first N⁺P between the layer⁺Layers and first
N⁺Insulation provided to prevent electrical connection with layers
And all or part of the second N ⁻Mold well and P
⁻P-type silicon is insulated from the mold well by an insulating insulator
Substrate and P ⁻That the mold well was insulated with the insulating material for separation.
(Claim 18). In this case, the conductive type P and
N may be N and P of the opposite conductivity type, respectively (claim
Item 19).

The ESD protection device according to claim 18, wherein the P ⁺ layer and the first and second N ⁺ layers are formed simultaneously with the P ⁺ layer and the N ⁺ layer of the CMOS transistor constituting the internal circuit. (Claim 2
0). The same applies to the ESD protection device according to claim 19 (claim 21).

18. The ESD protection device according to claim 18, wherein the second N ^- type well has a CMO constituting an internal circuit.
It may be formed simultaneously with the N ^- type well of the S transistor (claim 22). The same applies to the ESD protection device according to claim 19 (claim 2).
3).

In the ESD protection device according to claim 18 or 19, the insulator is a dummy gate electrode formed simultaneously with a gate electrode and a gate insulating film of a CMOS transistor constituting an internal circuit, or a simple insulating film. (Claim 24). The dummy gate electrode or the insulating film may be formed in a ring shape with respect to the surface of the silicon substrate.

E according to claim 1, 2, 3, 5, 7 or 9
In SD protector, diodes, N formed in a P-type silicon substrate surface ^- -type well, the N ^- -type well P ⁺ layer is formed apart from each other on the surface and the N ⁺ layer, these P ⁺ layer And an insulator formed between the surface of the P-type silicon substrate and the N ⁺ layer. In this case, claims 1, 2, 4, 6,
11. The ESD protection device according to 8 or 10, wherein the conductive type P
And N may be N and P of opposite conductivity types, respectively.

E according to claim 1, 2, 3, 5, 7 or 9
In SD protector, diodes, N formed in a P-type silicon substrate surface ^- -type well, the N ^- -type well, the P ^{- -} P formed in the mold well surface away from each other on the type well surface formed P ⁺ layer and N ⁺ layer, and an insulator attached to the surface of the P-type silicon substrate between the P ⁺ layer and the N ⁺ layer. The P-type silicon substrate and the P ^- type well are It may be insulated by a separating insulator (claim 28). In this case, claims 1, 2, 4, 6, 8
Alternatively, in the ESD protection device according to claim 10, P and N of the conductivity type may be N and P of the opposite conductivity type, respectively.

Further, the ESD protection device according to the present invention may further have the following configuration. The diode includes a P ⁻ -type well formed on the surface of the silicon substrate, an N ⁺ layer and a P ⁺ layer formed separately from each other on the surface of the P ⁻ -type well, and between the N ⁺ layer and the P ⁺ layer. And a dummy gate electrode provided on the P ^- type well through an insulating film and connected to the ground terminal. In this case, the electric field between the N ⁺ layer and the dummy gate electrode is increased, so that the trigger is performed at a lower voltage. It should be noted that the conductivity types P and N may be N and P, respectively, of the opposite conductivity type.

A method for manufacturing an ESD protection device according to the present invention
Are the claims 1, 3, 4, 5, 6, 11, 12, 13, 1
A method for manufacturing an ESD protection device according to item 4 or 15.
And the following steps (claim 32). P-type silicon
CMOS transistors that constitute internal circuits
Star N⁻Type well and vertical bipolar transistor
N for collector connection that will be connected to the collector of⁻Type
A step of forming wells simultaneously. For P-type silicon substrate
And the collector that becomes the collector of the vertical bipolar transistor
Lecter N⁻Mold well and diode N⁻Mold well
Step of forming simultaneously. Of vertical bipolar transistor
Collector N⁻Base P in mold well ⁻Mold layer, and
N of diode⁻P serving as anode in mold well⁻Mold layer
Forming simultaneously. CMOS transistor P⁻
N in mold well⁺Layer, vertical bipolar transistor
N for Lecter Connection⁻N in mold well⁺Mold layer, vertical bipolar
Transistor P⁻N as an emitter in the mold layer⁺Mold layer
And diode P⁻N serving as cathode for mold layer⁺Same mold layer
Sometimes forming process. CMOS transistor N⁻Mold
P in the well⁺Layer, P of vertical bipolar transistor⁻Type
P in layer⁺Mold layer and diode P⁻P for mold layer⁺Mold layer
Step of forming simultaneously. In this case, claim 2, 7, 8,
The method for manufacturing the ESD protection device according to 9 or 10 is as follows.
The node and the cathode are reversed (claim 33).

The ESD protection device according to the present invention is manufactured at the same time as the CMOS transistor manufacturing process except for the steps. Since the process is an ion implantation for the same portion, it is only necessary to add one mask in a normal CMOS transistor manufacturing process.

[0025] The vertical-type collector of the bipolar transistor N ^- type well and a diode the N ^- region type well is formed in the process, the step of forming simultaneously the dummy gate electrode and the gate electrode of the CMOS transistor, further comprising stuff It may be. However, the dummy gate electrode is
This prevents the N ⁺ -type layer of the vertical bipolar transistor and the diode formed in the process from being connected to the P ⁺ -type layer of the vertical bipolar transistor and the diode formed in the process in a later process. (Claim 3
4). Alternatively, the N ⁺ -type layer of the vertical bipolar transistor and the diode formed in the step, and the P ⁺ layer of the vertical bipolar transistor and the diode formed in the fifth step
^{The method} may further include a step of forming an insulating film for preventing connection with the ⁺ type layer in a later step (claim 35). Also in the method for manufacturing an ESD protection device according to the present invention, P and N of the conductivity type may be N and P of the opposite conductivity type, respectively.

In other words, the present invention provides an electrostatic discharge (ES)
As a method for protecting a semiconductor device from D), a normal CM
A trigger element operating at a low voltage and a vertical bipolar transistor are formed using a manufacturing method compatible with the OSFET manufacturing process, and an internal MOS transistor is formed when an electrostatic pulse is applied to an input / output pad or a power supply pad. The trigger element operates at a low voltage so that the gate insulating film does not break down, and the trigger current activates the vertical bipolar transistor, releasing a large amount of charge in the vertical direction of the silicon substrate to prevent current concentration, A structure of an ESD protection device characterized by obtaining an ESD resistance and a method of manufacturing the same.

[0027]

1 to 3 show an ES according to the present invention.
1 shows a first embodiment of a D protection device, FIG. 1 is a circuit diagram, FIG.
3 is a plan view, and FIG. 3 is a vertical sectional view taken along line III-III in FIG. Hereinafter, description will be made based on these drawings. The ESD protection device of the present embodiment operates as an input buffer protection circuit.

The ESD protection device according to the present embodiment is provided between an input terminal (input pad) 6 of a semiconductor integrated circuit chip and a CMOS transistor 100 and diodes 311, 31 which break down due to an overvoltage applied to the input terminal 6.
2 having a trigger element 310 and diodes 311 and 3
12 conducts due to the breakdown of the vertical bipolar transistor 21, thereby discharging the accumulated charge at the input terminal 6.
1 and 212. 2 and 3 show only the vertical bipolar transistor 211 as a part of the ESD protection element 210 and only the diode 311 as a part of the trigger element 310.

The CMOS transistor 100 is an NMOS
This is a CMOS inverter including a transistor 101 and a PMOS transistor 102. Diode 311
Has a cathode connected to the input terminal 6 and an anode connected to the base of the vertical bipolar transistor 211. The diode 312 has a cathode connected to the power supply terminal 7 and an anode connected to the base of the vertical bipolar transistor 212. A resistor 313 is connected between the anode of the diode 311 and the ground terminal 8. A resistor 314 is connected between the anode of the diode 312 and the input terminal 6. Both the vertical bipolar transistors 211 and 212 are of the NPN type. The vertical bipolar transistor 211 has a collector connected to the input terminal 6 and an emitter connected to the ground terminal 8. The vertical bipolar transistor 212
The collector is connected to the power terminal 7 and the emitter is connected to the input terminal 6. The resistors 313 and 314 are made of single crystal silicon, polycrystal silicon, metal, or the like formed in the same semiconductor integrated circuit chip.

In recent years, since the thickness of the gate insulating film has been rapidly reduced, the CMOS transistor 1 to be protected is
It is necessary for the ESD protection element 210 to operate at a lower voltage than that at which the gate insulating film of No. 00 is broken. In this embodiment,
Due to the voltage drop when the trigger current, which is the breakdown current of the diodes 311 and 312, flows through the resistors 313 and 314,
The base potentials of the vertical bipolar transistors 211 and 212 are raised to increase the vertical bipolar transistors 211 and 212.
Turn 212 on. As a result, a large amount of charge due to static electricity stored in the input terminal 6 is released in the vertical direction of the silicon substrate. Therefore, current concentration can be prevented, and a large ESD tolerance can be obtained.

Vertical bipolar transistors 211 and 21
Protection device 210 with diode 2 and diode 31
The formation of the trigger element 310 provided with 1 and 312 can be realized only by adding one ion implantation mask in a normal CMOSFET manufacturing process. Hereinafter, the manufacturing method will be described with reference to FIGS.

First, the ESD protection element 210 will be described. A collector lead portion 10 and an emitter 11 are formed simultaneously with the N ⁺ diffusion layer 1 of the CMOS transistor 100, and a base lead portion 12 is formed simultaneously with the P ⁺ diffusion layer 2 of the CMOS transistor 100. In order to separate the silicide between the emitter 11 and the base lead portion 12,
A dummy gate electrode 13 formed simultaneously with the gate electrode 3 of the CMOS transistor 100 is used. The dummy gate electrode 13 does not apply a potential but separates silicide. Then, an opening 50 is formed in the resist using an additional ion implantation mask, and ions are implanted, thereby forming the base 16 of the P ⁻ region.
And a collector N well 17 are simultaneously formed. The collector N well 17 formed at this time and the collector lead portion 10 formed separately are connected to the N
The connection is made using a connection N-well 14 formed simultaneously with the well 5. Thereby, a vertical bipolar transistor can be formed using a CMOS process. The ion implantation at this time may be performed before or after the formation of the gate electrode 3.

Next, the trigger element 310 will be described. N⁺
P⁻Type diode is the emitter of the ESD protection element 210.
CMOS transistor with the same structure as the
Star 100 N⁺N at the same time as diffusion layer 1⁺The part 21
P of OS transistor 100 ⁺P at the same time as the diffusion layer 2⁻Department
26 lead-out portions 22 are formed. This allows the desired
Trigger voltage and reverse leak level can be set
Become.

FIGS. 4 to 6 are sectional views showing a method of manufacturing the ESD protection device of the present embodiment. Hereinafter, FIGS. 3 to 6
Based on the above, a method for manufacturing the ESD protection device of the present embodiment will be described in detail.

First, as shown in FIG.
Simultaneously with the formation of the N well 5 of the transistor 100, the ESD protection element
N-well for connection of the child 210 with the collector drawer 10
14 is formed. The doping concentration in this region is about 10
¹⁷cm^-3-10¹⁸cm ^-3It is. Also, CMO
Simultaneously with the formation of the gate electrode 3 of the S transistor 100,
The dummy gate electrode 13 of the ESD protection element 210 and the
The dummy gate electrode 23 of the trigger element 310 is formed. This
This is because the emitter 11 of the ESD protection element 210 and the base
The exposed portion 12 is formed by a silicon layer formed on the diffusion layer later.
This is to prevent connection due to a password. same
Thus, N of the trigger element 310⁺Part 21 and drawer part 22
To prevent later connection by silicide.
It is.

Subsequently, as shown in FIG. 5, the ESD protection element 2 is
Ion implantation to form ten bases 16
Carried out at ¹⁸ cm ^-3, is then performed by ion implantation of about ¹⁰ 18 ^{cm -3} to form the collector N-well 17. At this time, the P ⁻ portion 26 and the N well 27 of the trigger element 310 are also formed at the same time.

Subsequently, as shown in FIG. 6, simultaneously with the formation of the N ⁺ diffusion layer 1 of the CMOS transistor 100, the collector lead portion 10, the emitter 11, the N ⁺ portion 21 and the like are formed.

Subsequently, as shown in FIG. 3, simultaneously with the P ⁺ diffusion layer 2 of the CMOS transistor 100, a base lead portion 12, a lead portion 22, and the like are formed. Finally, by forming wiring on these layers, the circuit shown in FIG. 1 is formed.

Next, the operation of the ESD protection device according to the present embodiment will be described with reference to FIGS.

The operation when an electrostatic pulse is applied to the input terminal 6 will be described. First, when a positive ESD pulse is applied to the input terminal 6 with respect to the ground terminal 8,
SD protection element 210, trigger element 310, and CMO
A high voltage is applied to the gate insulating film of the S transistor 100. Therefore, before the gate insulating film of the CMOS transistor 100 is destroyed, it is necessary that the ESD protection element 210 operates to quickly release the charge due to the ESD.

Assuming that the gate insulating film of the CMOS transistor 100 has a thickness of 4 nm, the gate insulating film is broken at about 8 V by a constant voltage stress. That is, the ESD protection element 210 needs to operate at a lower voltage. However, the vertical bipolar transistor ES
When the D protection element 210 is formed, the collector N well 1
Since the withstand voltage between the gate 7 and the base 16 is about 10 V, this alone cannot protect the fine CMOS transistor 100 having a thin gate insulating film.

Therefore, a trigger element 310 that operates at a voltage as low as possible above the power supply voltage is required. Since the trigger element 310 has the P ⁻ portion 26 formed by ion implantation, a desired trigger voltage or a leak level in the reverse direction can be set by controlling the dose.
It is easy to obtain a trigger voltage of about V.

FIG. 7 shows current-voltage characteristics when an ESD electrostatic pulse is applied to the pad. First, when the trigger element 310 operates at about 4 V, the trigger current and the resistor 313 increase the base potential of the ESD protection element 210, and operate the ESD protection element 210. When the ESD protection element 210 operates, the charge applied to the input terminal 6 by the ESD can be released to the ground terminal 8 by using the vertical bipolar transistor 211. For this reason,
If the withstand voltage of the gate insulating film of the CMOS transistor 100 of the internal circuit is 8 V, the charge can be released at a lower voltage, so that the breakdown of the gate insulating film can be prevented.

Further, a negative ESD with respect to the ground terminal 8
Is applied to the input terminal 6, the pulse E shown in FIG.
Collector N well 17 of SD protection element 210 and P substrate 5
1 and is, N ⁺ P ^- to become forward can escape rapidly charge.

FIG. 8 shows a breakdown current value per unit length when the ESD protection device of the present embodiment is used and when a lateral parasitic bipolar transistor of a conventional MOS transistor is used. The breakdown current value of the ESD protection element including the vertical bipolar transistor of the present embodiment is larger than that of the horizontal bipolar transistor. When the thickness of the internal gate insulating film is reduced to about 2 nm, the breakdown current value of the lateral bipolar transistor decreases sharply.
The decrease is slight in the vertical bipolar transistor.

FIG. 9 is a circuit diagram showing a second embodiment of the ESD protection device according to the present invention. Hereinafter, description will be made based on this drawing. The ESD protection device according to the present embodiment operates as a power supply protection circuit.

The ESD protection device of the present embodiment comprises a power supply terminal (power supply pad) 7 of a semiconductor integrated circuit chip and an internal circuit 1.
And a trigger element 315 having a diode 316 that breaks down due to an overvoltage applied to the power supply terminal 7 and a vertical bipolar that conducts due to the breakdown of the diode 316 and discharges the accumulated charge at the power supply terminal 7. ESD protection element 213 having transistor 214
And

The diode 316 has a cathode connected to the power supply terminal 7 and an anode connected to the base of the vertical bipolar transistor 214. A resistor 317 is connected between the anode of the diode 316 and the ground terminal 8. The vertical bipolar transistor 214
It is an NPN type. The collector is connected to the power supply terminal 7 and the emitter is connected to the ground terminal 8.

The plan view and the sectional view are the same as those in FIGS. 2 and 3 except for the reference numerals. Therefore, the ESD protection device of the present embodiment also has the same operation and effect as the first embodiment.

10 to 15 show a third embodiment of the ESD protection device according to the present invention. FIG. 10 is a plan view and FIG.
Is a vertical sectional view taken along line XI-XI in FIG. 10, and FIGS.
FIG. 3 is a cross-sectional view illustrating a manufacturing method. Hereinafter, description will be made based on these drawings. However, the same parts as those in FIG. 2 to FIG.

In the ESD protection device of this embodiment, instead of the dummy gate electrodes 13 and 23 for isolating silicide (FIGS. 2 and 3), an insulating layer covering the diffusion layer so that silicide is not formed for forming a resistance element or the like. Films 18 and 28 (SiO
₂ or SiN).

First, as shown in FIG. 12, simultaneously with the formation of the N well 5 of the CMOS transistor 100, the N well 14 for connection with the collector lead-out portion 10 of the ESD protection element 200 is formed.

Subsequently, as shown in FIG. 13, ion implantation for forming the base 16 of the ESD protection element 200 is performed using the opening 50 of the resist having a predetermined shape as a mask, and then the collector N well 17 is formed. Ion implantation for formation is performed. In this case, P of the trigger element 300 ^- Part 26 and N-well 27 are simultaneously formed.

Subsequently, as shown in FIG. 14, at the same time as the formation of the N ⁺ diffusion layer 1 of the CMOS transistor 100, a collector lead portion 10, an emitter 11, an N ⁺ portion 21 and the like are formed.

Subsequently, as shown in FIG. 15, at the same time as the P ⁺ diffusion layer 2 of the CMOS transistor 100, a base lead portion 12, a lead portion 22, and the like are formed.

Subsequently, as shown in FIG. 11, in the ESD protection element 200, the insulating film 18 and the trigger element 310
Then, an insulating film 28 is formed. This is because the emitter 11 and the base lead portion 12 of the ESD protection element 200 are
This is for preventing connection by a silicide formed on the diffusion layer later. Similarly, trigger element 3
This is to prevent the N ⁺ part 21 of 00 and the lead part 22 from being connected by silicide.

Finally, a circuit shown in FIG. 1 is formed by forming a wiring in these upper layers.

FIGS. 16 to 18 show a fourth embodiment of the ESD protection device according to the present invention. FIG.
FIG. 18 is a plan view, and FIG. 18 is a vertical sectional view taken along line XVIII-XVIII in FIG. Hereinafter, description will be made based on these drawings. In the ESD protection device of the present embodiment, the trigger element
The protection element operates as a vertical bipolar transistor.

The ESD protection device according to the present embodiment includes a power supply terminal (power supply pad) 7 of a semiconductor integrated circuit chip and an internal circuit 1.
And a trigger element 400 having a diode 402 that breaks down due to an overvoltage applied to the power supply terminal 7, and a vertical bipolar that conducts due to the breakdown of the diode 402 and discharges the accumulated charge at the power supply terminal 7. ESD protection element 200 having transistor 201
And

The diode 402 is between the collector ^{and the} base of the vertical bipolar transistor 401. The cathode of the diode 402, that is, the collector of the vertical bipolar transistor 401 is connected to the power supply terminal 7, and the anode of the diode 402, that is, the base of the vertical bipolar transistor 401 is connected to the vertical bipolar transistor 201.
Connected to the base. A resistor 403 is connected between the anode of the diode 402, that is, the base of the vertical bipolar transistor 401 and the ground terminal 8. The vertical bipolar transistors 201 and 402 are
It is an NPN type. The collector is connected to the power supply terminal 7 and the emitter is connected to the ground terminal 8.

In the present embodiment, the emitter lead-out section 40 is also provided in the trigger element 400 and connected as shown in FIGS. When connected in this manner, the trigger element 400
Since the vertical bipolar transistor 401 is also formed, the trigger element 400 also operates as an ESD protection element. N ⁺ part (collector) of trigger element 400
A diode 40 comprising a base 41 and a P ^- part (base) 46;
2, the base potentials of the vertical bipolar transistors 201 and 401 increase due to the trigger current and the resistor 403.
By operating these together, the electric charge of the power supply terminal 7 due to the static electricity can be released by both. Although the ESD protection device of the present embodiment is applied to a power supply pad, it may be applied to an input pad or an output pad by providing two as in the first embodiment.

FIGS. 19 and 20 are sectional views showing a method of manufacturing the ESD protection device according to the present embodiment. Hereinafter, a method of manufacturing the ESD protection device according to the present embodiment will be described in detail with reference to FIGS.

First, simultaneously with the formation of the N well 5 of the CMOS transistor 100, the connection well 14 for connection with the collector lead-out portion 10 of the ESD protection element 200 and the emitter connection N well 44 of the trigger element 400 are formed.

Subsequently, as shown in FIG. 19, ion implantation for forming the base 16 of the ESD protection element 200 is performed using the opening 50 of the resist having a predetermined shape as a mask, and then the collector N well 17 is formed. Is performed to perform ion implantation. At this time, the P ^- section 4 of the trigger element 400
6 and the emitter N-well 47 are also formed at the same time.

Subsequently, as shown in FIG. 20, simultaneously with the formation of the N ⁺ diffusion layer 1 of the CMOS transistor, the collector lead portion 10 and the emitter 1 of the ESD protection element 200 are formed.
1, and the emitter lead-out part 40 of the trigger element 400
And a collector 41. Subsequently, at the same time as the P ⁺ diffusion layer 2 of the CMOS transistor 100, the P ⁻ part 4 serving as the base of the base lead-out part 12 and the trigger element 400.
6 are formed.

Subsequently, the insulating film 1 of the ESD protection element 200
8 and the insulating film 48 of the trigger element 400 are formed. This is to prevent the emitter 11 and the base lead portion 12 of the ESD protection element 200 from being connected by silicide formed on the diffusion layer later. Similarly, it is to prevent the N ⁺ portion 41 and the lead portion 42 of the trigger element 400 from being connected by silicide.

Finally, wiring is formed on these layers to form the circuit shown in FIG.

FIGS. 21 and 22 show a fifth embodiment of the ESD protection device according to the present invention. FIG. 21 is a plan view and FIG.
FIG. 22 is a vertical sectional view taken along the line XXII-XXII in FIG. 21. Less than,
Description will be made based on these drawings. In the ESD protection device of the present embodiment, the collector of the ESD protection element is shared in order to reduce the area.

The ESD protection element 230 according to the present embodiment
Is the ES in the third embodiment shown in FIG. 10 and FIG.
The two collector N wells 17 of the D protection element 200 are shared to form one collector N well 17 '. The area is reduced by using the collector lead-out portion 10 only at both ends of the collector N well 17 '. The method for manufacturing the ESD protection device according to the present embodiment is the same as that of the third embodiment shown in FIGS.

FIGS. 23 and 24 show a sixth embodiment of the ESD protection device according to the present invention. FIG.
FIG. 24 is a vertical sectional view taken along line XXIV-XXIV in FIG. 23. Less than,
Description will be made based on these drawings. The ESD protection device of the present embodiment uses a common ESD protection element and trigger element in order to reduce the area.

The ESD protection element 240 according to the present embodiment
The trigger element 310 and the two bases 16 and the P ^- section 26 of the ESD protection element 200 and the trigger element 300 in the third embodiment shown in FIGS. The two collector N-wells 17 and 27 of the ESD protection element 200 and the trigger element 300 in the three embodiments are shared to form one collector N-well 19. The collector lead-out section 10 of the ESD protection element 240
By reducing the area only. The method for manufacturing the ESD protection device according to the present embodiment is the same as that of the third embodiment shown in FIGS.

FIG. 25 is a longitudinal sectional view showing a seventh embodiment of the ESD protection device according to the present invention. Hereinafter, description will be made based on this drawing. The ESD protection device according to the present embodiment is a trigger element capable of triggering at a lower voltage.

The ESD protection device according to the present embodiment is the same as the first embodiment except that the dummy gate electrode 23 of the trigger element 310 is fixed to the ground.
When the dummy gate electrode 23 of the trigger element 310 is fixed to the ground, the electric field between the N ⁺ part 21 and the dummy gate electrode 23 is increased, so that the trigger is performed at a lower voltage.

FIGS. 26 and 27 show an eighth embodiment of the ESD protection device according to the present invention. FIG. 26 is a circuit diagram, and FIG.
Is a longitudinal sectional view. Hereinafter, description will be made based on these drawings. However, the same parts as those in FIG. 1 and FIG. The ESD protection device of the present embodiment operates as an input buffer protection circuit.

The ESD protection device according to the present embodiment is provided between an input terminal (input pad) 6 of a semiconductor integrated circuit chip and a CMOS transistor 100 and breaks down due to an overvoltage applied to the input terminal 6.
Trigger element 510 having two and diodes 511 and 5
12 conducts due to the breakdown of the vertical bipolar transistor 21, thereby discharging the accumulated charge at the input terminal 6.
1 and 212. The diodes 511 and 512 are a plurality of diodes connected in series, the overvoltage is a forward voltage for the diodes 511 and 512, and the breakdown is a substantial breakdown due to conduction. The diode 51
In FIG. 26, 1, 512 are shown as four diodes connected in series, but in FIG. 27, two diodes are connected in series and simplified for convenience.

The diode 511 has a cathode connected to the base of the vertical bipolar transistor 211 and an anode connected to the input terminal 6. Diode 512
Has a cathode connected to the base of the vertical bipolar transistor 212 and an anode connected to the power supply terminal 7. A resistor 313 is connected between the cathode of the diode 511 and the ground terminal 8. Diode 51
A resistor 314 is connected between the input terminal 6 and the cathode 2.

Vertical bipolar transistors 211 and 21
2 is the same as in the first embodiment. Diode 5
Numerals 11 and 512 are formed by an N + diffusion layer 1, a P + diffusion layer 2, an N well 5, and the like formed during a normal CMOS process.

In the first embodiment, breakdown of a reverse diode is used as a trigger element. On the other hand, in the present embodiment, a trigger element 510 in which forward diodes are connected in multiple stages so as to be higher than the power supply voltage is used.

In particular, a low-voltage operation device of 1.5 V or less has a very thin gate insulating film, and is broken by application of 5 V or more. To realize a low voltage trigger that can prevent gate insulating film breakdown in this voltage region,
This embodiment is effective. In the present embodiment, a desired trigger voltage can be secured by changing the number of series-connected diodes in accordance with the power supply voltage.

FIG. 28 is a graph showing a comparison result of characteristics between a trigger element using breakdown of a reverse diode and a trigger element in which forward diodes are connected in multiple stages in series. Hereinafter, description will be made based on this drawing.

In the case of utilizing the breakdown in the reverse direction, when a trigger of 5 V or less is to be performed, the voltage can be slightly lowered by increasing the concentration of the junction, but at the same time, Zener leak increases before breakdown. Therefore, there is a disadvantage that off-leakage during normal LSI operation increases. for that reason,
It is difficult to further reduce the breakdown voltage. Therefore, by supplying a current to the base of the vertical bipolar transistor using a trigger element in which forward diodes are connected in multiple stages, an ESD protection element that triggers at a lower voltage can be realized.

FIG. 29 is a graph showing current-voltage characteristics when an ESD electrostatic pulse is applied to a pad in the ESD protection device of this embodiment. Hereinafter, description will be made based on this drawing.

Assuming that the trigger voltage for one diode stage is Vf (about 0.6 V), the trigger voltage of a diode having four stages connected in series is Vf × 4 = about 2.4 V. When an ESD surge is applied to the pad and exceeds 2.4 V, this forward series diode conducts and injects current into the base of the vertical bipolar transistor. The trigger current activates the vertical bipolar transistor, which is a protection element with a high driving force, and discharges the ESD charge.

Recently, a CMO operating at a low voltage of about 1.2 V
In the S device, an extremely thin gate insulating film having a thickness of about 2.5 nm or less is used. The breakdown voltage of this gate insulating film is about 4 to 5V. In such a case, by connecting the forward diodes in multiple stages in series, the CMO
By setting the trigger voltage to be higher than the power supply voltage of the S internal circuit, it is possible to trigger an ESD discharge below the breakdown voltage of the gate insulating film without causing a malfunction during the actual operation of the LSI. Become.

FIG. 30 is a circuit diagram showing a ninth embodiment of the ESD protection device according to the present invention. Hereinafter, description will be made based on this drawing. The ESD protection device according to the present embodiment operates as a power supply protection circuit.

The ESD protection device according to the present embodiment comprises a power supply terminal (power supply pad) 7 of a semiconductor integrated circuit chip and an internal circuit 1.
And a trigger element 515 having a diode 516 that breaks down due to an overvoltage applied to the power supply terminal 7 and a vertical bipolar that conducts due to the breakdown of the diode 516 and discharges the charge stored in the power supply terminal 7. ESD protection element 213 having transistor 214
And The diode 516 has a plurality of diodes connected in series, the overvoltage is a forward voltage for the diode 516, and the breakdown is a substantial breakdown due to conduction.

The diode 516 has a cathode connected to the base of the vertical bipolar transistor 214 and an anode connected to the power supply terminal 7. A resistor 317 is connected between the cathode of the diode 516 and the ground terminal 8. The vertical bipolar transistor 214
It is an NPN type. The collector is connected to the power supply terminal 7 and the emitter is connected to the ground terminal 8.

The sectional view is based on FIG. Therefore, the ESD protection device according to the present embodiment also has the same operation and effect as the eighth embodiment.

FIG. 31 is a sectional view showing a tenth embodiment of the ESD protection device according to the present invention. Hereinafter, description will be made based on this drawing. The circuit diagram of the ESD protection device of the present embodiment is the same as that of the eighth embodiment (FIG. 26).

In this embodiment, as the trigger element 510, a diode formed at the same time as forming a vertical bipolar transistor is used by being serially connected in the forward direction. In the eighth embodiment shown in FIG. 27, a diode including the P + layer 2 / N well 5 is used. On the other hand, in the present embodiment, a diode including the N + layer 521 / P− layer 526 formed when forming the vertical bipolar transistor is used. In a high current region such as at the time of an ESD charge discharge, the resistance of the well is dominant, and this resistance determines the discharge capability.

The diode composed of P + layer 2 / N well 5 shown in FIG. 27 has a large resistance because a current flows below the separation band. In contrast, in the present embodiment, the P + layer 5
22 / N + layer 521 is separated by the dummy gate 523 when the vertical bipolar transistor is formed, and the concentration of the P− layer 526 can be adjusted by additional implantation of the vertical bipolar transistor. And the resistance can be reduced.

The P + layer 2 / N well 5 shown in FIG.
Since a parasitic vertical bipolar transistor composed of the P + layer 2 / N well 5 / P substrate 51 is formed in the diode of, a current flowing through the P substrate 51 is generated. Therefore, the current supplied to the base of the vertical bipolar transistor, which is a protection element, decreases. However, in the present embodiment, the diode composed of the N + layer 521 / P− layer 526 has a N well 527 formed simultaneously with the collector layer 17 of the ESD protection element 210, and therefore, cannot block a current flowing in the vertical direction. So you can
A current can be efficiently supplied to the base of the ESD protection element 210 (see FIG. 32). Therefore, according to the present embodiment, the trigger current can be supplied to the base of the vertical bipolar transistor with high efficiency, so that the size of the trigger element can be reduced.

The present invention is, of course, not limited to the first to tenth embodiments. For example, P-type may be referred to as N-type, and N-type may be referred to as P-type. Accordingly, the NPN type may be replaced with the PNP type by setting the N type and the P type to the opposite conductivity types.

[0094]

According to the ESD protection device of the present invention,
By using the breakdown voltage of the diode as a trigger of the vertical bipolar transistor, current concentration and electric field concentration at the junction hardly occur even when the size is reduced, and characteristics of triggering at a low voltage can be easily realized. According to the method for manufacturing an ESD protection device according to the present invention, the ESD protection device according to the present invention can be easily manufactured only by adding one mask to a normal CMOS process.

In other words, the effects of the present invention are as follows. The first effect is that the current is released in the vertical direction by using a vertical bipolar transistor, so that the conventional CMOS transistor is used.
Since the current concentration is less than that of the SFET that uses a parasitic bipolar transistor to flow current in the lateral direction,
The ESD protection element itself is not easily broken. The second effect is that, since the current that can be discharged in the same area is large, the area required for the ESD protection element can be reduced, so that the input capacitance required for high-speed operation can be reduced. The third effect is that a vertical bipolar transistor and a trigger element can be formed only by adding one ion implantation mask for an ESD protection circuit to a general CMOSFET process without using a BiCMOS process. CM
It can be manufactured by an OSFET compatible process. The fourth effect is
Since it has a trigger element that operates at low voltage, CMO
Destruction of the gate insulating film of the SFET can be prevented. The fifth effect is that it is possible to form an element that triggers at a desired voltage.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an ESD protection device according to the present invention.

FIG. 2 is a plan view of the ESD protection device of FIG. 1;

FIG. 3 is a vertical sectional view taken along line III-III in FIG. 2;

FIG. 4 is a sectional view illustrating a method of manufacturing the ESD protection device of FIGS. 2 and 3;

FIG. 5 is a cross-sectional view illustrating the method of manufacturing the ESD protection device in FIGS. 2 and 3;

FIG. 6 is a cross-sectional view illustrating the method of manufacturing the ESD protection device in FIGS. 2 and 3;

FIG. 7 is a diagram showing an example of the ESD protection device shown in FIG.
9 is a graph showing current-voltage characteristics when an electrostatic pulse of D is applied.

8 is a graph showing a breakdown current value per unit length when the ESD protection device of FIG. 1 is used and when a horizontal parasitic bipolar transistor of a conventional MOS transistor is used.

FIG. 9 is a circuit diagram showing a second embodiment of the ESD protection device according to the present invention.

FIG. 10 is a plan view showing a third embodiment of the ESD protection device according to the present invention.

11 is a vertical sectional view taken along line XI-XI in FIG.

FIG. 12 is a sectional view illustrating the method of manufacturing the ESD protection device in FIGS. 10 and 11;

FIG. 13 is a cross-sectional view illustrating the method of manufacturing the ESD protection device in FIGS. 10 and 11;

FIG. 14 is a cross-sectional view illustrating the method of manufacturing the ESD protection device in FIGS. 10 and 11;

FIG. 15 is a cross-sectional view illustrating the method of manufacturing the ESD protection device in FIGS. 10 and 11;

FIG. 16 is a circuit diagram showing a fourth embodiment of the ESD protection device according to the present invention.

17 is a plan view showing the ESD protection device of FIG.

18 is a vertical sectional view taken along line XVIII-XVIII in FIG.

FIG. 19 is a sectional view illustrating the method of manufacturing the ESD protection device in FIG. 16;

FIG. 20 is a sectional view illustrating the method of manufacturing the ESD protection device in FIG. 16;

FIG. 21 is a plan view showing a fifth embodiment of the ESD protection device according to the present invention.

22 is a vertical sectional view taken along the line XXII-XXII in FIG. 21.

FIG. 23 is a plan view showing a sixth embodiment of the ESD protection device according to the present invention.

24 is a vertical sectional view taken along line XXIV-XXIV in FIG.

FIG. 25 is a sectional view showing a seventh embodiment of the ESD protection device according to the present invention.

FIG. 26 is a circuit diagram showing an eighth embodiment of the ESD protection device according to the present invention.

FIG. 27 is a longitudinal sectional view of the ESD protection device of FIG. 26;

FIG. 28 is a graph showing a comparison result of characteristics between a trigger element using breakdown of a reverse diode and a trigger element in which forward diodes are connected in multiple stages in series.

FIG. 29 is a graph showing current-voltage characteristics when an ESD electrostatic pulse is applied to a pad in the ESD protection device of FIG. 26;

FIG. 30 is a circuit diagram showing a ninth embodiment of the ESD protection device according to the present invention.

FIG. 31 is a sectional view showing a tenth embodiment of the ESD protection device according to the present invention.

FIG. 32 (a) is a cross-sectional view showing a diode formed of a P + layer / N well formed by an existing CMOS process according to the eighth embodiment. FIG. 32 (b)
It is sectional drawing which shows the diode which utilized a part of vertical bipolar transistor in 10th Embodiment.

FIG. 33 is a graph showing current-voltage characteristics when an ESD electrostatic pulse is applied to a pad in a conventional technique.

[Description of Signs] 6 Input terminal (pad) 7 Power supply terminal (pad) 8 Ground terminal (pad) 311, 312, 316, 402, 511, 512, 5
16 Diode 300, 310, 315, 400, 510, 515 Trigger element 201, 211, 212, 214 Vertical bipolar transistor 200, 210, 213, 230, 240 ESD protection element

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/04 27/092

Claims (36)

[Claims] An ES provided between a pad of a semiconductor integrated circuit chip and an internal circuit of the semiconductor integrated circuit chip.
In the D protection device, a trigger element having a diode that breaks down due to an overvoltage applied to the pad; and an ESD protection element having a vertical bipolar transistor that discharges accumulated charge in the pad by being turned on by the breakdown of the diode. An ESD protection device, comprising: 2. The diode according to claim 1, wherein one or more diodes are connected in series, the overvoltage is a forward voltage for the diode, and the breakdown is a substantial breakdown due to conduction. 2. The ESD protection device according to claim 1. 3. The pad is an input terminal or an output terminal, the trigger element includes first and second diodes and first and second resistors, and the ESD protection element is an NPN-type first and second diode. The second vertical bipolar transistor, wherein the first diode has a cathode connected to the pad, an anode connected to the base of the first vertical bipolar transistor, and the second diode has a cathode Is connected to a power supply terminal, an anode is connected to the base of the second vertical bipolar transistor, and the first resistor is connected between an anode of the first diode and a ground terminal; The second resistor is connected between the anode of the second diode and the pad, and the first vertical bipolar transistor is A collector connected to the power supply terminal, an emitter connected to the pad, an emitter connected to the pad, an emitter connected to the ground terminal, and an emitter connected to the ground terminal. 2. The ESD according to claim 1, further comprising at least one of the first resistor and the first vertical bipolar transistor, and at least one of the second diode, the second resistor, and the second vertical bipolar transistor. 3. Protective equipment. 4. The pad is an input terminal or an output terminal, the trigger element comprises first and second diodes and first and second resistors, and the ESD protection element is a PNP-type first and second ESD protection element. The second vertical bipolar transistor, the first diode has a cathode connected to the base of the first vertical bipolar transistor, an anode connected to a ground terminal, and the second diode has a cathode Is connected to the base of the second vertical bipolar transistor, the anode is connected to the pad, and the first resistor is connected between the cathode of the first diode and the pad. The second resistor is connected between the cathode of the second diode and the power supply terminal, and the first vertical bipolar transistor is A collector connected to the ground terminal, an emitter connected to the pad, the second vertical bipolar transistor has a collector connected to the pad, an emitter connected to the power supply terminal, the first diode, 2. The ESD according to claim 1, further comprising at least one of the first resistor and the first vertical bipolar transistor, and at least one of the second diode, the second resistor, and the second vertical bipolar transistor. 3. Protective equipment. 5. The pad is a power supply terminal, the vertical bipolar transistor is an NPN type, the diode has a cathode connected to the pad,
An anode is connected to the base of the vertical bipolar transistor, and between the anode of the diode and a ground terminal,
The ESD protection device according to claim 1, wherein a resistor is connected, a collector of the vertical bipolar transistor is connected to the pad, and an emitter is connected to the ground terminal. 6. The pad is a power supply terminal, the vertical bipolar transistor is a PNP type, the diode has a cathode connected to the base of the vertical bipolar transistor, an anode connected to a ground terminal, The ESD according to claim 1, wherein a resistor is connected between a cathode of the diode and the power supply terminal, and a collector of the vertical bipolar transistor is connected to the ground terminal, and an emitter is connected to the pad. Protective equipment. 7. The pad is an input terminal or an output terminal, the trigger element comprises first and second diodes and first and second resistors, and the ESD protection element is an NPN-type first and second diode. A second bipolar transistor, wherein the first diode has an anode connected to the pad, a cathode connected to the base of the first vertical bipolar transistor, and the second diode has an anode Is connected to a power supply terminal, a cathode is connected to a base of the second vertical bipolar transistor, and a first resistor is connected between a cathode of the first diode and a ground terminal; The second resistor is connected between the cathode of the second diode and the pad, and the first vertical bipolar transistor is A collector connected to the power supply terminal, an emitter connected to the pad, an emitter connected to the pad, an emitter connected to the ground terminal, and an emitter connected to the ground terminal. The ESD according to claim 2, further comprising at least one of the first resistor and the first vertical bipolar transistor, and the second diode, the second resistor, and the second vertical bipolar transistor. Protective equipment. 8. The pad is an input terminal or an output terminal, the trigger element comprises first and second diodes and first and second resistors, and the ESD protection element is a PNP-type first and second ESD protection element. The second vertical bipolar transistor, wherein the first diode has an anode connected to the base of the first vertical bipolar transistor, a cathode connected to the ground terminal, and the second diode has an anode Is connected to the base of the second vertical bipolar transistor, the cathode is connected to the pad, and the first resistor is connected between the anode of the first diode and the pad; The second resistor is connected between the anode of the second diode and the power supply terminal, and the first vertical bipolar transistor is A collector connected to the ground terminal, an emitter connected to the pad, the second vertical bipolar transistor has a collector connected to the pad, an emitter connected to the power supply terminal, the first diode, The ESD according to claim 2, further comprising at least one of the first resistor and the first vertical bipolar transistor, and the second diode, the second resistor, and the second vertical bipolar transistor. Protection device. 9. The pad is a power supply terminal, the vertical bipolar transistor is an NPN type, the diode has an anode connected to the pad,
A cathode is connected to the base of the vertical bipolar transistor, and between the cathode of the diode and a ground terminal,
A resistor is connected, a collector of the vertical bipolar transistor is connected to the pad, an emitter is connected to the ground terminal, the first diode, the first resistor and the first vertical bipolar transistor, The ESD protection device according to claim 2, further comprising at least one of the second diode, the second resistor, and the second vertical bipolar transistor. 10. The pad is a power supply terminal, the vertical bipolar transistor is a PNP type, the diode has an anode connected to the base of the vertical bipolar transistor, a cathode connected to a ground terminal, Between the anode of the diode and the power supply terminal,
A resistor is connected, the vertical bipolar transistor has a collector connected to the ground terminal, an emitter connected to the pad, the first diode, the first resistor, and the first vertical bipolar transistor, The ESD protection device according to claim 2, further comprising at least one of the second diode, the second resistor, and the second vertical bipolar transistor. 11. An E chip provided between a pad of a semiconductor integrated circuit chip and an internal circuit of the semiconductor integrated circuit chip.
In the SD protection device, a collector and a base operate as a diode that breaks down due to an overvoltage applied to the pad, and a first vertical bipolar transistor that discharges accumulated charge in the pad by conducting due to breakdown of the diode. An ESD protection device, comprising: a trigger element having the same; and an ESD protection element having a second vertical bipolar transistor that discharges accumulated charges in the pad by being rendered conductive by breakdown of the diode. 12. The pad is an input terminal or an output terminal, and the trigger element is an NPN vertical bipolar transistor A and a vertical bipolar transistor B operating as the first vertical bipolar transistor; And the second resistor. The ESD protection element includes an NPN-type vertical bipolar transistor C and a vertical bipolar transistor D that operate as the second vertical bipolar transistor, and the vertical bipolar transistor A, C has a collector connected to the pad, a base connected to each other, an emitter connected to the ground terminal, and a first resistor between the base of the vertical bipolar transistors A and C and the ground terminal. The collectors of the vertical bipolar transistors B and D have a power supply. The second resistor is connected between the bases of the vertical bipolar transistors B and D and the pad, and the first resistor is connected between the pad and the pad. And at least one of the second resistance and the second vertical bipolar transistor, and the second resistance and the second vertical bipolar transistor.
The ESD protection device according to any one of the preceding claims. 13. The power supply terminal of the pad, wherein the first and second vertical bipolar transistors are N-type.
A PN type, a collector is connected to the pad, a base is connected to each other, an emitter is connected to a ground terminal, and between the bases of the first and second vertical bipolar transistors and the ground terminal, The ESD protection device according to claim 11, wherein a resistor is connected. 14. The pad is an input terminal or an output terminal; the trigger element is a PNP-type vertical bipolar transistor A and a vertical bipolar transistor B operating as the first vertical bipolar transistor; And a second resistor. The ESD protection element includes a PNP-type vertical bipolar transistor C and a vertical bipolar transistor D that operate as the second vertical bipolar transistor. C has an emitter connected to the pad, a base connected to each other, a collector connected to the ground terminal, and a first resistor connected between the base of the vertical bipolar transistors A and C and the pad terminal. The vertical bipolar transistors B and D have emitters connected to a power supply terminal. , The base is connected to each other, the collector is connected to the pad, the second resistor is connected between the base of the vertical bipolar transistors B and D and the power supply terminal, And at least one of the second resistance and the second vertical bipolar transistor, and the second resistance and the second vertical bipolar transistor.
The ESD protection device according to any one of the preceding claims. 15. The device according to claim 15, wherein the pad is a power supply terminal, and the first and second vertical bipolar transistors are
An NP type, a collector is connected to a ground terminal, a base is connected to each other, an emitter is connected to the pad, and a resistor is provided between the base of the first and second vertical bipolar transistors and the pad. The ESD protection device according to claim 11, wherein is connected. 16. The ESD protection according to claim 11, wherein the collector layers of the first vertical bipolar transistor and the second vertical bipolar transistor are formed at the same time. apparatus. 17. The ESD according to claim 11, wherein the first vertical bipolar transistor and the second vertical bipolar transistor have a common collector layer. Protective equipment. 18. The method of claim 17, wherein vertical bipolar transistor or the diode, the first N formed in the P-type silicon substrate surface ^- -type well and this first N ^- said P-type silicon substrate surface in contact with the mold wells second N formed ^- -type well and, the second N ^- -type and a second N ⁺ layer formed on the well surface, the first N ^- type well formed on a surface the P ^- -type A well, a P ⁺ layer and a first N ⁺ layer formed apart from each other on the surface of the P ⁻ -type well, and the P ⁺
Consists all or part of the annexed been insulator to prevent electrical connection between the P ⁺ layer and the first N ⁺ layer between the layer and the first N ⁺ layer, the second 4. The N ^- type well and the P ^- type well are insulated by a separating insulator, and the P-type silicon substrate and the P ^- type well are insulated by a separating insulator. The ESD protection device according to claim 7, 5, 7, 9, 11, 12, or 13. 19. The vertical bipolar transistor or the diode, the first P formed in N-type silicon substrate surface ^- -type well and, this first P ^- the N-type silicon substrate surface in contact with the mold wells second P formed ^- -type well and, the second P ^- type and a second P ⁺ layer formed on the well surface, the first P ^- -type well surface which is formed in the N ^- type A well, an N ⁺ layer and a first P ⁺ layer formed apart from each other on the surface of the N ⁻ type well, and these N ⁺
Comprising all or part of the annexed been insulator to prevent electrical connection between the P ⁺ layer and the first N ⁺ layer between the layer and the first P ⁺ layer, the second 5. The P ^- type well and the N ^- type well are insulated by a separating insulator, and the N-type silicon substrate and the N ^- type well are insulated by a separating insulator. , 6, 8, 10, 11, 14, or 15
The ESD protection device according to any one of the preceding claims. 20. The P ⁺ layer and the first and second N ⁺ layers are formed simultaneously with the P ⁺ layer and the N ⁺ layer of a CMOS transistor constituting the internal circuit. The ESD protection device according to any one of the preceding claims. 21. The N ⁺ layer and the first and second P ⁺ layers are formed simultaneously with the N ⁺ layer and the P ⁺ layer of a CMOS transistor constituting the internal circuit. The ESD protection device according to any one of the preceding claims. 22. The ESD protection device according to claim 18, wherein the second N ^- type well is formed at the same time as the N ^- type well of the CMOS transistor forming the internal circuit. 23. The ESD protection device according to claim 19, wherein the second P ^- type well is formed at the same time as the P ^- type well of the CMOS transistor forming the internal circuit. 24. The ESD protection according to claim 18, wherein the insulator is a dummy gate electrode formed simultaneously with a gate electrode and a gate insulating film of a CMOS transistor constituting the internal circuit, or a simple insulating film. apparatus. 25. The ESD protection device according to claim 24, wherein the dummy gate electrode or the insulating film is formed in a ring shape with respect to the surface of the silicon substrate. 26. The diode is a P-type silicon substrate.
N formed on the surface ⁻Mold well and this N⁻Mold well table
P formed on the plane apart from each other⁺Layer and N⁺Layers and this
Our P⁺Layer and N⁺P-type silicon substrate surface between layers
The ESD protection device according to claim 1, 2, 3, 5, 7, 7, or 9, wherein the ESD protection device comprises:
Place. 27. The diode according to claim 27, wherein the diode is an N-type silicon substrate.
P formed on the surface ⁻Mold well and this P⁻Mold well table
P formed on the plane apart from each other⁺Layer and N⁺Layers and this
Our P⁺Layer and N⁺P-type silicon substrate surface between layers
The ESD protection device according to claim 1, 2, 4, 6, 8, or 10, wherein the device comprises an insulator formed therein.
Place. 28. The diode is a P-type silicon substrate.
N formed on the surface ⁻Mold well and this N⁻Mold well table
P formed on the surface⁻Mold well and this P⁻Mold well surface
Formed at a distance from each other⁺Layer and N⁺Layers and these
P⁺Layer and N ⁺On the P-type silicon substrate surface between the layers
The P⁺Layer and N⁺To prevent electrical connection to the layer.
The P-type silicon substrate and the P-type silicon substrate.⁻Separation from mold well
The ESD protection device according to claim 1, 2, 3, 5, 7, or 9, which is insulated by an edge.
Place. 29. The diode is an N-type silicon substrate.
P formed on the surface ⁻Mold well and this P⁻Mold well table
N formed on the surface⁻Mold well and this N⁻Mold well surface
Formed at a distance from each other⁺Layer and N⁺Layers and these
P⁺Layer and N ⁺On the surface of the N-type silicon substrate between
The P⁺Layer and N⁺To prevent electrical connection to the layer.
The N-type silicon substrate and the N-type silicon substrate.⁻Separation from mold well
The ESD protection device according to claim 1, 2, 4, 6, 8, or 10, which is insulated with an edge.
Place. 30. The diode, P formed on a silicon substrate surface ^- -type well, the P ^- and N ⁺ layer and the P ⁺ layer formed apart from each other in the mold well surface, and these N ⁺ layer wherein P between P ⁺ layer ^- consists of an on type well connected to the ground terminal along with the provided via an insulating film a dummy gate electrode, according to claim 4, 5, 6, 7 11. The ESD protection device according to claim 9, 8, 9, or 10. 31. An N ^- type well formed on the surface of a silicon substrate, an N ⁺ layer and a P ⁺ layer formed apart from each other on the surface of the N ^- type well, and the N ⁺ layer. 8. A dummy gate electrode provided between the P ⁺ layer and the N ⁻ -type well via an insulating film and connected to a ground terminal. 11. The ESD protection device according to claim 9, 8, 9, or 10. 32. The method of claim 1, 3, 4, 5, 6, 11, 1.
The ESD protection device according to 2, 13, 14 or 15 is manufactured.
A method for forming the internal circuit on a P-type silicon substrate
MOS transistor N⁻Mold well and the vertical
Core that is connected to the collector of the polar transistor
N for Lecter Connection⁻First step to form mold well simultaneously
With respect to the P-type silicon substrate, the vertical bipolar transistor
Collector N to be the collector of transistor⁻Mold well, and
And N of the diode⁻Second forming the mold well simultaneously
And a collector N of the vertical bipolar transistor.⁻Mold
The base P in the ⁻Mold layer and N of the diode
⁻P serving as anode in mold well⁻Forming mold layers simultaneously
A third step, P of the CMOS transistor⁻N in mold well⁺Mold layer,
N for collector connection of the vertical bipolar transistor⁻
N in mold well⁺Mold layer, the vertical bipolar transistor
P⁻N as an emitter in the mold layer⁺Mold layer, and the die
P⁻N serving as cathode for mold layer⁺Form layer simultaneously
A fourth step of performing⁻P in mold well⁺Mold layer,
P of the vertical bipolar transistor⁻P for mold layer⁺Type
Layer and P of the diode⁻P for mold layer⁺Mold layer at the same time
A method of manufacturing an ESD protection device, comprising: forming a fifth step. 33. The method according to claim 2, 7, 8, 9 or 10.
What is claimed is: 1. A method for manufacturing an ESD protection device, comprising:
MOS transistor N⁻Mold well and the vertical
Core that is connected to the collector of the polar transistor
N for Lecter Connection⁻First step to form mold well simultaneously
With respect to the P-type silicon substrate, the vertical bipolar transistor
Collector N to be the collector of transistor⁻Mold well, and
And N of the diode⁻Second forming the mold well simultaneously
And a collector N of the vertical bipolar transistor.⁻Mold
The base P in the ⁻Mold layer and N of the diode
⁻P serving as cathode in mold well⁻Forming mold layers simultaneously
A third step, P of the CMOS transistor⁻N in mold well⁺Mold layer,
N for collector connection of the vertical bipolar transistor⁻
N in mold well⁺Mold layer, the vertical bipolar transistor
P⁻N as an emitter in the mold layer⁺Mold layer, and the die
P⁻N serving as an anode in the mold layer⁺Form layer simultaneously
A fourth step of performing⁻P in mold well⁺Mold layer,
P of the vertical bipolar transistor⁻P for mold layer⁺Type
Layer and P of the diode⁻P for mold layer⁺Mold layer at the same time
A method of manufacturing an ESD protection device, comprising: forming a fifth step. N type well and the diode ^{- -} 34. Collector N of the vertical bipolar transistor in a region where the mold well is formed in the second step to form simultaneously the dummy gate electrode and the gate electrode of the CMOS transistor A step of forming the dummy gate electrode with the vertical bipolar transistor and the diode of the vertical bipolar transistor formed in the fourth step.
And ⁺ -type layer, wherein those in which the P ⁺ -type layer of the fifth said vertical bipolar transistor formed by the step and the diode prevented from being connected in a later step, according to claim 32 or 33 ESD according Manufacturing method of protection device. 35. The N ⁺ -type layer of the vertical bipolar transistor and the diode formed in the fourth step, and the P ⁺ -type layer of the vertical bipolar transistor and the diode formed in the fifth step. 34. The method for manufacturing an ESD protection device according to claim 32, further comprising a step of forming an insulating film for preventing connection in a later step. 36. The method for manufacturing an ESD protection device according to claim 32, wherein the conductive type P is replaced with N, and the conductive type N is replaced with P.