JPH0389561A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a parasitic capacitance based on wirings by composing an npn bipolar transistor of a p-type base layer and an n-type emitter layer formed by doping an n-type epitaxial layer with impurity near a predetermined region and an n-type collector by an n-type epitaxial layer itself. CONSTITUTION:After an opening of an SiN film is oxidized, a mask 17 is formed on an emitter region, and boron is ion implanted to form an outer base 18. Further, boron is implanted to form an intrinsic base 19. thereafter, an SiO2 film 20 is deposited by a CVD, and heated to form a profile. Then, after the film 20 and the SiN film on the surface are removed, polysilicon 21 is deposited, and arsenic is ion implanted. Thereafter, an SiO2 film is deposited by a CVD, and heated to form an emitter 22. An n-type epitaxial layer remaining at the lower side of the base 19 becomes a collectors 23. The SiO2 film and an unnecessary polysilicon are dry etched to be removed, and an SiO2 film is again deposited by a CVD.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which a light receiving element and an electronic element are monolithically formed on the same substrate.

[Conventional technology]

2. Description of the Related Art Optical receiving circuits are conventionally known in which a PIN photodiode is used as a light receiving element and an npn bipolar transistor is used as an electronic element for the signal processing circuit. However, in the conventional circuit, the PIN photodiode and the npn bipolar transistor are formed on separate chips, and are simply connected to each other by wiring on a hybrid IC substrate.

[Problem to be solved by the invention]

However, conventional configurations using hybrid ICs have problems such as large parasitic capacitance due to wiring and difficulty in automating the assembly process, so a monolithic configuration has been desired.

An object of the present invention is to solve these problems.

[Means to solve the problem]

In order to solve the above problems, a semiconductor device of the present invention is a semiconductor device in which a lightly doped p-type epitaxial layer is formed on a highly doped p-type semiconductor substrate, and an n-type epitaxial layer is further formed thereon. Since the n-type buried layer is formed in the surface layer of a predetermined region of the low concentration p-type epitaxial layer, the high concentration p-type semiconductor substrate can be made into a P layer, one low concentration epitaxial layer and an n-type buried layer. P with N layers
The IN photodiode is configured with a p-type base layer and an n12 epitaxial layer formed by doping impurities into the n-type epitaxial layer near the PIN photodiode region, and an n12 layer formed by the n-type epitaxial layer itself.
The collector layer constitutes an npn bipolar transistor.

[Effect]

A PIN photodiode and an npn bipolar transistor can coexist on the same substrate by forming an epitaxial layer with a two-layer structure consisting of a lightly doped p-type epitaxial layer and an n-type epitaxial layer on the highly doped p-type semiconductor substrate.

〔Example〕

FIG. 1 is a partially sectional perspective view showing an embodiment of the semiconductor device of the present invention, and FIG. 2 is a process sectional view showing the manufacturing process thereof.

First, the manufacturing method will be explained with reference to FIG.

A low-concentration p-type epitaxial layer 2 with an impurity concentration of about 210-1014/cIII3 is formed to a thickness of 30-50 μm on a high-concentration p-type semiconductor substrate 1 with an impurity concentration of about 10-1021/cIn3.

Although not shown, an SiO2 film for preventing autodoping is formed on the back surface of the semiconductor substrate 1 (see FIG. 2(A)). Next, a SiO2 film 3 is applied to the surface.
, and its Si
o 2 Process the film 3. Using the SiOZ film 3 as a mask, boron ions are implanted from above to form a p-well buried layer 4 for an npn transistor. This buried layer 4
The impurity concentration is about 1015 to 1016/cl13 (see FIG. 2(B)). As shown by the position of the p-well buried layer 4, approximately the right half of the figure is the npn transistor formation region, and the left half is the PIN photodiode formation region. Then, the SiO2 film 3 on the surface is processed again using photolithography or the like, and antimony (Sb) is thermally diffused using the processed SiO2 film as a mask. This results in an n-type buried layer 5 for the npn transistor and an n-type buried layer 6 for the PIN photodiode.
is formed.

The impurity concentration of the n-type buried layer 5.6 is 1019 to 1020/
cs3 (see Figure 2 (C)). FIG. 3 shows the profiles of the buried layers 4 to 6 described above, and curve A
is the profile of antimony and curve B is the profile of boron. After that, the SiO2 film 3 on the surface
is removed to form an n-type epitaxial layer 7 having a thickness of 2 μm±0.2 μm.

The impurity concentration is about 1015 to 1016/cIII3 (see FIG. 2(D)). This completes the buried diffusion and epitaxial growth steps.

Next, the separation process will be explained.

A SiO2 film 8 and a SiN film 9 are formed over the entire surface of the n-type epitaxial layer 7. Then, a resist 10 is applied thereon, and the SiO2 film 8 and 5iNIli 9 in desired areas are removed by etching using photolithography. Thereafter, using the SiO2 film 8 and the SiN film 9 as masks, the n-type epitaxial layer 7 is etched from the surface.
Wet etching to a depth of 1 μm, then 0.7
Shallow grooves are formed by anisotropic dry etching to a depth of .mu.m (see FIG. 2(E)). Here, the desired regions include an isolation region of an npn) transistor, an isolation region between a p-type base layer and a collector all that will be provided in the future inside the npn transistor, a light receiving region of a PIN photodiode, and the like.

Next, a resist 11 is applied, and only the upper part of the groove provided in the isolation region is removed by photolithography. Then, anisotropic dry etching of 3.0 .mu.m is performed using the resist 11 as a mask to deepen the shallow trenches located in the isolation region.

Thereafter, boron ions are implanted while leaving the resist 11 to form a pl stopper layer at the bottom of each deep groove (see FIG. 2(F)). Next, resist 10
, 11 are removed, resist is applied again and boron ions are implanted using photolithography to form the p-tub 12. The p-tubs 12 are formed to surround the PIN photodiode region and the npn transistor region, respectively. Then, the resist is removed, and an SIO2 film and a SiN film are formed on the inner surface of the valley.

Then, by anisotropic etching of SiN, the SiN film at the bottom is removed while leaving the SiN film on the side walls of the valley groove (second step).
(See figure (G)). Subsequently, thermal oxidation is performed in an atmosphere of 6 atm and 1050°C. As a result, the portions not covered with the SiN film are oxidized.

The thickness of the oxide film obtained by this oxidation is about 1.5 μm, and almost completely fills the shallow trench. after that,
By depositing polysilicon 13 over the entire surface, even deep trenches are filled. Then, a SiO2 film and 5iNJli are formed on the surface of the polysilicon 13, and patterned by dry etching so that it remains only in the upper part of the deep groove (see FIG. 2(H)). Next, polysilicon 13 is etched. This leaves polysilicon 13 only inside the deep trench. After removing the SiN film remaining on the surface by dry etching, oxidation is performed to flatten the surface (see FIG. 2 (1)).

Next, an SiO2 film 26 and a SiN film 27 are formed on the surface. Desired regions of these films are patterned using photolithography technology.

By diffusing phosphorus using the remaining SiO2 film 26 and SiN film 27 as a mask, an n layer 15 that will become the collector all of the npn transistor and an n layer 16 that will become the electrode extraction layer of the PIN photodiode are formed (second (See figure (J)).

In addition, in FIGS. 2(J) to 2(M), polysilicon and 5iNll in the deep trenches are omitted for simplicity. Subsequently, after oxidizing the opening of the SiN film, a mask 17 is formed in the emitter region, and boron ions are implanted to form an external base 18 (see FIG. 2(K)). Furthermore, the intrinsic base 19 is formed by implanting boron ions using photolithography technology. After that, the SiO2 film 20
is deposited by chemical vapor deposition (CVD) and heated to form a profile (see FIG. 2(L)).

Next, after removing the 0SiN film on the SiO□ film 20 on the surface by dry etching, polysilicon 21 is deposited. Then, arsenic ions are implanted (see Figure 2 (M)).
. Thereafter, a SiO2 film is deposited by CVD and heated to form the emitter 22.

Note that the n-type epitaxial layer left below the base 19 becomes the collector 23. Then, the SiO2 film and unnecessary polysilicon are removed by dry etching, and the SiO□ film is deposited again by CVD (see Figure 2 (N)).
.

The semiconductor device shown in FIG. 1 is one in which necessary electrodes are formed after the above steps, and a PIN photodiode 31 and an NPNH transistor 32 are monolithically formed on the same substrate. The P1N photodiode 31 is a substrate PI in which the high concentration p-type semiconductor substrate 1 is a P layer, the low concentration p-type epitaxial layer 2 is one layer, and the n-type buried layer 6 is an N layer.
N photodiode. A cathode electrode 33 is provided on the n-type buried layer 6 via an electrode extraction layer 16, and an anode electrode (not shown) is provided on the back surface of the substrate 1. When light is incident with a reverse bias applied between the electrodes, carriers are generated in the depletion region of the lightly doped p-type epitaxial layer 2, and these carriers move due to the electric field in the depletion region and become a photocurrent. Also, electrode 3 on the p4″ tab layer
4 functions as an anode electrode of the PIN photodiode together with the electrode on the back surface. By adding this electrode 34 as an anode electrode, parasitic resistance can be reduced more than when only the back surface electrode is used as the anode electrode.

npn) transistor 32 is provided with an emitter electrode 35, a base electrode 36, and a collector electrode 37 as shown in the figure. The p-type buried layer 4 is provided to prevent punch-through with surrounding elements. Further, a stopper layer 29 is provided around the bottom of the separation groove to more effectively prevent punch-through.

〔Effect of the invention〕

As explained above, according to the semiconductor device of the present invention, P
Since the IN photodiode and the npn bipolar transistor are monolithically formed on the same substrate,
This has the effect of reducing parasitic capacitance based on wiring. Therefore, when used in optical communication receiving circuits, etc., it is possible to operate at higher speeds than conventional circuits. Furthermore, there is no need for an assembly process like that required for hybrid ICs.

[Brief explanation of drawings]

FIG. 1 is a partial cross-sectional perspective view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a process cross-sectional view showing a manufacturing method thereof, and FIG.
The figure is a graph showing the profile of the buried layer. 1...High concentration p-type semiconductor substrate, 2...Low concentration n-type epitaxial layer, 4...p-type buried layer, 5.6...n
Type buried layer, 7... N-type epitaxial layer, 12...
p+ tab, 18...external base, one...intrinsic base, 22...emitter, 23...collector, 31...
...PIN photodiode, 32...npn) transistor.

Claims (1)

[Claims] A semiconductor device comprising a lightly doped p-type epitaxial layer formed on a highly doped p-type semiconductor substrate and an n-type epitaxial layer further formed thereon, the surface layer portion of a predetermined region of the lightly doped p-type epitaxial layer. An n-type buried layer is formed in the PIN photodiode, in which the highly doped p-type semiconductor substrate is a P layer, the lightly doped epitaxial layer is an I layer, and the n-type buried layer is an N layer. a p-type base layer and an n-type epitaxial layer formed by doping impurities into the n-type epitaxial layer near the predetermined region;
1. A semiconductor device characterized in that an npn bipolar transistor is constituted by an n-type emitter layer and an n-type collector layer formed by the n-type epitaxial layer itself.