JPH0388596A - Extended chrominance signal interpolating circuit - Google Patents

Abstract

PURPOSE:To smooth the change of a chrominance signal and to improve picture quality by providing a selecting circuit to select and output output data from a one-sampling period delay circuit and interpolation data from an interpolation data forming circuit with the period of the 1/interger number for one sampling period of the extended chrominance signal. CONSTITUTION:Output data DA from a one-sampling period delay circuit 1 and three interpolation data 2DA/4+DB/4, DA/2+DB/2 and DA/4+3DB/4 from an interpolation data forming circuit 10 are applied to a selecting circuit 3 as selecting inputs. A selection control signal is applied from a timing control circuit 2 to this selecting circuit 3 and based on this selection control signal, the selecting circuit 3 selects the data in the order of the data DA, 3DA/4+DB/4, DA/2+DB/2 and DA/4+3DB/4. Accordingly, the data passing through the selecting circuit 3 are gradually changed from data DA to data DB with the 1/4 sampling period. The selecting circuit 3 executes selecting operation based on the 4 times frequency 11.34MHz of a sampling frequency 2.835MHz.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an expanded color signal interpolation circuit, for example, a so-called MUSE (multiple 5ub-Nyq
The present invention can be applied to a receiving device that receives a band-compressed television signal such as a television signal of a UIST sampling gencoding system.

[Prior art] The baseband bandwidth of high-definition television signals is 30M
Hz, and high-definition television signals cannot be transmitted using one channel of current satellite broadcasting, and the band must be compressed to about 8 MHz for transmission. The MUSE system has been proposed as a system for transmitting a high-definition television signal after compressing its band.

As a device for receiving a television signal encoded according to the MUSE method, there is, of course, a receiving device that can reproduce up to a high-definition television signal, but in addition to this, the received signal can be received by an existing television method (for example,
There is a receiving device that converts television signals into NTSC television signals. The latter is proposed to achieve compatibility with existing current television systems.

The latter receiving device receives a MUSE television signal with 1125 scanning lines and an aspect ratio of 16:9, and receives the MUSE television signal with 5 scanning lines.
Processing is performed to convert the signal into a television signal with 25 lines and an aspect ratio of 4:3. Conventionally, scanning lines are thinned out and
Conversion was performed by extracting a portion with an aspect ratio of 4:3 from the thinned signal. Also, if the received signal is MU
Since it is an SE television signal, after such conversion (or before conversion), line-sequential decoding processing is performed.In other words, the color signal inserted in the horizontal blanking period is extracted and the color signal is divided into color difference signals. While doing so, the time axis is 4
It had doubled in size.

[Problem to be solved by the invention] In the case of a receiving device that reproduces even high-definition television signals,
Since all decoding processing, which is the reverse processing of encoding, is performed, the image quality can be obtained from the beginning as intended.

That is, since it is encoded so that a predetermined image quality can be ensured, decoding it can ensure a predetermined image quality.

On the other hand, in the receiving device that converts into a television signal of the current system, the image quality deteriorates because processing other than reverse processing of encoding processing is also performed. Since the scanning lines are thinned out, it is unavoidable that the vertical resolution will deteriorate. However, because the sampling frequency was lowered and the scanning lines were thinned out, and the color signal was expanded by a factor of 4, it became noticeable that the diagonal outline of the color signal became stepped, that is, the linearity of the color signal was lost. This caused the image quality to deteriorate.

The present invention has been made in consideration of the above points, and it is an object of the present invention to provide an expanded color signal interpolation circuit that can suppress image quality deterioration caused by color signal expansion processing.

[Means for Solving the Problem] In order to solve the problem, in the present invention, the expanded color signal is sampled at the next stage of the color signal expansion circuit that expands the color signal whose time axis is compressed. an interpolated data forming circuit that forms at least t pieces of interpolated data obtained by weighted addition of first and second data obtained before and after the l sampling period delay circuit; , a selection circuit that selects and outputs the output data from the one sampling period delay circuit and the interpolated data from the interpolation data forming circuit at a period l that is an integer of one sampling period of the expanded color signal. A signal interpolation circuit was provided.

[Function] When a color signal is expanded on the time axis, this expansion lengthens the time it takes to take the same data value. Therefore, we installed an expanded color signal interpolation circuit at the next stage of the color signal expansion circuit to perform interpolation processing, shorten the time required to obtain the same data value, smooth the change, and improve the image quality from the color signal side. I made it.

The expanded color signal interpolation circuit used includes a one-sampling period delay circuit, an interpolation data formation circuit, and a selection circuit.

The one-sampling-period delay circuit extracts first and second data that differ by one sampling period of the expanded color signal, and the interpolation data forming circuit weights and adds these first and second data. to form at least one piece of interpolated data. Then, the selection circuit appropriately selects and outputs the output data from the one sampling period delay circuit and the interpolated data from the interpolation data forming circuit at a period that is an integer fraction of one sampling period of the expanded color signal. , and sends the interpolated color signal to the next stage.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an expanded color signal interpolation circuit to which an expanded color signal is given after being subjected to line-sequential decoding by a color signal expansion circuit (not shown).

In the case of this embodiment, it is applied to a receiving device that converts a MUSE television signal into a current system television signal, and the sampling frequency of the time-axis expanded color signal is, for example, 2.835 MHz. . Also,
Since the color signal given to the expanded color signal interpolation circuit shown in Fig. 1 has been subjected to line-sequential decoding processing,
More precisely, it is one of the color difference signals R-Y and B-Y.

In the drawing, a color signal (digital data) which has been time-extended in the same way as in the conventional apparatus is applied to a one-sampling period delay circuit 1 having a D-type flip-flop circuit configuration, for example. This l sampling period delay circuit 1 includes:
A clock signal having a frequency equal to the sampling frequency of the input color signal is supplied from the timing control circuit 2, and the sampling period delay circuit 1 performs a delay operation in synchronization with this.

Thus, from before and after the sampling period delay circuit 1,
Two delay circuits that differ by the F sampling period 1.
Both the data DA via the l sampling period delay circuit 1 and the previous data DB via the l sampling period delay circuit 1 are interpolated data forming circuit B.
given to 10.

In this embodiment, the interpolation data forming circuit IO forms three pieces of interpolation data.

Data 1) A is 3 through 3/4 times FlifI construction
It is multiplied by /4 and given to the adder circuit ↓2, and the data DB is 1
It is multiplied by 1/4 via the /4 multiplier circuit 13 and then outputted to the adder circuit 2.
given to. The adder circuit 12 adds these to form the upper interpolated data 3DA/4+DB/4 which is close to the data DA. Further, the data DA is multiplied by ↓/2 via the 1/2 multiplier circuit ↑4 and given to the adder circuit 15, and the data DA is
is multiplied by 1-72 via the 1/2m multiplier circuit (6) and given to the addition circuit Bl 5.The addition circuit ↑5 adds these and produces the second interpolated data DA/, which is the average of the data DA and DB.
2+DB/2 is formed. Furthermore, data DA is 1/4
The data DB is multiplied by 1/4 via the multiplication circuit B17 and given to the adder circuit ↑8, and the data DB is multiplied by 3/4 via the 3/4 multiplication circuit 19.
It is multiplied by 4 and given to addition circuit 818. Adding circuit ↑8 adds these and obtains third interpolated data D that is close to data DB.
Form A/4+3DB/4.

1 sampling period delay time H @ Output data D from 1
A, and three interpolated data 3DA/4+DB/4, DA/2+DB/2, DA from interpolated data forming circuit IO
/4+3DB/4 is given to the selection circuit 3 as a selection input. This selection circuit 3 is given a selection control signal from the timing control circuit 82, and the selection circuit Fi113 selects the data DA, 3DA/
4+DB/4, DA/2+DB/2, DA/4+3DB
Select data in the order of /4. Therefore, the data passing through the selection circuit 3 gradually changes from data DA to data DB at a sampling period of ↑/4. In addition,
The selection circuit 3 has the above-mentioned sampling frequency of 2.835.
The selection operation is based on a frequency of 11°34 MHz, which is four times MHz.

The data passing through this selection circuit 3 is given an 11.34 MHz clock signal from the timing control circuit 2.
For example, it is applied to a latch circuit B4 having a D-type flip-flop circuit configuration, is latched, and is output.

Note that the latch circuit 4 is provided for phase synchronization with the luminance signal and for making the clock rates the same.

Therefore, according to the embodiment described above, it is possible to output a color signal with smooth changes even after time axis expansion, and the image quality from the color signal side can be improved compared to the conventional one. In this way, the clock rate 1 ~ changes by going through the expanded color signal interpolation circuit, but in the case of a MUSE television signal receiving device, the clock rate conversion is required after the color signal expansion process, so this is not necessary. Clock rate changes are not an issue.

In addition, in the above-mentioned embodiment, an application is shown to a receiving device that converts a MUSE television signal to a current system television signal, but the line-sequential 0 decoding configuration of a receiving device that reproduces a high-definition television signal is also applicable. It can also be applied to
The present invention is not limited to a receiving device for compressed band television signals such as the MUSE method, but can also be applied to various devices having a color signal expansion processing configuration.

Further, the number of interpolated data is not limited to three types as described above.

[Effects of the Invention] As described above, according to the present invention, the color signal whose time axis is expanded and the time for taking the same data value is expanded is outputted via the expanded color signal interpolation circuit. Changes in color signals are smoothed out, making it possible to improve image quality compared to conventional methods.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an expanded color signal interpolation circuit according to the present invention. DESCRIPTION OF SYMBOLS 1...1 sampling period delay circuit, 2...timing control circuit, 3...latch circuit,]0...interpolation data formation circuit, 11.19...3/4 multiplication circuit, 12
, 1 t5. 18...addition circuit, ■3. 17...l/4 multiplier circuit, 14. 16... 1/2 multiplier circuit.

Claims (1)

[Scope of Claims] A one-sampling period delay circuit that is provided at the next stage of a color signal expansion circuit that expands a color signal whose time axis is compressed, and that delays the expanded color signal by one sampling period. , an interpolation data forming circuit that forms at least one piece of interpolation data obtained by weighted addition of first and second data of the color signal obtained before and after the one sampling period delay circuit; and from the one sampling period delay circuit. The output data of
and a selection circuit that selects and outputs the interpolated data from the interpolated data forming circuit at a period that is an integer fraction of one sampling period of the expanded color signal. .