JPH0387044A - Compound semiconductor device - Google Patents

Abstract

PURPOSE:To contrive an increase in the integration of a device by a method wherein carriers to leak from a compound semiconductor crystal active layer are completely interrupted by an interelement isolation groove and a dielectric layer or a depletion layer in the groove and the leak of the carriers at a deep place in the active layer is inhibited by the existence of a heterointerface. CONSTITUTION:An AlxGa1-xAs (the x is 0.3 to 0.4) layer 22 and a GaAs layer 23 are deposited on a GaAs substrate 21 in the order of the layers 22 and 23 by a organometallic method and a heterointerface 24 is formed. A CVD-SiO2 film 25 is superposed, an RIE is performed using CF4+CHF3 and an opening 25A is formed. An RIE is performed using CCl2F2+He and an isolation groove 26 is selectively formed in the layer 22. A mask 25 is removed and ohmic source and drain electrodes 27 and 28 and a Schottky gate electrode 29 are formed to complete a compound semiconductor device. A polycrystalline GaAs insulator layer can be selectively grown in the groove 26 utilizing the mask 25A.

Description

[Detailed Description of the Invention] [Summary] Regarding a compound semiconductor device with an improved structure for performing isolation between elements or isolation between electrodes, the present invention relates to a compound semiconductor device that ensures isolation between elements and isolation between electrodes in a compound semiconductor device by extremely simple means. A compound semiconductor crystal layer that is interposed between a compound semiconductor crystal substrate and a compound semiconductor crystal active layer and has a composition that creates a hetero interface with the compound semiconductor crystal active layer, and a surface The device is configured to include an inter-element isolation trench reaching at least the compound semiconductor crystal active layer, or an inter-element isolation trench in which a dielectric material is embedded.

[Industrial application field]

The present invention relates to a compound semiconductor device having an improved structure for isolation between elements or isolation between electrodes.

In order to achieve high integration of semiconductor devices, it is an important factor to ensure isolation between elements or isolation between element electrodes.

[Conventional technology]

FIG. 15 shows an explanatory diagram of main parts for explaining a conventional compound semiconductor device.

In the figure, 1 is a semiconductor crystal substrate, 2 is a source electrode, and 3 is a semiconductor crystal substrate.
is a drain electrode, 4 is a gate electrode, 5 is an electrode of an adjacent element (an electrode that becomes a side gate), 6 is a power source for applying a drain voltage, and 7 is a power source for applying a voltage to an adjacent element (an electrode that becomes a side gate). Q is a field effect transistor, (4) is a drain voltage, (4) is a drain current, Vsg is a side-gate voltage, and e- is a leaking electron.

In general, compound semiconductor crystals, such as GaAs crystals, have a higher bulk resistivity than silicon crystals, and therefore,
Electrical insulation between elements and electrodes is relatively easy, but as semiconductor devices become more highly integrated, for example, electrons e-
flows in and changes the transistor characteristics.

FIG. 16 shows the side gate voltage v1. and transistor Q
It is a diagram showing the relationship between drain current ■4 flowing in
The horizontal axis represents the side gate voltage V sv, and the vertical axis represents the drain current ■d (arbitrary unit).

As seen in characteristic line A in the figure, the side gate voltage V
When the drain current I4 becomes less than the value v0 of 3g, the drain current I4 rapidly decreases.

In order to solve these problems, various methods have been adopted for isolation between elements and between element electrodes. Bulk resistance is increased by inducing defects.

FIG. 17 shows a main part explanatory diagram illustrating a semiconductor device in which isolation regions are formed between elements, and the same symbols as those used in FIG. 15 indicate the same parts or have the same meanings. .

In the figure, numeral 8 indicates a separation region formed by implanting oxygen ions or hydrogen ions.

FIG. 18 is an explanatory view of the main parts illustrating a semiconductor device in which a voltage is applied by forming an impurity region of a conductivity type opposite to that of a semiconductor crystal substrate, and is used in FIGS. 15 and 17. Symbols and the same symbol indicate the same part or have the same meaning.

In the figure, 9 is an impurity region formed between the transistor Q and the electrode 5 of an adjacent element, 10 is an electrode that contacts the impurity region 9, and 11 is a separation voltage application for applying voltage to the impurity region 9. , and ■i indicate the negative separation voltage, respectively. Note that the impurity region 9 is located on the semiconductor crystal substrate 1.
Needless to say, if it is n-type, it should be made p-type.

In this semiconductor device, a negative isolation voltage V is applied to impurity region 9, which is, for example, p-type, and the insulation between elements is enhanced by utilizing the potential barrier of the pn junction.

[Problem to be solved by the invention]

In contrast to the semiconductor device described with reference to FIG. 15, the semiconductor devices shown in FIGS. 17 and 18 are ones in which measures have been taken, especially regarding isolation between elements. Although these measures have some effect, As seen in characteristic line B (semiconductor device explained in FIG. 17) and characteristic line C (semiconductor device explained in FIG. 18) in FIG. 16, the voltage V at which the side gate effect occurs is slightly increased. Although it is effective, it cannot be said to be sufficient because it cannot suppress the leaking electrons e-.

In addition, air separation is also carried out by etching a part of the wafer, but compound semiconductor crystals, unlike silicon crystals, tend to lose their crystal properties, so it is not recommended to perform too deep etching. Shallow etching is insufficient in suppressing leaking electrons e-.

The present invention attempts to make it possible to reliably perform isolation between elements and isolation between electrodes in a compound semiconductor device using extremely simple means.

[Means to solve the problem]

FIG. 1 shows an explanatory diagram of the main parts of a compound semiconductor device for explaining the present invention in detail, and the same symbols as those used in FIGS. 15, 17, and 18 indicate the same parts. or have the same meaning.

In the figure, 21 is a semiconductor crystal substrate, 22 is a first semi-insulating compound semiconductor crystal layer, 23 is a second semi-insulating compound semiconductor crystal layer, 24 is a hetero interface, and 26 is a hetero interface 14 from the surface. The groove reaching 27° is the source electrode, 28. is a drain electrode, 29. indicate gate electrodes, respectively.

FIG. 2 shows an energy band diagram of the semiconductor device shown in FIG. 1, and symbols used in FIG. 1 indicate the same parts or have the same meanings.

In the figure, E is the bottom of the conduction band, Ev is the top of the valence band,
El is the energy band gap of the first semi-insulating compound semiconductor crystal layer 22, E gZ is the energy band gap of the second semi-insulating compound semiconductor crystal layer 23, Δ
Ec indicates the discontinuous value of the conduction band at the hetero interface. Note that it is easy to make such an energy band structure appear; for example, if AffiGaAs is used as the first semi-insulating compound semiconductor layer 22 and GaAs is used as the second semi-insulating compound semiconductor layer 23, Just use it.

In the semiconductor device shown in FIG. 1, as shown in FIG. 2, the bottom EC of the conduction band at the hetero interface between the first compound semiconductor crystal layer 22 and the second compound semiconductor crystal layer 23 is Since it is discontinuous, the potential barrier at the hetero interface 24 acts on the electrons in the second compound semiconductor crystal layer 23, so that the electrons cross it and enter the first compound semiconductor crystal layer 22. It doesn't flow in.

For this reason, in the compound semiconductor device of the present invention, there is a gap between the compound semiconductor crystal substrate (for example, the GaAs crystal substrate 21) and the compound semiconductor crystal active layer (for example, the semi-insulating GaAs crystal layer 23). A compound semiconductor crystal layer (for example, semi-insulating AfGaAs crystal layer 22) having a composition that is interposed and forms a hetero interface (for example, hetero interface 24) with the compound semiconductor crystal active layer, and at least the compound semiconductor crystal layer from the surface. It is provided with an inter-element isolation trench (for example, the inter-element isolation trench 26) that reaches into the crystal active layer, or an inter-element isolation trench in which a dielectric material is embedded.

[Effect]

By adopting the above method, carriers leaking from the compound semiconductor crystal active layer are completely blocked by the element isolation trench, the dielectric material in the element isolation trench, or the depletion layer, and carriers leaking from deep areas are completely blocked. The presence of the hetero-interface suppresses the carriers that would otherwise occur, making it possible to greatly contribute to higher integration of compound semiconductor devices.

〔Example〕

3 to 6 are cross-sectional side views of the main parts of the compound semiconductor device at key points in the process for explaining the case of manufacturing the first embodiment of the present invention. I will explain while referring to it.

See Figure 3 (311 metalorganic vapor deposition).
r phase epitaxialme th
By applying the od:MOVPE) method, GaA
A semi-insulating AfGaAs crystal layer 22 and a semi-insulating GaAs crystal layer 23 are grown on the s-crystal substrate 21 at around 1. Note that 24 indicates a hetero interface.

Examples of main data regarding each crystal layer are as follows.

■ Aj! X value for xGa, -XAs crystal layer 22:
0.3 to 0.4 Thickness: approx. 1000 (in) ■ Thickness of the GaAs crystal layer 23: 2000 to 6000 (in) See Figure 4 (4)-1 Chemical vapor deposition
By applying the chemical vapor deposition (CVD) method, a silicon dioxide (silicone dioxide
A SiOz) film 25 is formed.

(4)-2 Resist process in normal photolithography technology and reactive ion etching using CF4 + CHF3 as etching gas.
By applying a ton etching (RIE) method, the silicon dioxide film 25 is selectively etched to form an opening 25A in a portion where an element isolation region is to be formed.

Refer to FIG. 5 (5)-1 By applying the RIE method, the silicon dioxide film 25
Using the GaAs crystal layer 23 as a mask, the AfGa
Selective etching is performed to reach the As crystal layer 22 to form isolation grooves 26 between elements.

Furthermore, this etching is Aj! It automatically stops at the surface of the GaAs crystal layer 22.

Examples of conditions for this etching are as follows.

Etching gas: CCf, F! :He=2:5 Pressure crab~10" (Torr) Output crab 200 (W) Wafer temperature: 60 ("C) See Figure 6 (6)-1 Remove the silicon dioxide film 25 used as a mask Then, by applying conventional lift-off techniques, the ohmic contact source electrode 27. ．． 27□, drain electrode 28. ．． Form 2L.

(6)-2 Apply a conventional technique to form a Schottky contact gate electrode 291.29□.

In the semiconductor device manufactured in this way, not only electrons leak from the surface of the GaAs crystal layer 23, but also electrons do not leak from deep areas because of the presence of the hetero interface 24.

FIG. 7 shows the side gate voltage of the semiconductor device manufactured as described above. It is a diagram showing the relationship between
The vertical axis represents the drain current a (arbitrary unit).

In the figure, D indicates a characteristic line related to an embodiment of the present invention, and E indicates a characteristic line related to a conventional example shown for reference.

It can be seen that according to the present invention, no change in characteristics appears in the practical operating range of the semiconductor device.

FIG. 8 shows a cutaway side view of essential parts for explaining the second embodiment of the present invention, and the same symbols as those used in FIGS. 3 to 6 indicate the same parts or have the same meanings. shall have.

In this embodiment, the inter-element isolation groove 30 is located at the hetero interface 2.
4 and is formed to penetrate into the AlGaAs crystal layer 22.

It is easy to form such an inter-element isolation groove 30, and the GaAs crystal layer 23 and the Al1GaAs crystal layer 2
As a condition for etching 2, etching gas: C
l1t (20 (sccm)) pressure crab lX10-' (T
orr) The output microwave should be 600 (W), the high frequency should be 200 (W), and the wafer temperature should be near 0 ('C). In this case, it goes without saying that the etching is stopped by time control.

FIG. 9 shows a cutaway side view of essential parts for explaining the third embodiment of the present invention, and the same symbols as those used in FIGS. 3 to 6 indicate the same parts or have the same meanings. shall have.

In this embodiment, an insulator is buried in the element isolation trench 26 formed to reach the 2,1eGaAs crystal layer 22. In this process description, AfGaAs crystal J
The steps up to the formation of the inter-element isolation grooves 26 reaching i22 are completely the same as the steps explained with reference to FIGS. 3 to 6, so the explanation will be omitted and the next step will be explained.

(9)-1 By applying the MOVPE method, an insulator made of, for example, polycrystalline GaAs is selectively grown in the isolation trench 26 using the silicon dioxide film 25 as a mask to form the isolation region 26A. . Incidentally, the conditions for this selective growth are exemplified as follows.

Wafer temperature: 450 ("C) Gas composition: ASH31 [f/mjn] TMG O, 44 (sc cm) Growth rate: 100 (people/m1n) (9)-2 Removing the silicon dioxide film 25 used as a mask Thereafter, ohmic contact source electrodes 27I, 27! and drain electrodes 281.28□ are formed by applying a normal lift-off technique.

(9)-3 Applying conventional techniques, Schottky contact gate electrode 29. ．． Form 29□.

In the semiconductor device manufactured according to this example, GaA
Not only will electrons not leak from the surface of the s-crystal layer 23, but due to the presence of the hetero interface 24, electrons will not leak from deep areas. Furthermore, in this embodiment, the inter-element isolation groove 26
Since the insulator is embedded therein, the surface of the semiconductor device is flattened.

FIG. 10 shows a cutaway side view of essential parts for explaining the fourth embodiment of the present invention, and the same symbols as those used in FIG. 9 indicate the same parts or have the same meaning. do.

In this embodiment, an isolation region 30A consisting of an inter-element isolation trench 30 filled with an insulator is formed extending beyond the hetero interface 24 and into the AflGaAs crystal layer 22.

It is easy to form such an isolation region 30A, and the inter-element isolation groove 3 that penetrates into the AIGaAS crystal layer 22 can be easily formed.
0, an insulator made of polycrystalline GaAs, for example, may be selectively grown in the element isolation trench 30. Incidentally, in this case, the etching is naturally stopped by time control. Further, the conditions for selective growth may be the same as those for the process exemplified above.

11 to 14 are cross-sectional side views of the main parts of a compound semiconductor device at key points in the process for explaining the case of manufacturing the fifth embodiment of the present invention. This will be explained with reference to the figures.

In this process description, the process up to the formation of the opening 25A in the silicon dioxide film 25 serving as a mask is completely the same as the process described with reference to FIGS. 3 to 6, so it will be omitted, and the next step will be explained.

Refer to FIG. 1101)-1 By applying the RIE method, the silicon dioxide film 25
Using this as a mask, selective etching is performed to reach an appropriate depth from the surface of the GaAs crystal layer 23 to form the inter-element isolation grooves 31.
form. Incidentally, in this case, the etching is naturally stopped by time control. Further, the conditions for this etching may be the same as those for the process illustrated and explained above.

Refer to FIG. 12 (12)-1 After removing the silicon dioxide film 25 used as a mask, a resist process in normal photolithography is applied to form an opening 3 in the area of the isolation trench 30.
A photoresist film 32 having a thickness of 2A is formed.

See Figure 1303)-1 By applying the vacuum evaporation method and lift-off method,
A separation voltage application electrode 33 of a Schottky contact made of Affi, W, or the like is formed.

Refer to FIG. 14 Q4)-1 Applying a normal technique, ohmic contact source electrodes 27+, 27□ and drain electrodes 28□28□ are formed.

(+4)-2 Applying conventional techniques, Schottky contact gate electrode 29. ．． Form 29□.

In the semiconductor device manufactured in this way, as shown in the figure, when a separation voltage ■l is applied to the separation voltage application electrode 33, a depletion layer 34 extends from the Schottky contact and Aj! Since the GaAs crystal layer 22 is reached and the space between adjacent elements is completely closed, in this case as well, the GaAs
Not only electrons leak from the surface of the crystal layer 23, but also electrons do not leak from the deep part due to the existence of the hetero interface 24.

〔Effect of the invention〕

In the compound semiconductor device according to the present invention, there is provided a compound semiconductor crystal layer having a composition that forms a hetero-interface with the compound semiconductor crystal active layer, and an inter-element isolation trench that reaches at least from the surface into the compound semiconductor crystal active layer. have.

By adopting the above structure, carriers leaking from the compound semiconductor crystal active layer are completely blocked by the element isolation trench or depletion layer, and carriers attempting to leak deep into the compound semiconductor crystal active layer are also blocked by the presence of the hetero interface. This can greatly contribute to higher integration of compound semiconductor devices.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the main parts of a compound semiconductor device for explaining the present invention in detail, Fig. 2 is an energy band diagram of the semiconductor device seen in Fig. 1, and Figs. FIG. 7 is a cross-sectional side view of the main parts of a compound semiconductor device at important points in the process for explaining the case of manufacturing the first embodiment of the invention, which was manufactured by the process explained in FIGS. Side gate voltage v1 regarding the semiconductor device.
FIG. 8 is a diagram showing the relationship between I and drain current I; FIG. 8 is a cutaway side view of essential parts for explaining the second embodiment of the present invention; FIG.
The figure is a cutaway side view of essential parts for explaining the third embodiment of the present invention, FIG. 10 is a cutaway side view of essential parts for explaining the fourth embodiment of the present invention, and FIGS. 11 to 14 The figure is a cross-sectional side view of the main part of a compound semiconductor device at key points in the process for explaining the case of manufacturing the fifth embodiment of the present invention.
Fig. 5 is an explanatory diagram of the main parts to explain a conventional compound semiconductor device, Fig. 16 is a diagram showing the relationship between the side gate voltage V so and the drain current flowing through the transistor Q4,
FIG. 17 is a main part explanatory diagram illustrating a semiconductor device in which isolation regions are formed between elements, and FIG. 18 is a semiconductor device in which a voltage is applied by forming an impurity region of the opposite conductivity type to that of the semiconductor crystal substrate. Each of the figures shows an explanatory view of a main part illustrating the following. In the figure, 21 is a semiconductor crystal substrate, 22 is a first semi-insulating compound semiconductor crystal layer, 23 is a second semi-insulating compound semiconductor crystal layer, 24 is a hetero interface, and 26 is a hetero interface 14 from the surface. 27° is the source electrode, 28□ is the drain electrode, 29. indicate gate electrodes, respectively. Figure 2 Figure 2 25A Figure 15 10 V, (v) 5 Figure 7 Figure 3 Third implementation of this acceptance fIJ /') rO N Figure 13 Figure 14 Saki An explanatory diagram of the main parts of the conventional compound semiconductor device I for N theory T3?
Figure 5VB2 (V) Figure 16

Claims (1)

[Scope of Claims] 1. A compound semiconductor crystal layer interposed between a compound semiconductor crystal substrate and a compound semiconductor crystal active layer and having a composition that forms a heterointerface with the compound semiconductor crystal active layer; What is claimed is: 1. A compound semiconductor device comprising an element isolation groove extending from a surface to at least the compound semiconductor crystal active layer. 2. The compound semiconductor device according to claim 1, wherein a dielectric material is embedded in the element isolation trench.