JPH0385922A - Multiplex decoding circuit - Google Patents

Abstract

PURPOSE:To attain high speed decoding of a compression code data by applying parallel decoding to a compression code data by means of plural decoding circuits to which blocks split by split control circuit splitting the data to a prescribed block is sequentially assigned. CONSTITUTION:A split control circuit 2 splits a compression coding data 1 to a prescribed block number and a decoding circuit 4 consists of plural decoding circuits 4-1-4-n decoding the compression coding data 1. The compression coding data 1 received by the split control circuit 2 is split into a prescribed block number and assigned to an idle circuit of the decoding circuits 4-1-4-n and the assigned decoding circuits 4-1-4-n decode the compression code data 1 and the result is stored in a picture memory 5. That is, the compression coding data 1 is split and assigned sequentially to the plural decoding circuits 4-1-4-n, where the data is subject to parallel decode processing simultaneously. Thus, the compression code data is decoded at a high speed.

Description

[Detailed Description of the Invention] [Summary] Regarding a decoding circuit that decodes compressed encoded data, the compressed encoded data is divided and assigned to a plurality of decoding circuits to perform decoding processing simultaneously in parallel, thereby decoding the compressed encoded data at high speed. The system is equipped with a division control circuit that divides compressed encoded data into predetermined blocks, and a plurality of decoding circuits that sequentially allocate blocks divided by the division control circuit, so that decoding is performed in parallel by these multiple decoding circuits. Configure.

[Industrial application field]

The present invention relates to a decoding circuit that decodes compressed encoded data. In recent years, with the widespread use of image processing,
It is desired to decode and expand compression-encoded image data at high speed.

[Prior Art and Problems to be Solved by the Invention] Conventionally, when compressed image data is decoded, only one decoding circuit is used to sequentially decode it to generate an original image. For this reason, there is a problem in that the decoding performance has an upper limit depending on the ability of the decoding circuit, and high-speed decoding is not possible.

The present invention aims to decode compressed code data at high speed by dividing compressed code data and assigning it to a plurality of decoding circuits to perform decoding processing simultaneously and in parallel.

(Means to solve tl!!l!) FIG. 1 shows a basic configuration diagram of the present invention.

In the figure, a dividing circuit 111i11 divides compressed encoded data 1 into predetermined blocks.

The decoding circuit 4 is composed of a plurality of decoding circuits 4-1 to 4-n that decode the compressed encoded data 1.

The image memory 5 is a memory that stores image data decoded by the decoding circuits 4-1 to 4-n.

[Effect]

As shown in FIG. 1, the present invention divides compressed code data l received by a division control circuit 2 into predetermined blocks and allocates them to empty ones of decoding circuits 4-1 to 4-n.
These assigned decoding circuits 4-1 to 4-n decode the compressed code data l and store it in the image memory 5.

Therefore, compressed encoded data 1 is divided into multiple decoding circuits 4.
-1 to 4-n are sequentially allocated and decoded simultaneously in parallel, thereby making it possible to decode compressed encoded data at high speed.

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be explained in detail using FIGS. 1 to 3.

In FIG. 1, compressed code data 1 is the received compressed code data 1.
Encoded image data, such as MR (Mod
This is compressed encoded data that is encoded line by line using a (read) code.

The division control circuit 2 divides the compressed code data 1 into a predetermined block (
For example, it is divided into sections (for example, every predetermined number of lines) and allocated to an empty one of the decoding circuits 4-1 to 4-n that has completed the decoding process.

The division number designation register 3 is a register that stores the number of divisions into which the compressed code data l is to be divided, for example, the number of division lines m.

The decoding circuit 4 is composed of a plurality of decoding circuits 4-1 to 4-n, and decodes the compressed encoded data 1 in parallel.

The image memory 5 expands and stores image data decoded by the plurality of decoding circuits 4-1 to 4-n.

With the above configuration, the number m of lines divided and passed to the decoding circuits 4-1 to 4-n is set in advance in the division number specification register 3, and the division system n circuit 2 specifies the division number from the compressed code data 1. The compressed decoded data corresponding to the number m of lines taken out from the register 3 is sequentially assigned to the vacant decoding circuits 4-1 to 4-n, decoding processing is performed, and the decoded image data is stored line by line in the image memory. By sequentially developing and storing the image data in the corresponding positions of 5 and decoding it to the original image data, it becomes possible to simultaneously perform high-speed decoding in parallel by a plurality of decoding circuits 4-1 to 4n.

FIG. 2 shows an example of compressed code data. Here, EOL
1-1 is an end of file, which is a line termination code. Data 1-2, Di through Dn, are compression-encoded image data for each line. The compressed code data for l lives consists of, for example, Di and EOL.

FIG. 3 shows a configuration diagram of one embodiment of the present invention.

In FIG. 3, memory 1-3 is a memory that stores compressed encoded data.

The DMAC 6 reads the compressed code data l from the memory l-3 in units of, for example, 1 byte and sequentially sends the data to the division control circuit 2.
This is for MA transfer.

The division control circuit 2 converts the compressed code data into E O1.

(Line termination code)
) is comprised of a buffer 2-2 and the like that temporarily stores data for three hides.

The FIFO buffer 7-L 7-2 is a FIFO buffer that stores m947 pieces of compressed code data allocated from the division control circuit 2.

The decoding circuits 4-1 and 4-2 decode compressed encoded data.

The write circuit 8 writes the decoded image data to the position in the image memory 5 designated by the expansion position designation register 9.

Next, the operation of the configuration shown in FIG. 3 will be explained in detail using FIG.

In Fig. 4, ■ is m from the received compressed code data.
Extract data (1) for 547 minutes.

(2) passes the m547 worth of data (11) extracted in (2) to the decoding circuit fil 4-1 and activates it. In response to this activation, the decoding circuit (1) 4-1 is passed to the
The image data after decoding is expanded and written into the image memory 5 line by line.

(2) passes the extracted data (2) for m547 to the decoding circuit f2) 4-2 and starts it up. In response to this activation, the decoding circuit (2) 4-2 decodes the passed m547 worth of data, and expands and writes the decoded image data of the lever into the image memory 5 line by line.

In (2), similarly to (2) and (2), the extracted data for m547 +nl is passed to the decoding circuit +n+4-n and activated.

In response to this activation, the decoding circuit (nl 4-n) decodes the passed m547 worth of data, and in step (2), the decoded image data is developed and written into the image memory 5 line by line.

By the above processing, the received compressed encoded data is converted into m54
The image data is divided into 7 minutes each, passed sequentially to an empty one of the decoding circuits 114-1 to 1nl4-n and activated, and the decoded image data is developed and stored in the image memory 5. By decoding, multiple decoding circuits il+
4-1 to decoding circuit (n) 4-n enables high-speed decoding in parallel.

〔Effect of the invention〕

As explained above, according to the present invention, a configuration is adopted in which compressed encoded data is divided and allocated to the vacant ones among the plurality of decoding circuits 4-1 to 4-n, and the decoding process is performed simultaneously and in parallel. Therefore, compressed encoded data for 100 pages can be decoded at high speed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is an example of compressed code data, FIG. 3 is a diagram showing one implementation of the present invention, and FIG. 4 is an explanatory diagram of the operation of the present invention. In the figure, 1 is compressed encoded data, 2 is a divided wI box circuit, and 4 is a divided wI box circuit.
4-1 to 4-n represent decoding circuits, and 5 represents an image memory.

Claims (1)

[Claims] A decoding circuit that decodes compressed encoded data includes a division control circuit (2) that divides the compressed encoded data into predetermined blocks, and a plurality of decoders that sequentially allocate the divided blocks by the division control circuit (2). A multiple decoding circuit comprising: a circuit (4), and configured such that decoding is performed in parallel by the plurality of decoding circuits (4).