JPH0385014A - Pwm/dc voltage conversion circuit - Google Patents

Pwm/dc voltage conversion circuit

Info

Publication number
JPH0385014A
JPH0385014A JP22190589A JP22190589A JPH0385014A JP H0385014 A JPH0385014 A JP H0385014A JP 22190589 A JP22190589 A JP 22190589A JP 22190589 A JP22190589 A JP 22190589A JP H0385014 A JPH0385014 A JP H0385014A
Authority
JP
Japan
Prior art keywords
current source
flowing
capacitor
voltage
pwm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22190589A
Other languages
Japanese (ja)
Inventor
Michio Nakao
中尾 美智男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP22190589A priority Critical patent/JPH0385014A/en
Publication of JPH0385014A publication Critical patent/JPH0385014A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To attain PWM/DC voltage conversion with less power consumption and load fluctuation by switching a flowing-in current source and a flowing-out current source based on a PWM signal so as to act the result on a capacitor and extracting the capacitor voltage. CONSTITUTION:A flowing-in current source 1 and a flowing-out current source 2 connect to a capacitor C alternatively with a changeover switch 3 and the changeover of the changeover switch 3 is controlled with a PWM signal given through a terminal 4. The constant currents I1, I2 of the flowing-in current source 1 and the flowing-out current source 2 are made identical to each other. By switching the flowing-in current source 1 and the flowing-out current source 2 with respect to the capacitor C by using a PWM signal, a DC voltage proportional to a time ratio of the connection to the flowing-in current source 1 and the flowing-out current source 2 and the constant current 1 and inversely proportional to the capacitance of the capacitor C is led out at an output terminal 5.

Description

【発明の詳細な説明】 皮栗圭生剋里欽顆 本発明はPWM(パルス幅変調)信号をDC(直流)電
圧に変換するPWM/DC電圧変換回路に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PWM/DC voltage conversion circuit that converts a PWM (pulse width modulation) signal into a DC (direct current) voltage.

従来生技査 斯るPWM/DC電圧変換回路はマイクロコンピュータ
から出力されるPWM信号により直流電圧制御を行う回
路(例えばテレビジボン受像機等の選局回路)に使用さ
れる。
BACKGROUND OF THE INVENTION Such a PWM/DC voltage conversion circuit is used in a circuit (for example, a channel selection circuit of a television set) that controls a DC voltage using a PWM signal output from a microcomputer.

従来のPWM/DC電圧変換回路は第6図に示すように
マイクロコンピュータから与えられたPWM信号をトラ
ンジスタ(QIO)で増幅した後、ローパスフィルタ(
11)でDC電圧に変換し、その出力を演算増幅器(1
0)のマイナス入力端子(−)に供給している。この第
6図の回路は選局回路の一部を威しており、前記演算増
幅器(10)はそのプラス入力端子(+)に33V電源
電圧を抵抗(+2&) (R?)で分圧して得た電圧を
抵抗(R6)を通して入力しており、出力には同調電圧
を発生するようになっている。前記ローパスフィルタ(
II)は抵抗(1?り (R4)とコンデンサ(C+)
とから構成されている。
As shown in Figure 6, a conventional PWM/DC voltage conversion circuit amplifies a PWM signal given from a microcomputer using a transistor (QIO), and then passes it through a low-pass filter (
11) into a DC voltage, and the output is sent to an operational amplifier (1
0) is supplied to the negative input terminal (-). The circuit shown in Fig. 6 functions as a part of the channel selection circuit, and the operational amplifier (10) divides the 33V power supply voltage to its positive input terminal (+) with a resistor (+2&) (R?). The obtained voltage is input through a resistor (R6), and a tuning voltage is generated at the output. The low pass filter (
II) is a resistor (1? (R4) and a capacitor (C+)
It is composed of.

Hが ° しようとする課 上述のようにPWM信号を増幅した後、これをローパス
フィルタで直流化する従来のPWM/Dc1を圧変換回
路では電圧制御範囲(同調電圧範囲)を広くするために
はトランジスタ(Q、。)のコレクタと電源(33V 
)との間に接続されている抵抗(R8)の値を小さくし
なければならない。しかし、このように抵抗(Rg)の
値を小さくすると、比較的大きな電流が流れることにな
るため消費電力を小さくすることができないという欠点
が生じる。しかも、その電流はON33/Ihの変動が
あるため負荷変動が大きくなってしまう。
As mentioned above, in order to widen the voltage control range (tuning voltage range) in the conventional PWM/Dc1 pressure conversion circuit, which amplifies the PWM signal and converts it to DC using a low-pass filter, The collector of the transistor (Q,.) and the power supply (33V
) must be made small. However, when the value of the resistance (Rg) is reduced in this way, a relatively large current flows, resulting in a drawback that power consumption cannot be reduced. Moreover, since the current includes ON33/Ih fluctuations, the load fluctuations become large.

本発明はこのような点に鑑みなされたものであって消費
電力及び負荷変動の少ないPWM/DC電圧変換回路を
提供することを目的とする。
The present invention has been made in view of these points, and it is an object of the present invention to provide a PWM/DC voltage conversion circuit with low power consumption and low load fluctuation.

i、を”ンするための 上記の目的を達成するため本発明のPWM/DC電圧変
換回路は、コンデンサと、該コンデンサに対する流入電
流源及び流出電流源と、PWM信号に基づいて前記流入
電流源と流出電流源を切換えて前記コンデンサに作用さ
せる切換え手段と、前記コンデンサの電圧を取出す手段
と、から構成されている。
The PWM/DC voltage conversion circuit of the present invention includes a capacitor, an inflow current source and an outflow current source for the capacitor, and an inflow current source and an outflow current source for the capacitor. and switching means for switching the outflow current source to act on the capacitor, and means for taking out the voltage of the capacitor.

立−里 このような構成によると、切換え手段による流出電流源
、流入電流源の切換えによってコンデンサの充放電が行
われる。そして、その切換えはPWM信号に基づいて行
われる。従って、PWM信号のパルス幅に応じて充電時
間や放電時間が変わり、コンデンサの電圧が変わる。
According to this configuration, the capacitor is charged and discharged by switching between the outflow current source and the inflow current source by the switching means. The switching is performed based on a PWM signal. Therefore, the charging time and discharging time change depending on the pulse width of the PWM signal, and the voltage of the capacitor changes.

大」L燃 以下、本発明の実施例を図面に従って説明する。Large” L-fuel Embodiments of the present invention will be described below with reference to the drawings.

第1図において、(1)はコンデンサ(C)に充電電流
を与えるための流出電流源であり、(2)は同じく放電
電流を与える流入電流源である。これらの電流源(1)
 (2)は切換えスイッチ(3)によって択一的にコン
デンサ(C)に接続され、その機能を行う。
In FIG. 1, (1) is an outflow current source for providing a charging current to the capacitor (C), and (2) is an inflow current source that also provides a discharging current. These current sources (1)
(2) is alternatively connected to the capacitor (C) by a changeover switch (3) to perform its function.

切換えスイッチ(3)の切換えは端子(4)を通して与
えられるPWM信号によって制御される。例えば、PW
M信号のローレベル期間では切換スイッチ(3)は接点
(3a)側に設定され、ハイレベル期間では接点(3b
)側に設定される。ここで、流出電流源(1)と流入電
流源(2)の定電流1.、1.は互いに同一(1+ =
1!−1)とする、ただし、これらの定電流1+、 I
tは必ずしも同一である必要はない。
The switching of the changeover switch (3) is controlled by a PWM signal applied through the terminal (4). For example, PW
During the low level period of the M signal, the changeover switch (3) is set to the contact (3a) side, and during the high level period, the changeover switch (3) is set to the contact (3b) side.
) side. Here, the constant current 1. of the outflow current source (1) and the inflow current source (2). , 1. are the same as each other (1+ =
1! −1), but these constant currents 1+, I
t does not necessarily have to be the same.

而して、第1図ではPWM信号でコンデンサ(C)に対
し流出電流源(1)と流入電流源(2)を切換えること
により流出電流源(1)と流入電流源(2)につながる
時間比と定電流■に比例し、コンデンサ(C)の容量に
反比例した直流電圧が出力端子(5)に導出される。尚
、(R) (R)は比較的大きな値に選ばれた抵抗であ
る。
In Fig. 1, by switching between the outflow current source (1) and the inflow current source (2) for the capacitor (C) using a PWM signal, the time period during which the outflow current source (1) and the inflow current source (2) are connected is determined. A DC voltage proportional to the ratio and the constant current ■ and inversely proportional to the capacitance of the capacitor (C) is derived to the output terminal (5). Note that (R) (R) is a resistance selected to have a relatively large value.

次に第1図の構成を具体化した第2図について説明する
。同図において、トランジスタ(Qs) (口、)はカ
レントミラー接続の流出電流源(1)を構成し、(Q4
) (Qs) (Qt) (Ql)は同じくカレントミ
ラー接続の流入電流源(2)を構成している。これらの
電流源(1) (2)の入力端はそれぞれトランジスタ
(Ql)(Qりのコレクタに接続されている。トランジ
スタ(口、)(Qt)はエミッタ側に共通接続された定
電流源(6)と共に差動増幅器(7)を構成しており、
トランジスタ(口、)のベースは定電圧源(8)に接続
され、トランジスタ(QりのベースはPWM信号入力端
子(9)に接続されている。
Next, FIG. 2, which embodies the configuration of FIG. 1, will be explained. In the same figure, a transistor (Qs) constitutes a current mirror-connected outflow current source (1), and (Q4
) (Qs) (Qt) (Ql) similarly constitutes an inflow current source (2) of current mirror connection. The input terminals of these current sources (1) and (2) are respectively connected to the collectors of transistors (Ql) (Q). 6) constitutes a differential amplifier (7),
The base of the transistor (Q) is connected to a constant voltage source (8), and the base of the transistor (Q) is connected to a PWM signal input terminal (9).

次に第2図の回路の動作を第3図の信号波形図を参照し
て説明する。差動増幅器(7)はトランジスタ(Ql)
のベースに印加されている定電圧(V th)とトラン
ジスタ(0□)のベースに印加されているPWM信号と
を比較し〔第3図(a))、PWM信号が定電圧(Vt
h)よりも高い部分ではトランジスタ(口l)がOFF
でトランジスタ(Q2)がONとなり、流入電流源(2
)が作動してコンデンサ(C)を定電流■で放電させる
。この放電電流はトランジスタ(O6)を通して接地点
へ流れる。このとき、流出電流源(1)はトランジスタ
(Q、)がOFFであるため作動せず、トランジスタ(
Ql)(口、)はカットオフとなっている。
Next, the operation of the circuit shown in FIG. 2 will be explained with reference to the signal waveform diagram shown in FIG. Differential amplifier (7) is a transistor (Ql)
The constant voltage (V th) applied to the base of the transistor (0□) is compared with the PWM signal applied to the base of the transistor (0
The transistor (portion l) is OFF at the part higher than h)
The transistor (Q2) turns on, and the inflow current source (2
) operates to discharge the capacitor (C) with a constant current ■. This discharge current flows to the ground point through the transistor (O6). At this time, the outflow current source (1) does not operate because the transistor (Q, ) is OFF, and the transistor (
Ql) (口, ) is the cutoff.

逆にPWM信号が定電圧(Vth)よりも低い部分では
トランジスタ(Q l)がONで、トランジスタ(Q2
)がOFFとなるので、流出電流源(1)と流入電流源
(2)は切換えられ、流出電流源(1)が作動し、流入
電流源(2)は不作動となる。このため、コンデンサ(
C)はトランジスタ(06)を通して定電流Iで充電さ
れる。
Conversely, when the PWM signal is lower than the constant voltage (Vth), the transistor (Ql) is ON and the transistor (Q2
) is turned off, the outflow current source (1) and inflow current source (2) are switched, the outflow current source (1) is activated and the inflow current source (2) is inactivated. For this reason, the capacitor (
C) is charged with a constant current I through the transistor (06).

第3図において、(b)は流入電流源(2)による放電
電流を、(C)は流出電流源(1)による充電電流を示
している。また、(d)はコンデンサ(C)の電圧を示
している。PWM信号の周期(T)に対する放電期間(
T1)と充電期間(T2)の比が変わることにJっでコ
ンデンサ(C)の電圧も変化する。
In FIG. 3, (b) shows the discharging current caused by the inflow current source (2), and (C) shows the charging current caused by the outflow current source (1). Moreover, (d) shows the voltage of the capacitor (C). The discharge period (T) of the PWM signal (
As the ratio between T1) and the charging period (T2) changes, the voltage of the capacitor (C) also changes.

第4図は入力されるPWM信号のデユーティb(T I
 /T X 100)と出力電圧(直流)との関係を汚
しており、そのうち(イ)は流出電流(充電電流)I、
と流入電流(放電電流)T2とを同一とし大場合、 (
ロ)は+ + > I tとした場合、 (ハ)がhく
T2とした場合の特性をそれぞれ表わしている。
Figure 4 shows the duty b (T I
/T x 100) and the output voltage (DC).
When the inflow current (discharge current) T2 is the same and large, (
(b) represents the characteristics when + + > I t, and (c) represents the characteristics when h is T2.

第5図は選局回路に第2図の回路を用いた場その例を示
しており、コンデンサ(C)の出力が演寥増幅器(10
)のマイナス入力端子(−)に与えらする。演算増幅器
(10)のプラス入力端子(+)にに第6図の従来例と
同一の回路が接続されている。
Figure 5 shows an example of a channel selection circuit using the circuit shown in Figure 2, in which the output of the capacitor (C) is connected to the performance amplifier (10
) to the negative input terminal (-) of the terminal. The same circuit as the conventional example shown in FIG. 6 is connected to the plus input terminal (+) of the operational amplifier (10).

発奥立剋果 本発明によれば少ない消費電流(従って少なし消費電力
)で出力の直流電圧範囲を広くとることができる。また
、このように消費電流を小さくフることができるので、
電源の負荷変動をなくすことが可能である。更に本発明
の回路は上記実施伊からも分るようにtC化にも適する
According to the present invention, it is possible to widen the output DC voltage range with less current consumption (therefore, less power consumption). In addition, since the current consumption can be reduced in this way,
It is possible to eliminate load fluctuations in the power supply. Furthermore, the circuit of the present invention is also suitable for tC conversion, as can be seen from the above implementation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明を実施したPWM/DC電圧変換回路を
示す図であり、第2図はその具体的構成を示す回路図、
第3図は第2図を説明するための信号波形図、第4図は
PWM信号と出力電圧との関係について説明するための
特性図である。第5図は第2図の回路を選局回路に用い
た場合の回路図である。第6図は従来例を示す回路図で
ある。 (1)−流出電流源、(2)−・−流入電流源。 (3)−・切換えスイッチ、 (5) −・出力端子。 (7)・・・差動増幅器、(C)・・−コンデンサ。
FIG. 1 is a diagram showing a PWM/DC voltage conversion circuit implementing the present invention, and FIG. 2 is a circuit diagram showing its specific configuration.
FIG. 3 is a signal waveform diagram for explaining FIG. 2, and FIG. 4 is a characteristic diagram for explaining the relationship between the PWM signal and the output voltage. FIG. 5 is a circuit diagram when the circuit shown in FIG. 2 is used as a channel selection circuit. FIG. 6 is a circuit diagram showing a conventional example. (1) - Outflow current source, (2) - - Inflow current source. (3) - Selector switch, (5) - Output terminal. (7)...Differential amplifier, (C)...-capacitor.

Claims (1)

【特許請求の範囲】[Claims] (1)コンデンサと、該コンデンサに対する流入電流源
及び流出電流源と、PWM信号に基づいて前記流入電流
源と流出電流源を切換えて前記コンデンサに作用させる
切換え手段と、前記コンデンサの電圧を取出す手段と、
から成るPWM/DC電圧変換回路。
(1) A capacitor, an inflow current source and an outflow current source for the capacitor, switching means for switching the inflow current source and outflow current source to act on the capacitor based on a PWM signal, and means for extracting the voltage of the capacitor. and,
PWM/DC voltage conversion circuit consisting of.
JP22190589A 1989-08-29 1989-08-29 Pwm/dc voltage conversion circuit Pending JPH0385014A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22190589A JPH0385014A (en) 1989-08-29 1989-08-29 Pwm/dc voltage conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22190589A JPH0385014A (en) 1989-08-29 1989-08-29 Pwm/dc voltage conversion circuit

Publications (1)

Publication Number Publication Date
JPH0385014A true JPH0385014A (en) 1991-04-10

Family

ID=16773998

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22190589A Pending JPH0385014A (en) 1989-08-29 1989-08-29 Pwm/dc voltage conversion circuit

Country Status (1)

Country Link
JP (1) JPH0385014A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5812427A (en) * 1995-04-24 1998-09-22 Nippondenso Co., Ltd. Physical quantity detecting apparatus
US6082196A (en) * 1996-04-26 2000-07-04 Denso Corporation Physical quantity detecting device
JP2020532275A (en) * 2017-09-30 2020-11-05 深▲セン▼市▲華▼星光▲電▼半▲導▼体▲顕▼示技▲術▼有限公司 Liquid crystal display panel and switching control circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5812427A (en) * 1995-04-24 1998-09-22 Nippondenso Co., Ltd. Physical quantity detecting apparatus
US6082196A (en) * 1996-04-26 2000-07-04 Denso Corporation Physical quantity detecting device
JP2020532275A (en) * 2017-09-30 2020-11-05 深▲セン▼市▲華▼星光▲電▼半▲導▼体▲顕▼示技▲術▼有限公司 Liquid crystal display panel and switching control circuit

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