JPH0384929A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance a close contact property between a lead and a bump by a method wherein a bump whose area is relatively large is divided into small bumps, its plating growth speed is approached to that of a bump whose area is relatively small and a height of the bumps is made uniform. CONSTITUTION:Regarding at least a bump whose area is largest, the bump is divided, and a growth operation is executed by making an area of bumps nearly equal; then, a plating growth speed becomes nearly uniform inside a chip, and an irregularity in a plating height can be reduced. For example, since an area of a pad 6a for power-supply line use is about three times that of a pad 6b for signal line use, a bump 5a is divided into three so that the same size as that of a bump 5b for signal line use can be used. Concretely, a bump (bump for power-supply line use) whose Al pad size is large is divided in a designing stage; a mask is made in such a way that a size of a bump is as large as that of a bump (bump for signal use) whose size is small. After that, a tab bonding operation is executed by using an ordinary heating tool. Thereby, a close contact property between a lead and the bump becomes good.

Description

[Detailed Description of the Invention] [Summary] A semiconductor device having a process of forming bumps by plating on each of metal pads having different areas formed on the surface of a semiconductor chip, and connecting leads to each of the bumps by the TAB method. Regarding the manufacturing method, in order to improve the adhesion between the lead and the bump during ILB and improve its reliability, the bump formed on the metal pad with almost the maximum area without any internal conflict between the metal pads is required. The bumps are formed by plating as a plurality of bumps spaced apart from each other, the sizes of all the bumps are approximately equal, and the leads are uniformly connected to each bump.

[Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device,
More specifically, it relates to a method for manufacturing a semiconductor device that includes a step of forming bumps by plating on each of metal pads having different areas formed on the surface of a semiconductor chip, and connecting leads to each of the bumps using the TAB method. It is.

In recent years, with the further miniaturization and higher integration of semiconductor devices, the leads, which are the mounting components for mounting semiconductor chips incorporating semiconductor ICs into packages, have become increasingly miniaturized, making mounting using conventional wire bonding difficult. In addition, requirements for reliability in terms of resistance to stress and radiation shielding against stress applied to semiconductor chips within mounted packages are becoming increasingly strict.

[Conventional technology]

The conventional TAB method will be explained with reference to FIG. In the figure,
1 is a package board made of Al2tOs, etc., 2 is a wiring pattern on the board side, 3 is a semiconductor chip, 4 is a Cu wire or a TAB lead made of a Cu wire plated with Sn, 5 is an Au
It is a metal bump made of %Cu or pb-Sn alloy. A polyimide coating (not shown) is applied to the lower surface of the semiconductor chip 3 (the surface facing the package substrate 1) to protect the semiconductor chip 3 from radiation such as alpha rays emitted from the package substrate 2.

The connection between the TAB leads 4, 4' and the semiconductor chip (3) side is ILB (Inner Lead Bonding).
), while the connection between the TAB leads 4.4' and the package board (1) side is called OL B (Outer Le
ad bonding). Until now, T.A.
It is possible to connect the semiconductor chip 3 and the package substrate up to a B lead pitch interval of 100 μm and a number of TAB lead terminals of approximately 500 bins.

Below, the structure on the ILB side will be explained with reference to FIGS. 3 and 4. In Figure 0, 6 is the Aβ wiring exposed on the surface of the semiconductor chip (3), and 7 is the insulating layer covering the semiconductor surface. It is a cover membrane.

In conventional Au bump manufacturing technology, bumps 5a with a large size (area) such as AQ pads used for power supplies and bumps 5b with small sizes such as Aβ pads used for signal lines are plated in the same plating bath. Manufactured by growth. However, with this plating growth technique, it has been found that the growth rate of the plating depends on the plating area, and if the size of the Aβ bud is large, the height of the Au bump becomes high. Figure 5 shows experimental data conducted by the present inventor, and shows non-cyanide or cyanide plating bath (
current density 0.4 A/cm"), surface area 9
When Au bumps of 000 μm and 54,000 μd were grown, it was shown that the plating height (thickness) varied greatly with the growth time.

[Problem to be Solved by the Invention J] Due to such a difference in plating growth rate, the heights of the completed Au bumps 5 vary.

The height of the Au bump 5 is generally from several μm to several tens of μm, with 20 to 30 μm being the most common.Also, the size of Aβ bumps is divided into two types, one for signal lines and one for power lines, and the former has a resistance of 7000 to 10000 μm. , the latter is 20000~s o
o o o When Au bumps 5, which are often used in ILnf and have such a difference in area, are made using the conventional method, the thickness is several μmxl.
A height variation of 0 μm occurs. For this reason, when ILB is performed, a large number of leads are pressed against each bump 5 at once by a tool, and at this time, the taller Au bumps 5 are crushed, while the lower Au bumps have a small local gap between them and the leads. This makes it difficult to achieve complete bonding, resulting in poor adhesion. That is, in the conventional Au bump plating method, the adhesion between the leads and the bumps tends to be poor on the signal line side during ILB. Here, the current on the signal line side is weaker than on the power line side, so
Even a slight bonding defect may cause a conduction defect, which may greatly impair reliability. In addition, if the adhesion is poor,
The signal line side junction becomes sensitive to stress due to temperature rise during use and thermal cycles due to cooling, which may significantly impair the reliability of the device.

Therefore, it is an object of the present invention to improve the adhesion between leads and bumps during ILB and improve the reliability thereof.

[Means for Solving the Problems] The method of the present invention includes, if necessary, separating a plurality of bumps formed on a metal pad whose area is approximately the maximum even if there is no internal conflict between the metal pads at intervals from each other. The invention is characterized in that the bumps are formed by plating, the sizes of all the bumps are approximately equal, and the leads are uniformly connected to each bump.

Conventionally, both large and small Aβ bud sizes,
However, in the present invention, the height of all bumps can be made as uniform as possible by dividing the large bump and making it the same size as the small bump, or making it close to the small bump. It is something to do. Here, if we divide the bumps at least for the bumps with the largest area and grow them with approximately the same area, we get
The plating growth rate becomes almost uniform within the chip, and variations in the plating height can be reduced.

In many semiconductor chips, the power line pads are significantly larger than the signal line pads, as described above. Therefore, the size of the pad is classified into two ranges, and the bump division described above is performed for the pad that belongs to the larger range and has the maximum size.

If necessary, if the size difference between the largest and smallest dimensions is large, the bumps can also be split for intermediate sized pads, rather than multiple pad sizes being separated into separate ranges as described above. If there are some duplicates,
A metal pad having an area of about 1.5 times or more, preferably twice or more of the smallest area of the metal pad among the metal pads,
A plurality of bumps having approximately the same size as the bumps formed on the metal pad having the minimum area are formed at intervals from each other, and a lead is connected to each bump,
It becomes possible to make the plating growth rate uniform for all pads.

For example, in this case, if the minimum dimension is (Smin (μm2)), a pad that is a little less than twice the size of Sm1n will have one bump, a pad that is about 2 to 3 times as large will have two bumps, and so on. The number of bumps is changed depending on the pad area.

[Function] In the present invention, by dividing a relatively large bump into smaller bumps, the plating growth rate can be reduced.
It is possible to bring the area closer to a bump with a relatively small area and make the height of the bump uniform, thereby improving the adhesion between the lead and the bump during ILB. Hereinafter, the present invention will be explained in more detail by way of examples with reference to FIGS. 1 and 6.

[Example] FIG. 1 is a drawing in which the same layers and the like as in FIG. 4 are indicated by the same reference numerals. In the figure, 8 is lead, 10 is Sn plating, 9 is C
These are U-rays, all of which are publicly known. The cover layer 7 is selectively removed using a resist, and plating is performed with, for example, a non-cyan or cyan plating solution while leaving the resist.

In this plating, as usual, the pads 6a, 6b
is connected to the cathode, so the A4 pad 6a resembles a common cathode, but the cathode area that determines the plating speed is not the product of the AJ2A2 pad 6a, but the area of the AJ2 pad 6a of the part exposed outside the resist. Therefore, bump 5a
The plucking speed is significantly reduced.

FIG. 6 is a plan view showing the positions and areas of the AJ2 pad 6, bumps 5, and leads 8. Since the power line pad 6a has an area about three times that of the signal line pad 6b, the bump 5a was divided into three parts, each having the same dimensions as the signal line bump 5b.

Specifically, at the design stage, AI! , divide the large pad size (power bump) and divide it into smaller pad size (power bump).
Just make a mask so that it is the same size as the signal bump).

Tab bonding is then performed using a conventional heating tool.

[Effects of the Invention] As explained above, according to the present invention, by making the bump height uniform, the adhesion between the lead and the bump can be improved, and reliability can be greatly improved. This greatly contributes to improving assembly yield.

[Brief explanation of drawings]

FIG. 1 is a detailed explanatory diagram of the present invention, Figure 2 is a TAB explanatory diagram of the prior art. Figure 3 is a plan view of a conventional bump. Figure 4 is a cross-sectional view of a conventional bump. Figure 5 is a graph showing the relationship between plating thickness and plating time. FIG. 6 is a plan view of an embodiment of the present invention.

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device comprising the steps of forming bumps by plating on each of metal pads having different areas formed on the surface of a semiconductor chip, and connecting leads to each of the bumps, in which at least one of the metal pads is The bump formed on the metal pad with approximately the largest area is formed by plating as a plurality of bumps spaced apart from each other, if necessary, and the size of all the bumps is approximately equal, and each bump is A method for manufacturing a semiconductor device, characterized by uniformly connecting leads to a semiconductor device.