JPH038443U - - Google Patents

Info

Publication number
JPH038443U
JPH038443U JP6950789U JP6950789U JPH038443U JP H038443 U JPH038443 U JP H038443U JP 6950789 U JP6950789 U JP 6950789U JP 6950789 U JP6950789 U JP 6950789U JP H038443 U JPH038443 U JP H038443U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit package
internal connection
connection electrodes
periphery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6950789U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6950789U priority Critical patent/JPH038443U/ja
Publication of JPH038443U publication Critical patent/JPH038443U/ja
Pending legal-status Critical Current

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の斜視図、第2図は
本実施例による収容部の形状を説明する平面図、
第3図は従来の集積回路パツケージの一例を示す
斜視図、第4図は従来例の収容部の形状を説明す
る平面図である。 1,7……集積回路パツケージ、2……外部接
続用端子、3……凹部、4……内部接続用電極、
5,8……収容部、6,9……集積回路基板。
FIG. 1 is a perspective view of an embodiment of the present invention, and FIG. 2 is a plan view illustrating the shape of the accommodating portion according to the embodiment.
FIG. 3 is a perspective view showing an example of a conventional integrated circuit package, and FIG. 4 is a plan view illustrating the shape of the accommodating portion of the conventional example. 1, 7... Integrated circuit package, 2... Terminal for external connection, 3... Recess, 4... Electrode for internal connection,
5, 8...Accommodating part, 6, 9...Integrated circuit board.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 内部周囲に内部接続用電極と外部周囲に外部接
続用端子をそれぞれ具備し且つ内部にほぼ四角形
の集積回路基板の収容部を有する集積回路パツケ
ージにおいて、前記内部接続用電極を配した周囲
の少なくとも2個所に凹部を設けたことを特徴と
する集積回路パツケージ。
In an integrated circuit package having internal connection electrodes on the inside periphery and external connection terminals on the outside periphery, and having a substantially rectangular integrated circuit board accommodating part inside, at least two of the peripheries around which the internal connection electrodes are arranged are provided. An integrated circuit package characterized by having recesses provided at certain locations.
JP6950789U 1989-06-13 1989-06-13 Pending JPH038443U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6950789U JPH038443U (en) 1989-06-13 1989-06-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6950789U JPH038443U (en) 1989-06-13 1989-06-13

Publications (1)

Publication Number Publication Date
JPH038443U true JPH038443U (en) 1991-01-28

Family

ID=31604870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6950789U Pending JPH038443U (en) 1989-06-13 1989-06-13

Country Status (1)

Country Link
JP (1) JPH038443U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61152046A (en) * 1984-12-26 1986-07-10 Fujitsu Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61152046A (en) * 1984-12-26 1986-07-10 Fujitsu Ltd Semiconductor device

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