JPH0382913A - Signal processing circuit for encoder - Google Patents

Abstract

PURPOSE:To make it possible to detect a position highly accurately by providing a reference sine-wave-signal generating means, a correcting-data generating means, a correcting means, a multiplying means and a detecting means. CONSTITUTION:Mainly, an up/down counter 45 and a ROM 42 constitute a reference sine-wave-signal generating means. A RAM 49 constitutes a correcting- data generating means. An adding circuit 50 constitutes a correcting means. Furthermore, multiplying circuits 41a and 41b constitute a multiplying means. A subtracting circuit 43, a comparator 44, a zero-cross-pulse generating circuit 46, a latch circuit 47 and the like constitute a detecting means. The relative position of a movable part is detected based on a correction reference signal obtained by correcting a reference sine wave signal. Therefore, the relative position of the movable part can be accurately obtained even if the sine wave signal from an encoder is deviated from an accurate sine wave. The correcting signal data means generates the correction data in response to a temporary position when the deviating amount is changed in response to the value of the relative position and in response to the second parameter when the deviating amount is changed in response to the second parameter.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a signal processing circuit for an encoder as a position detection device.

(Prior Art) Encoders used as position detection devices include types that can obtain a sine wave two-phase output signal, such as a so-called resolver and an encoder disclosed in Japanese Patent Application Laid-Open No. 62-8015. Since this type of encoder detects the position according to the introduction of the values of two sine wave signals, it has the advantage of being able to perform highly accurate position detection in principle.

(Problem to be Solved by the Invention) However, the two-phase sine wave signal output from the encoder is not a precise sine wave and generally includes errors.

For example, errors caused by the mechanical structure of the encoder always occur at the same rotational position of the rotary encoder. Furthermore, such errors may also change depending on the environmental temperature of the encoder. Conventionally, since the sine wave two-phase output signal of the encoder contained errors in this way, it was difficult to actually perform highly accurate position detection.

(Object of the Invention) The present invention was made to solve the above-mentioned problems in the prior art, and its purpose is to provide a signal processing circuit for an encoder that can perform highly accurate position detection. .

(Means for Solving the Problem) In order to solve the above-mentioned problem, in a first configuration of the present invention, the relative position of the movable part with respect to the fixed part is detected as a phase variable from an encoder attached to a predetermined movable part. A signal processing circuit of an encoder for detecting the relative position by receiving first and second sine wave signals of different phases, which include the following:

■ A reference sine waveform that generates first and second reference sine wave signals of different phases as signals having an ideal sine wave waveform with the temporary position as a phase variable while changing the temporary position as a variable parameter over time. Wave signal generation means.

(i) The first and second correction data, which are obtained in advance based on the deviation from the ideal sine wave waveform of the first and second sine wave signals that change depending on the relative position, are adjusted according to the temporary position. correction data generating means for storing first and second correction data in accordance with the temporary position;

(2) A correction means for generating first and second corrected reference signals by correcting the first and second reference sine wave signals with the first and second correction data, respectively.

■ The first and second correction reference signals are respectively
By multiplying by the second sine wave signal, the first and second
multiplication means for producing a multiplied signal.

(2) Detection means that calculates a difference between the first and second multiplied signals and generates the temporary position as a detected value of the relative position when the difference is equal to a predetermined reference difference value.

In the second configuration of the present invention, instead of the correction data generating means in the first configuration,
first and second correction data obtained in advance based on the deviation of the sine wave signal from the ideal sine wave waveform are stored according to the second parameter, and the first and second correction data are stored according to the second parameter. and a correction data generating means for generating first and second correction data respectively.

Note that the term "position" in this embodiment includes not only a position on a linear axis but also a rotation angle around a rotation axis. Furthermore, the term "sine wave" is a term in a broad sense that includes not only a sine wave in the narrow sense represented by sin θ, but also a cosine wave whose phase is shifted from the sine wave.

(Function) The relative position of the movable part is detected based on the corrected reference signal obtained by correcting the reference sine wave signal, so even if the sine wave signal from the encoder deviates from an accurate sine wave, the relative position of the movable part is detected. can be determined accurately.

If the amount of deviation of the sine wave signal from the encoder from the ideal sine wave changes depending on the relative position value,
The correction signal data means may generate correction data depending on the low position.

Moreover, when the amount of deviation changes according to the second parameter, the correction data generating means may generate the correction data according to the second parameter.

(Embodiment) A. Overall configuration of the apparatus FIG. 1 is a block diagram showing the configuration of a control system to which an embodiment of the present invention is applied. This control system includes a first encoder 10, a second encoder 20, and a first
a second signal processing circuit 30 for the encoder, a second signal processing circuit 40 for the second encoder, and a control device 60.
and a switch circuit 70.

The first and second encoders 10.20 have the same rotation axis α
Rotary encoders are installed around each. The first encoder 10 generates a sinusoidal output signal e e in which one rotation of the rotation axis α corresponds to one period. On the other hand, in the second LA' IB encoder 20, one rotation of the rotation axis α has N periods (
(N is an integer from tens to hundreds). FIG. 2 shows these sine wave output signals CIA' IB, e2A' e2B, and The phase of the sine wave output signal e e1^' 2A and the second sine wave output signal e and e is 91
．． 8 2B O° different. The first signal processing circuit 3o receives the sinusoidal output signal CIA'e1B from the first encoder 10, processes it, and generates a first rotation angle θ1 as the absolute position of the rotation axis α.

On the other hand, the second signal processing circuit 40
The sinusoidal output signal from e and the 28th"
It receives the detected value of the first rotation angle θ1 from the signal processing circuit 30 of 2B1 and generates the detected value of the second rotation angle θ2. The second rotation angle θ2 is a value indicating how many radians is one period (2π radians), which is an angle obtained by dividing one rotation of the rotation axis α into N equal parts. First and second rotation angles θ, θ
2 is given to a control device 6O, and a drive device (not shown) for the rotation axis α is controlled by the control device 60.

Note that the first signal processing circuit 30 is a conventionally used circuit, and the present invention is applied to the second signal processing circuit 40.

B. Configuration and operation of the first signal processing circuit The principle of signal processing in the first signal processing circuit 30 is as follows.

The two-phase output signal e1AeLB of the first encoder 10 is
It is expressed as follows.

e = k sinθ1・(1,)1, A
le = k cos θt-(2) IB
L Here, k: Constant θ1: Rotation angle of rotation axis α Meanwhile, within the signal processing circuit 30, two other reference sine waves si
nφ and COSφ( are generated, and the following multiplication is performed with the two-phase output signal e e described in 1).

IA'' (B E-e ・ cosφI IA IA = k sinθ cosφ =・(3)
L 1 1 E =e sinφI LB IB −Ic cosθ l51nφ −=(4)i
t t Furthermore, the difference ΔE11 between the two multiplication results E and E
, find A ID.

ΔE1. ``''EIA-01B = k sin (θ - φi)... (5) 1 In equation (5), if the angle φ1 that makes ΔE1-0 is found, the following is obtained.

φ1-01...(6a)
Or φ(紫θt+π...(6b
) However, both angles θ and φ1 are assumed to take values between O and 2π.

The signal processing circuit 30 changes the reference angle φ 2 as a variable parameter to find a reference angle φ 2 such that ΔE1=0, and outputs this reference angle φ1 as a detected value of the rotation angle θ1. Note that equation (6a) always holds true and φ1=
01, the rotation angle θ1 of the rotation axis α is set to 0.
When the angle φl is 0, adjustment is made to set the angle φl to 00 (this will be described later).

FIG. 3 is a block diagram showing the internal configuration of the first signal processing circuit 30. In the figure, the signal processing circuit 30 has two multiplication circuits 31a and 31b, and receives a two-phase signal el^ from the first encoder.

eIB is given to each. Also two multiplier circuits 3
1. a, 31. The digital values of the sine waves eO3φ and sinφI are respectively given to b from the ROMs 32a and 32b, and multiplication of the above equations (3) and (4) is performed. The multiplication results E and E are obtained by the multiplication circuit 311A.
It is applied from iB a, 31b to the subtraction circuit 33, and the subtraction of the above equation (5) is performed. The subtraction result ΔE1 is provided from the subtraction circuit 35 to the comparator 34, and it is determined whether ΔE=0. When ΔE1=0, the output signal ScI of the comparator 34 rises (or falls).

For example, when the value of the subtraction result ΔE changes from positive to negative, the output signal S is generated. 1 goes high and rises to the bell, while when it goes from negative to positive, it falls to the low level. The up/down counter 35 receives the output signal S from the comparator 34. 1, signal S
When the signal S is at H level, a countdown is performed to decrease the value of the reference angle φ1, while the signal S
When is at the L level, a count-up is performed to increase the value l of the reference angle φ1. The reference angle φ1 output from the Ara 1 down counter 35 is
These are given as addresses of the ROMs 32a and 32b, respectively. Output signal S of comparator 34. l is also given to the zero-cross pulse generation circuit 36. The zero cross pulse generation circuit 36 generates a signal S. The rising edge of 1 is detected and the latch gate i/control signal SLl is generated. The latch gate 1/control signal SL1 is applied from the zero-cross pulse generation circuit 36 to the latch circuit 37. The latch circuit 37 is given the angle φl output from the up/down counter 35 as input data, and when the latch gate control signal S1.1 rises to H level, it latches the value of the reference angle φ1 and uses it as input data. It is output as a detected value of rotation angle θ1. Note that the latch gate control signal S is sent as a busy signal B1 to the signal processing circuits 1, . 130 to the control device 60 (see FIG. 1). During the period when the latch circuit 37 is rewriting data (the period when the signal SLl is at H level), the control device 60
is prohibited from reading the value of rotation angle θ1 from the latch circuit 39.

f; and f FIG. 4 is a timing chart showing the operation of the signal processing circuit 30. At time t1o, the value of the subtraction result (hereinafter referred to as "difference") ΔE1 is positive, so the comparator 34
output signal S. l is kept at Llehe/l/. And this signal S. ■Up-down counter 35 received
is counting down the reference angle φ1. In FIG. 4, it is assumed that the counter 35 outputs the reference angle φ1 as an 8-bit digital value, and the value of the reference angle φ1 is shown in hexadecimal notation. When the value of the reference angle φI is counted down and reaches 0E (1, hexadecimal number), time t
The difference ΔE1 becomes zero. Then, 1 the output signal S of the comparator 34. I stands up. Zero cross pulse generation circuit 36 receives signal S. 1 is detected, and the output signal S1,1 is raised to H level for a short period of time. As a result, the latch circuit 37 which receives the signal SLL as a latch signal outputs the value of the reference angle φ=OE as the detected value of the rotation angle θ1. On the other hand, the signal S is generated at time t11. 1 rises to H level, up/down counter 3
5 is a reference angle. 4 Count up the value of φI. Then, at time t12, when the value of angle φ1 becomes OF, signal S is generated. 1 falls. Thereafter, the up/down counter 37 repeats counting down and counting up, and the signal S is output. 1 rises to the H level, the data in the latch circuit 37 is rewritten, and the data becomes the rotation angle θl.
is output as the detected value.

In addition, in Fig. 4, the value of the rotation angle θ1 of the rotation axis α is a constant value (
=OE), but even if the rotation angle θ1 changes over time, the value of the rotation angle θ1 at each time point is determined and outputted following this change.

When the value of the difference ΔE1 is zero, the reference angle φ1 and the rotation angle θ
1, the relationship of equation (6a) or equation (6b) is established. However, what we want to find is the relationship expressed by equation (6a).

Therefore, when starting up the control system shown in FIG. 1, the rotation angle θ1 of the rotation axis α is set to 00, and the latch circuit
is cleared by the clear signal CL, (see Figure 3),
The detected value of the rotation angle θ1, which is the output from the latch circuit 37, is adjusted to 0°. If the initial adjustment is performed in this way, the value will be applied to the signal processing circuit 3 following the change in the rotation angle θ1.
0, so the relationship in equation (6a) is always maintained.

FIG. 5 is a block diagram showing the internal configuration of the second signal processing circuit 40. This signal processing circuit 40 is a multiplication circuit 4
], a, 4 l b, ROM42. Subtraction circuit 43. Comparator 44. Up/down counter 45. It has a zero-cross pulse generation circuit 46 and a three-step latch circuit 47, and these components have the same functions as the components in FIG. However, the ROM 42 has the functions of the two ROMs 32 a and 32 b shown in FIG. 3, and has two reference sine waves sinφ and COSφ
Data representing 2 is outputted alternately in a time-sharing manner. That is, the reference angle φ2 is stored in the upper half of the address of the ROM 42.
The value of the reference sine wave sinφ2 for is stored,
1) The value of the reference cosine wave eosφ2 is stored in the lower half. Then, according to the selection signal MSB applied from the timing generation circuit 48 to the ROM 42, sinφ and co
The value of sφ2 is alternately outputted from the ROM 42. This selection signal MSB specifies the most significant bit of the address of the ROM 42. On the other hand, the lower bit of the address of the ROM 42 is the angle φ2 given from the up/down counter 45.
specified by.

The second signal processing circuit 40 further includes reference sine wave data s.
1nφ, correction value f for correcting COSφ2
, f is provided. Similarly to the ROM 42, the RAM 49 also stores the correction value f1 for the reference sine wave data sinφ2 in the upper half of the address, and the reference cosine wave data COSφ in the lower half.
A correction value f2 for is stored. Then, according to the selection signal MSB given from the timing generation circuit 48, the correction values f1 and f2 are outputted alternately. The reference sine wave data sinφ2°COSφ2 is added to the respective correction values f and f2 in the adder circuit 50, and the addition results (sinφ2+f) and (cosφ2+12) are added to the multiplication circuit 4]b.

41a, respectively.

The above addition result (sinφ2+f,), (cosφ2
+ f 2 ) are given to the multiplication circuits 41b, 4] and H, respectively, and the sine wave output signal e of the second encoder 20 is
Multiplication with e is performed. Multiplier circuit 2B'
2A Multiplication results E and E in 41a and 41b are subtraction port 2
The difference ΔE("' E2A "'
2B) is calculated. Then, similarly to the signal processing circuit 30 of FIG. 3, the comparator 44. Up/down counter 45. By the action of the zero cross pulse generation circuit 46 and the latch circuit 47, a reference angle φ2 that becomes φ2−〇 is obtained, and this is used as the detected value of the rotation angle θ2.
from the latch circuit 47 to the control device 6 via the data bus 51.
Output to 0.

In the second signal processing circuit 40, the up/down counter 45 and the ROM 42 mainly constitute the reference sine wave signal generating means in the present invention. Also, R.A.
M49 constitutes an 8-stage correction data generator, and the adder circuit 50 constitutes a correction means.

Furthermore, multiplication circuits 41a and 41b constitute multiplication means. Further, the subtraction circuit 43. Comparator 44, zero cross pulse generation circuit 46. The latch circuit 47 and the like constitute the detection means.

C-3, Calculation of correction value Correction values f, f2 ( is calculated, for example, as follows.

First, the two-phase output signal e2A"2 of the second encoder 20
Record B on some recording device. These two-phase output signals e e are not accurate sine waves or cosine waves as shown in FIG. 2(b), but contain errors, and can be expressed as follows.

e −k sinθ +a (θl) ・
-(7a)2^ 2゛2 e -k cosθ +b (θ, )
-(7b)2B 2 2 Here, a(θ) and b(θ1) are deviation amounts from an accurate sine wave, and are dependent on the rotation angle θ1.

Multiplication result E2AE2B in multiplication circuits 41a and 41b
should be as follows:

E −e ・(cosφ 10f2 (θ1))2A
2A 2-(k
sjnθ2+a(θ1〉)x (cosφ 10f2 (
θi, )) −(8a)E = e ・(sin
φ2+f1 (θ1))28 2B = (k eosθ2+b (θ())X (si
nφ +f1 (θ1)) −(81)) Correction value f
, f may be determined so that the value of ΔE (=E2A−E2B) becomes zero when θ2=φ2 holds. At this time, since E2A=E2+3, the following equation holds true.

(k sin θ2+a (θ1))X (cos
φ2+f2 (θ()) ””(k cosθ +b (θ1)) 2
B, the error a(θ,) corresponding to the value of the rotation angle θ1
, b(θ1) are known. Therefore, in equation (9), there are only two unknowns: the correction value f and (θ1)f (θ1). A correction value f (
θ ), f2 (0,1) set 1 ] 9 There are infinite combinations, but the multiplication circuit 41 . The correction values f (θ ) and f2 (θ1) may be appropriately determined by taking into consideration the accuracy of calculations in a, 41b and the subtraction circuit 43, respectively.

C-3, Writing operation of correction values Writing of correction values f and f2 to the RAM 52 is performed as follows. First, the levels of various control signals (see FIG. 1) given from the control device 10 to the signal processing circuit 40 are as follows.

Latch enable signal LE-H... (tea,) inhibit signal IN N=HI or otherwise. (10b) Buffer enable signal BE-H, (10c) Write control signal WR-H, (lod) Latch enable signal LE enables the 3-step latch circuit 47 via the inverter 55. input to the terminal. Therefore,
If LE-H, (LE=L), the three-step latch circuit 47 becomes high impedance, and the angle data φ2 given from the up/down counter 45 to the latch circuit 47 is not outputted to the outside. Further, the off-catch enable signal LE is also applied to the enable terminal of the 3-state buffer 53 as it is.

Therefore, when LE-Hl, this 3-state buffer 5
6 operates as a normal buffer and receives correction values f and f given from the control device 60 via the data bus 51.
is transmitted to the RAM data bus 101. Buffer enable signal BE is input to the enable terminal of 3-state buffer 54.

Therefore, when BE=H, the 3-state buffer 54 transmits the rotation angle θ1 given from the outside to the address bus 102 of the RAM. Note that at this time, the switch circuit 70 in FIG. 1 has been switched to the control device 60 side, and the RAM 5
The data of the rotation angle θ as address 2 is the correction value f
, f and 1 1, 2 are supplied from the control device 60 to the signal processing circuit 40 . Buffer enable signal BE is also input to the enable terminal of 3-state buffer 56 via inverter 55 at the same time. Therefore, if BE-H, (BE-L), 3-state buffer]
0 gate 56 becomes high impedance, and the address (angle φ2) applied from up/down counter 45 to RAM 49 via 3-state buffer 56 and address bus 102 is cut off. Write control signal WR is R
The signal is input directly to the write control terminal of the AM 49, and is also inverted via the inverter 57 and input to the read control terminal of the RAM 49. If WR=H, then
Correction values f , f given via data bus 101
is written into the RAM 49 according to the address θ1 given via the 2-address bus 102. Note that when the write control signal WR is set to L level, the correction values f 1 and f stored in the RAM 49 are transferred to the data 2 bus 101. ．． 3-state buffer 53. and is read out to the control device 60 via the data bus 51.

C-41 Rotation Angle Detection Operation The levels of each control signal applied from the control device 60 to the signal processing circuit 40 when detecting the rotation angle θ2 are as follows.

Latch enable signal L E = Lo...(
lla) Inhibit signal I H=H, or L...
(llb)] 0 Buffer enable signal BE-H...(+, lc) Write control signal WR-L. ...(lid)L
Since E-L (LE-H,), the 3-state latch circuit 47 becomes active, while the 3-state buffer 5
3 is in a high impedance state.

Also, since BE=H, the 3-state buffer 54.5
6 are in the active state and high impedance state, respectively. Furthermore, since it is WR-L, writing to the RAM 49 is prohibited and reading from the RAM 49 is enabled.

As a result of each control signal being applied as described above, the signal processing circuit 40 shown in FIG. 5 becomes equivalent to the circuit 40a shown in FIG. 6A.

The circuit 40a in FIG. 6A is almost equivalent to the first signal processing circuit 30 shown in FIG. 3 plus a RAM 49 and an adder circuit 5o.

FIG. 7 shows the signal processing circuit 4 when detecting the rotation angle θ2.
4 is a timing chart showing the operation of 0 (40a).

Rotation angle θ1 detected by the first signal processing circuit 3o
The data is periodically given to the RAM 49 via the address bus 102.

3. As shown in FIG. 7, when the rotation angle θ1 is supplied periodically, the reference timing signal S is simultaneously supplied from the first signal processing circuit 30 to the second signal processing circuit 40,
As shown in Figure A, the timing generation circuit 48 is manually operated. The timing generation circuit 48 generates a reference timing signal S
Based on the multiplication circuit 41. A timing signal 548 (see FIG. 7) for synchronizing the timings of ROM 42 and RAM 49 is generated. Of this timing signal S48, the selection signal MSB is given to the ROM 42, and the data DRoM of the reference sine waves sinθ and cosφ2 stored in the ROM 42 are periodically and alternately read out in accordance with this selection signal MSB. . The cycle of the selection signal MSB is the same as the cycle in which the reference angle φ2 manually entered from the up/down counter 45 to the address of the ROM 42 is updated. That is, the reference angle φ2 is 1
．． While this value is held, the selection signal MSB alternately takes the values "]" and "0" once each. When the value of the selection signal MSB is “1”, the data DR read from the ROM 42
oM is sinφ2, and the value of the selection signal MSB is “0”
At this time, the data DRoM read from the ROM 42 is a
osφ2. The selection signal MSB is also given to the RAM 49, and when the value of the selection signal MSB is "1", the RAM 49
The data D read from the RAM 49 is the correction value f1, and the data D read from the RAM 49 when the AM value of the selection signal MSB is "0".
is the correction value f2. As can be seen from FIG.
RAM synchronously and simultaneously provided to the adder circuit 50.

The result added by the addition circuit 50 is processed by the multiplication circuits 41a and 41b as follows. FIG. 6B is a block diagram showing the internal configuration of multiplication circuits 41a and 41b.

The multiplication circuits 41a and 41b both have two registers 411.
, 41.2, and a multiplier 413. The first register 411 is given the addition result from the adder circuit 50, and the addition result 1 (sfnφ2 + f t ) ( or (cosφ2+
f2)) is stored in the first register 411 as data Db1 (or
() (see Figure 7). No. 41
The data D, 1 (or Da□) written to 1 is written to the second register 412 in response to the register control signal S 2 applied from the timing generation circuit 48 to the second register 412. When data is written to the second register 412, the multiplier 413 writes the data to the second register 412.
The data D (or 2) is multiplied by the sine wave signal e2B (or e2^) given from the 22nd encoder 20, and the multiplication result E2B (or E2
A) (Figure 7n is not shown). As can be seen from FIGS. 6A and 7, the register control signal S given to the second register 412 is commonly given to the two multiplier circuits 41.a and 41b, and the register control signal S given to the second register 412 is The writing of data D, 2°Db2 and the output of the multiplication results are performed by two multiplication circuits 41a,
4.1b at the same timing. The subsequent operation is the same as that of the first signal processing circuit 30. That is, the difference ΔE (=
E2^-E2B), the comparator 44 causes the up/down counter 45 to count up or down.

As a result, the reference angle φ2 equal to the rotation angle θ2
The value of is detected and supplied from the latch circuit 47 to the control device 60 as the detected value of the rotation angle θ2.

Note that the inhibit signal IN becomes an L level when the control device 60 is reading the value of the rotation angle θ2 from the latch circuit 47, and prohibits rewriting of data in the latch circuit 47. That is, when the inhibit signal IN goes to the L level and is applied to the AND circuit 59, the latch gate control signals S1 and S2 in which the zero-cross pulse generation signal 46 is generated are blocked by the AND circuit 59 and sent back to the latch circuit 47. It disappears. Therefore, the control device 60 controls the rotation angle θ
This avoids the inconvenience that the data held in the latch circuit 47 is rewritten while the data 2 is being read from the latch circuit 47.

In this way, when detecting the rotation angle θ2 of the second encoder 20, the rotation angle θ1 detected by the seventh encoder 10 for absolute position detection is used, and the correction value fi (θ1 ).

Since the correction is performed using f (θ1), the sine wave two-phase output signal e2A of the second encoder 20.

Even if e2B is not a precise sine wave, the rotation angle θ2 can be detected with high precision.

D. Modifications The present invention is not limited to the above embodiments, and the following modifications are also possible.

(2) As the first signal processing circuit 30 for detecting the rotation angle θ1 of the first encoder 10, a circuit having the same configuration as the second signal processing circuit 40 may be used. At this time, the levels of each control signal given from the control device 60 when detecting the rotation angle θ1 are as follows.

Latch enable signal LE-L (12a
) inhibit signal I H-H, or. ...(12
b) Buffer enable signal BE-L...(1
2c) Write control signal WR-L. ...(L
2d) In this case, the signal processing circuit 40 of FIG. 5 becomes equivalent to the circuit 40b of FIG. 8. However, in the circuit 40 of FIG. 5, the portion indicated by angles θ and φ2 is
In the figure, the angles θ and φ are rewritten as] 1.

As can be seen from FIG. 8, the data of the reference angle φ2 outputted from the up/down counter 45 is also used to specify the address of the RAM 49. In this way, the two-phase output signal e of the first encoder]0,
Even if e is a precise sine wave or deviates from IALB, the correction value f according to the rotation angle θ1
, f using multiplication results E , E and subtraction 1,
1 1. A IB calculation result Δ
By correcting E1, the rotation angle θ1 can be detected with high accuracy.

Note that if the rotation angle θ1 can be detected with sufficiently high accuracy as described above, the second encoder 20 and its signal processing circuit 40 are unnecessary.

■ The error of the encoder's sinusoidal output signal may depend not only on the rotation angle but also on other parameters such as the encoder's environmental temperature. In this case, the correction value f,
f may be obtained as data dependent on various parameters such as the rotation angle θ1 and the environmental temperature 2 degrees, and stored in the RAM 49. And RAM4
9 address may be specified by the parameter.

■ The correction values f and f2 are stored in the RAM 49, but they can also be stored in a non-volatile memory (for example, a PROM).
), the data of the correction values f and f2 will be saved even if the power to the signal processing circuit is turned off. Therefore,
There is an advantage that it is not necessary to write the correction values f 1 and f 2 into the memory every time the power supply is turned on and off.

(2) Although the reference sine wave data is corrected by adding it to a correction value, the correction may be performed using other four arithmetic operations.

(2) Although the above embodiment is directed to a rotary encoder, the present invention may be applied to a linear encoder, and any signal processing circuit for an encoder that generates a sine wave two-phase signal can be applied.

(Effects of the Invention) As explained above, in this invention, the relative position of the movable part is detected based on the corrected reference signal obtained by correcting the reference sine wave signal, so that the sine wave signal from the encoder is converted into an ideal sine wave. There is an effect that the relative position of the movable part can be accurately determined even when the movable part deviates from the position shown in FIG.

Note that if the amount of deviation of the sine wave signal from the encoder from the ideal iE sine wave changes depending on the value of the relative position, the correction data generation means should generate correction data according to the low position. Accurate relative position detection is possible.

Moreover, when the amount of deviation changes according to the second parameter, if the correction data generating means generates the correction data according to the parameter of the second clause, accurate relative position detection is possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a control system to which an embodiment of the present invention is applied. FIG. 2 is a diagram showing the waveform of a sine wave output signal of an encoder. FIG. 3 is a diagram showing a first signal processing circuit. 4 is a timing chart showing the operation of the first signal processing circuit, FIG. 5 is a block diagram showing the structure of the second signal processing circuit, and FIG. 6A is a timing chart showing the operation of the first signal processing circuit. FIG. 6B is a block diagram showing the internal configuration of the multiplication circuit; FIG. 7 is a timing chart showing the operation of the second signal processing circuit; FIG. The figure is a block diagram showing an equivalent circuit during another operation of the second signal processing circuit. 1.0.20... Encoder, 41a, 41b... Multiplication circuit, 42... ROM, 43... Subtraction circuit, 44... Comparator, 45... Up/down counter, 46... Zero cross pulse generation circuit, 47...Latch circuit, 4...RAM. 3 50...Addition circuit, e2A'e2'...Sine wave signal, sinφ, cosφ2...Reference sine wave, θ1.θ2...Rotation angle, φ2...Reference angle, fl, f2... Correction value

Claims (2)

[Claims] (1) Detecting the relative position by receiving first and second sine wave signals of different phases that include the relative position of the movable part with respect to the fixed part as a phase variable from an encoder attached to a predetermined movable part. This is a signal processing circuit for an encoder, which changes a temporary position as a variable parameter over time, and converts the temporary position as a phase variable into a signal having an ideal sinusoidal waveform. a reference sine wave signal generating means for generating a second reference sine wave signal; correction data generating means that stores first and second correction data corresponding to the temporary position, and generates the first and second correction data, respectively, according to the temporary position; a correction means for generating first and second corrected reference signals by correcting a second reference sine wave signal with the first and second correction data, respectively; and a correction means for generating first and second corrected reference signals; multiplication means for generating first and second multiplied signals by multiplying by the first and second sine wave signals, respectively; and determining a difference between the first and second multiplied signals;
1. A signal processing circuit for an encoder, comprising: detecting means for generating the tentative position as a detected value of the relative position when the difference is equal to a predetermined reference difference value. (2) Detecting the relative position by receiving first and second sine wave signals of different phases that include the relative position of the movable part with respect to the fixed part as a phase variable from an encoder attached to a predetermined movable part. This is a signal processing circuit of an encoder for changing a temporary position as a first parameter over time, and converting a first out-of-phase signal into a signal having an ideal sinusoidal waveform with the temporary position as a phase variable. and a reference sine wave signal generating means for generating a second reference sine wave signal; and a reference sine wave signal generating means for generating a second reference sine wave signal, based on a deviation from an ideal sine wave waveform of the first and second sine wave signals, which varies according to a second parameter. A correction data generator that stores first and second correction data obtained in advance in accordance with the second parameter, and generates the first and second correction data respectively in accordance with the second parameter. correcting means for generating first and second corrected reference signals by correcting the first and second reference sine wave signals with the first and second correction data, respectively; and a second correction reference signal, respectively, to generate first and second multiplied signals by multiplying the first and second sine wave signals; Find the difference,
1. A signal processing circuit for an encoder, comprising: detecting means for generating the tentative position as a detected value of the relative position when the difference is equal to a predetermined reference difference value.