JPH0381117B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a reset circuit for a rechargeable electronic timepiece having a primary power source and a secondary power source. [Summary of the Invention] The present invention provides a rechargeable electronic watch that is driven by a primary power source and a secondary power source, and includes a voltage detecting means and a frequency divider that detect the voltage of the secondary power source even when the step motor is stopped by operating the crown or the like. By eliminating the need to reset the device, charging and discharging operations can be performed even when the step motor is stopped. [Prior Art] Fig. 4 shows an example of a conventional charging/discharging system for a rechargeable electronic watch having a primary power source and a secondary power source. The charging/discharging system in this example includes a solar cell 19 serving as a primary power source, capacitors 20 (hereinafter referred to as C1) and 21 (hereinafter referred to as C2) serving as a secondary power source, and switch means 22 (hereinafter referred to as S1), 23 (hereinafter referred to as S2), 24 (hereinafter referred to as S3), and backflow prevention diodes 25, 26. First, the charging/discharging operation will be explained. The state shown in (1) is called the immediate start state and the solar cell 19 charges the capacitor C2. Since the capacitors C1 and C2 have the relationship C1>>C2, the capacitor C2 is quickly charged.
Also, in this state, the switch means S1, S2, S3
Both are in the OFF state. The state shown in (2) is called the capacitor C1 charging state, and since the switch means S2 of the solar cell 19 is in the ON state, the capacitor C1 is charged. The transition condition from state (1) to state (2) is VDD−
If the voltage at which the circuit means connected between VSS can operate sufficiently is -VOP1, then -VOP1<VSS
becomes. Conversely, the transition condition from state (2) to state (1) is
Letting the lowest operating voltage of the circuit means be -VSTP, define the voltage -VOP2 such that -VSTP>-VOP2>-VOP1, and -VOP2
<VSS. The state shown in (3) is called the capacitor C1 charge completion state, and the switch means S1 and S2 are turned on, and the circuit means operates with the capacitor C1. The transition condition from state (2) to state (3) is −VOP
1>VC1. When the solar cell 19 is no longer exposed to light in this state, the capacitor C1 starts to discharge, and when the condition -VSTP<VC1 is reached, the state changes from state (3) to state (1) and the circuit means stops. The state shown in (4) is called an overcharge prevention state, and switch means S1, S2, and S3 are all turned on, and by shooting both ends of the solar cell 19, overcharging of the capacitor C1 is prevented. Here, if the withstand voltage of capacitor C1 is -VFUL,
It is assumed that a transition is made from state (3) to state (4) under the condition of -VFUL>VC1, and vice versa from state (4) to state (3) under the condition of -VFUL<VC1. By transitioning from state (1) to state (4) as described above, charging and discharging can be repeated. FIG. 5 shows an embodiment of the voltage detection means 4 and the switch means 6 for enabling the state transition of the charging/discharging system shown in FIG. The voltage detection means 4 includes voltage detection circuits 27, 28,
29, 30, 31, and a control circuit, and the switch means 6 includes MOS transistors 22, 23,
It consists of 24. Next, the voltage detection operation and switch operation will be explained. The voltage detection circuit 27 detects -VSTP of VC1, and when -VSTP<VC1, the output of the voltage detection circuit 27 becomes "L", and the NOR gate 3
The latch composed of 3 and 34 and the latch composed of NOR gates 39 and 40 are reset.
This is to turn off S1 of No. 2 and S2 of No. 23. This operation changes from state (3) to state (1) shown in Figure 4.
It means a transition to. The voltage detection circuit 28 detects -VOP2 of VSS, and when -VOP2<VSS, the output of the voltage detection circuit 28 becomes "L", and the NOR gate 39,
Reset the latch consisting of 40 and set the S of 23.
Turn 2 off. This operation means a transition from state (2) to state (1) shown in FIG. However, in state (3), the output of NOR gate 33 is “H”
Therefore, the OFF operation of S2 in 23 is not performed. The voltage detection circuit 29 detects -VOP1 of VSS, and when -VOP1>VSS, the output of the voltage detection circuit 29 becomes "H", and the NOR gate 39,
Set the latch consisting of 40, S2 of 23
is in NO state. This operation is in the state shown in Figure 4.
It means a transition from state (1) to state (2). The voltage detection circuit 30 detects -VOP1 of VC1. When -VOP1>VC1, the output of the voltage detection circuit 30 becomes "H" and the NOR gate 3
The latch consisting of 3 and 34 is set, and S1 of 22 is turned on. This operation means a transition from state (2) to state (3) shown in FIG. The voltage detection circuit 31 detects -VFUL of VC1, and when -VFUL>VC1, the output of the voltage detection circuit 31 becomes "H", turning on S3 of 24, and conversely, when -VFUL<VC1 24 S3
Turn off. This operation means a transition from state (3) to state (4) shown in FIG. 4, or vice versa. FIG. 6 shows an example of a conventional reset circuit. When an external mechanical restriction is applied, reset terminal 44 becomes "H" and this data is transferred to flip-flop 4.
When the output of the flip-flop 50 becomes "H", the frequency divider and pulse synthesis circuit are reset. [Problem to be solved by the invention] When a charging/discharging system as described above and a reset circuit are combined, the frequency divider is reset at the time of reset, so that the pulse should be output from the pulse synthesis circuit 3 shown in Fig. 5. SP1, SP2, SP3, SP4
Since the clock stops, the voltage detection means 4 will no longer function. Therefore, at the time of resetting, there are the following drawbacks. (1) If the capacitors C1 and C2 are charged in the states (2) and (3) shown in FIG. 4, they will be overcharged, which may cause deterioration or destruction of the capacitors C1 and C2. (2) If the battery is discharged in the states (2), (3), and (4) shown in Figure 4, the switch means 6 will stop operating without being controlled to the OFF state. ), the operation may not start. (3) In order to eliminate the problem in (1) above, if a Zener diode is placed in parallel with the primary battery to prevent overcharging, leakage current will flow through the Zener diode at times other than overcharging, which will reduce the charging efficiency of the primary power supply. It ends up making things look worse. [Means for Solving the Problems] The present invention has been made to eliminate the above problems, and in the reset state, at least the drive circuit of the step motor is reset and the frequency divider is reset. The second reset circuit resets the frequency divider at least for a short time immediately after the reset is released. [Function] By providing the reset circuit as described above,
The conventional charging/discharging system can be used as is, and normal charging/discharging operations can now be performed even in the reset state. [Example] Hereinafter, an example of the present invention will be described based on the drawings. FIG. 1 is a block diagram of a rechargeable electronic watch circuit according to the present invention, in which 1 is an oscillator, 2 is a frequency divider that divides the output of oscillator 1, and 3 is a pulse synthesizer that synthesizes pulses with the output of frequency divider 2. 4 is a voltage detection means that detects the voltage of the secondary power supply using the output of the pulse synthesis circuit 3; 5 is a step motor drive circuit that drives the step motor using the output of the pulse synthesis circuit 3; 7 is a frequency division circuit that uses the output of the pulse synthesis circuit 3 to drive the step motor; A second reset circuit 8 is used to reset the motor 2 for a short time, and a first reset circuit 8 is used to stop the motor drive signal when in the reset state. FIG. 2 shows a specific embodiment of the above-mentioned reset circuit (1) and reset circuit (2), and FIG. 3 is a timing chart thereof. As explained in the conventional reset circuit, when the reset circuit (1) of No. 8 enters the reset state, the reset terminal 9 becomes "H" and the flip-flops 13, 14,
Data is read through a chattering prevention circuit comprised of 15. As shown in Figure 3, the shortest reading time is 5.86 msec and the longest reading time is 9.77 msec. The output of flip-flop 15 is “H”
As a result, the step motor drive circuit 5 is reset and the step motor drive signal is stopped. Since this method can be sufficiently constructed using conventional techniques, it will be omitted here. As described above, since the reset circuit (1) of 8 does not reset at least the frequency divider 2, the voltage detection means 4 functions as usual. Next, the reset circuit (2) of 7 is the length after the reset is released.
A circuit for creating a 0.49 msec one-shot pulse, consisting of flip-flop 16, latch 17, and NOR.
It consists of a gate 18. As shown in the timing chart in FIG. 3, a one-shot pulse is output 0.98 msec at most immediately after the reset is released. This one-shot pulse is used to reset the frequency dividing stage from 512Hz onwards, and after about 1 second it acts to output the step motor drive waveform. The method for resetting the frequency division stage after 512 Hz can be sufficiently configured using conventional techniques, so the description thereof will be omitted. [Effects of the Invention] As described above, by providing the first reset circuit and the second reset circuit according to the present invention, charging and charging can be performed regardless of whether the battery is reset or not, and without adding any other elements. Discharge operation became possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a rechargeable electronic timepiece circuit according to the present invention, FIG. 2 is a diagram showing an embodiment of a reset circuit according to the present invention, FIG. 3 is a timing chart of the reset circuit, and FIG. 4 is a diagram of a conventional solar cell. FIG. 5 is a diagram of a charging/discharging system using a capacitor and a capacitor, FIG. 5 is an embodiment of voltage detecting means and switching means, and FIG. 6 is a conventional reset circuit diagram. DESCRIPTION OF SYMBOLS 1... Oscillator, 2... Frequency divider, 3... Pulse synthesis circuit, 4... Voltage detection means, 5... Step motor drive circuit, 6... Switch means, 7... Reset circuit (2), 8 ...Reset circuit (1), 9...Reset terminal, 10...NAND gate, 11, 12
...Inverter, 13, 14, 15, 16...Flip-flop, 17...Latch, 18...
NOR gate, 19... solar cell, 20, 21...
... Capacitor, 22, 23, 24 ... Switch means, 25, 26 ... Backflow prevention diode, 27,
28, 29, 30, 31... Voltage detection circuit, 3
2, 37, 38, 41, 42, 43...Inverter, 33, 34, 39, 40...NOR gate,
35...OR gate, 36...NAND gate, 4
4...Reset terminal, 45...NAND gate,
46, 47... Inverter, 48, 49, 50...
…flipflop.

Claims (1)

[Scope of Claims] 1 A solar cell or a generator as a primary power source, a capacitor or a secondary battery as a secondary power source, and comprising circuit means connected in parallel to the primary power source and the secondary power source, the circuit means includes at least an oscillator, a frequency divider that divides the output of the oscillator, a pulse synthesis circuit that synthesizes pulses using the output of the frequency divider, and a step motor drive circuit that drives a step motor using the output of the pulse synthesis circuit. and a rechargeable electronic timepiece, which also has voltage detection means for detecting the voltage of the secondary power supply using the output of the pulse synthesis circuit, and switch means for switching between charging and discharging of the secondary power supply using the output of the voltage detection means. a first reset circuit that resets at least the step motor drive circuit and does not reset the oscillator and frequency divider when the step motor is stopped by external mechanical regulation;
A rechargeable electronic timepiece characterized in that a second reset circuit is provided for resetting at least the frequency divider for a short time immediately after the mechanical restriction is released. 2. The rechargeable electronic timepiece according to claim 1, wherein the external mechanical restriction is a crown operation. 3. In paragraph 1, the first reset circuit;
2. The rechargeable electronic timepiece according to claim 1, wherein the voltage detection means is not reset by the second reset circuit.