JPH0380544A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce collector resistance and collector parasitic capacitance, and realize an element capable of high speed operation, by arranging a collector region, an element isolation insulating film and a collector leading-out region on a substrate having step-difference on the surface, and connecting the collector region with the substrate surface under the step-difference. CONSTITUTION:A collector region 2, an element isolation insulating film 3 and a collector leading-out region 4 are formed on a p-Si substrate 1 having step-difference on the surface. The collector region 2 is composed of an n-Si epitaxial layer in contact with the substrate surface under the step-difference, and in the inside, a conductivity type emitter region 8 and an opposite conductivity type base region 6 are formed in order from the surface. The collector leading-out region 4 is composed of a high concentration N-type poly Si layer formed on the element isolation insulating film 3 under the step-difference so as to be in contact with the side surface of the collector region 2. Since, in this structure, a buried layer is not present, and the collector is directly led out from the side surface of the collector region 2, the collector resistance can be reduced. The collector leading-out region 4 exists on a thick insulating film, so that the collector parasitic capacitance is reduced, thereby realizing the high speed operation of an element.

Description

[Detailed description of the invention] 〔overview〕 Regarding a semiconductor device having a bipolar transistor.

We aim to improve the operating speed of bipolar transistors by proposing a new structure without buried regions.

A substrate with a step on its surface has a collector region, an element isolation insulating film, and a collector lead-out region. An emitter region of one conductivity type and a base region of an opposite conductivity type are formed, an element isolation insulating film is formed on the substrate surface along the step in contact with the periphery of the collector region, and a collector lead-out region is formed on the side surface of the collector region. The structure is made up of a semiconductor layer of one conductivity type formed on the element isolation insulating film in contact with and under the step.

[Industrial application field]

The present invention relates to a semiconductor device having a bipolar transistor.

Bipolar transistors are widely used as components of high speed integrated circuits.

[Conventional technology]

As is well known, the basic structure of a bipolar transistor is to form a highly doped buried region on a substrate, and then form a shrimp layer, which will become a collector region, over the entire surface of the substrate.

It has a structure in which a base region and an emitter region are sequentially formed in the shrimp layer above the buried region.

FIG. 3 is a sectional view of a conventional bipolar transistor.

In the figure, 21 is a p-type semiconductor substrate, 22 is an n1-type buried region with high impurity concentration, 23 is an n-type epitaxial layer forming a collector, 24 is a p-type element isolation region, 2
5 is a p-type impurity-introduced layer that forms the base, and 26 is n0.
A type impurity-introduced layer constitutes an emitter, 27 is an n3 type collector electrode extraction region, 28, 29, and 30 are conductive layers, each forming a collector, a base, and an ivy electrode, and 31 is a field. It is an insulating layer.

In a transistor having such a structure, in order to ensure an insulating distance between the base electrode 29 and the ivy electrode 30,
Base region 25 must be significantly larger than emitter region 26. However, the operating region that takes part in the transistor action is only the region immediately below the emitter region 26, and the other region is for drawing out the base electrode, and it is desirable that the size of the region be as small as possible.

Conventional bipolar transistors have disadvantages in that the operating area must be made larger than functionally necessary, which limits the degree of integration and further limits the operating speed.

In recent years, in response to demands for higher speed and higher integration of devices, various methods of extracting the base have been devised and many proposals have been made.

The collector is generally drawn out from the buried region to the substrate surface.

[Problem to be solved by the invention]

When a buried region is used to lead out the collector, the parasitic capacitance of the collector is large, and the collector resistance increases by the amount that passes through the buried region, which impairs device characteristics.

The present invention aims to improve the operating speed of bipolar transistors by proposing a new structure without buried regions.

[Means to solve the problem]

The above problem was solved on a substrate with steps on the surface.

It has a collector region, an element isolation insulating film, and a collector lead-out region, and the collector region is made of a one-conductivity type semiconductor layer connected to the substrate surface under the step, and one-conductivity type emitter region 2 is returned to the inside from the surface in order. A mold base region is formed, an element isolation insulating film is formed on the substrate surface along the step in contact with the periphery of the collector region, and a collector lead-out region is formed in contact with the side surface of the collector region to protect the elements below the step. This is achieved in a semiconductor device consisting of a semiconductor layer of one conductivity type formed on an isolation insulating film.

[Effect]

The present invention has no embedded region and draws out the collector directly from the side of the collector region, reducing collector resistance.
Furthermore, since the collector lead-out region is located on a thick isolation insulating film, the parasitic capacitance of the collector is reduced, thereby increasing the speed of the device.

〔Example〕

FIG. 1 is a partially sectional perspective view illustrating an embodiment of the present invention.

In the figure, l is a p-St substrate, IC is a channel cut region, 2 is a collector region with an n-3i bilayer, 3 is an element isolation insulating film and is a Si0g film, 4 is a collector lead-out region, 5 is an insulating film between the eyebrows, 6 is a p-type base region, 7 is an insulating film between the eyebrows, 8
is an n-type vine area, E is a vine electrode, B is a base electrode, and C is a collector electrode.

The structure of this embodiment is as follows.

A p-5i substrate 1 having a step on its surface has a collector region 2, an element isolation insulating film 3, and a collector lead-out region 4.

Collector region 2 is n-5t connected to the substrate surface under the step.
It consists of a vinyl layer, and inside thereof, a monarch ivy region 89 of one conductivity type and a base region 6 of the opposite conductivity type are formed sequentially from the surface.

The element isolation insulating film 3 is formed on the substrate surface in contact with the periphery of the collector region 2 and along the steps.

The collector lead-out region 4 is made of a highly concentrated n-type poly-Si layer formed on the element isolation insulating film 3 under the step in contact with the side surface of the collector region 2.

Next, the outline of the manufacturing process of the semiconductor device of the example will be explained.

FIGS. 2(1) to 2(6) are cross-sectional views illustrating the manufacturing process of the embodiment.

In FIG. 2 (1), there is an n-3i layer 2 with a thickness of 0.5 to 1.0 am on the entire surface of the p-Si substrate 1 and a layer 2 with a thickness of 50 am.
A SiOz film 21 is grown by chemical vapor deposition (CVD).

Next, steps (grooves) are formed on the surface of the substrate on which the shrimp layer 2 is laminated.

A groove 22 with a width of 1 to 2 μm is formed around the collector region of the shrimp layer 2.
form. The depth of the groove 22 is 7000 mm for the p-3i substrate.
It will be formed to hold 12,000 people.

The grooves are formed by first buttering the Sing film 21 to open the groove forming portions, and then performing reactive ion etching (RIE) using the opened SiO□ film 21 as a mask.

RIB is 1. For example, using CIZ gas in a parallel plate type device, the pressure is reduced to 0.1 Torr to 13.56 MH.
This is done by applying a power of 200 II per substrate.

The shrimp layer 2 inside the groove becomes the collector region.

In Fig. 2 (2), due to thermal oxidation, the inner surface of the groove has a thickness of 5 mm.
00 A pad SiO! A film 23 is formed, and boron ions (B+) are implanted through this layer to form a 6N region IC with a + type channel.

The implantation conditions for B1 are as follows: energy: 80 KeV; dose: 5×10'3 to 2×10"cm-".

In Fig. 2 (3), a 5izN4 film 2 with a thickness of 1000 mm is applied to the inner side surface of the groove 22 using 9 ordinary glue steps.
Express 4.

To form the film 24 of 5L3N only on the inner side surface of the groove 22, for example, the following procedure is performed.

First, Si3 was applied to the entire surface of the substrate, covering the inside of the groove (side and bottom surfaces).
A N4 film is grown in a vapor phase, and the 5iJa film on the substrate surface and the groove bottom is removed by anisotropic etching using RIE, leaving the Si, N, and N films on the inner and outer sides of the groove. Next, apply resist to the entire surface of the substrate, covering the inside of the groove, and apply 5t3N to only the inner side surface of the groove 22 using a normal glue soger coating.
Buttering is performed so that the a film 24 remains.

In FIG. 2(4), a Sing film 3 having a thickness of 4,000 to 5,000 wafers is formed by wet oxidation as an isolation insulating film using an oxidation-resistant mask of 4 types of Sl and Na films. On this occasion.

The 5iO1 film 3 is also formed on the collector region.

Next, Si3N film 24 and pad Si0g film 23
remove.

In FIG. 2 (5), an n-type polySt layer with a thickness of 7,000 to 12,000 layers is deposited over the entire surface of the substrate, etched back, and a collector lead-out region 4 made of n+-type polySt is formed in the groove.
form. Here, doping with polySt may be performed after growth.

Next, a thermally oxidized 5iOz film 2 is applied to the surface of the collector lead-out region 4.
5 and then heat-treated to form the collector draw-out area 4.
Then, impurities are diffused into the collector region 2. the result,
The area inside the interface of the collector region 2 becomes n-type and serves to lower the contact resistance.

Next, thickness 4000-5000 people (7) CV D −
A SiOz film 26 is grown over the entire surface of the substrate.

In FIG. 2(6), the base region 6 is formed by opening the Sin films 26 and 3 on the collector region 2 and introducing p-type impurities.

Next, a base electrode B made of p-type poly-Si, a covering insulating film 261, and a SiO□ film 7 as an interlayer insulating film are sequentially formed in the opening.

For details of this process, see 9. For example, a p-type polySt layer for forming the base electrode B is formed on the entire surface of the substrate, covering the openings of the SiO□ films 26 and 3, and this is patterned to form the base electrode B. As a result, a covering insulating film 26 is grown over the entire surface of the substrate.

The coating insulating film 26 and the base electrode B in the emitter region forming portion are opened. A thermally oxidized SiO2 film 7 is formed on the surface of the base electrode B within the opening as an insulating film between the eyebrows. SiO inside the opening
□ An emitter electrode made of n-type poly-Si is formed via the film 7.

Next, impurities are diffused from the ivy electrode E to form an n+ type ivy region 8. Further, the emitter region 8 may be formed by ion implantation before forming the electrode.

With the above steps, the main part of the bipolar transistor is formed.

The embodiments can be applied in combination with other integrated circuit device formation processes.

〔Effect of the invention〕

As described above, according to the present invention, the operating speed of a bipolar transistor can be improved by using a novel structure that does not have a buried region.

For example, when the operating areas have the same dimensions.

A comparison between a conventional structure having a buried region and an embodiment without a buried region is as follows.

Conventional example Example Collector resistance (Ω) 84 Collector capacitance (pF/200 um”) 0.1
5 0.05-Speed (pS)
1.2 0.2

[Brief explanation of drawings]

FIG. 1 is a partially sectional perspective view illustrating an embodiment of the present invention. FIGS. 2(1) to 2(6) are cross-sectional views illustrating the manufacturing process of the embodiment. FIG. 3 is a sectional view of a conventional bipolar transistor. In fig. 1 is a p-3t substrate. IC is a channel cut area. 2 is the n-Si shrimp layer in the collector region. 3 is an element isolation insulating film, which is a Si0g film. 4 is the collector drawer area. Sen2ρb membrane. 6 is a p-type base region. 7 is the glabellar insulating membrane. 8 is the n-type industrial area. E is the emitter electrode, B is the base electrode. C is the collector electrode actual rejection 4P1 one ship F# surface deficiency ♀ 4-legged diagram 1st aFol○ color of 1 grain of grain] 20th (A-1) Example cross-sectional area depth 2 distribution/) 2)

Claims (1)

[Claims] A collector region (2) on a substrate (1) having a step on its surface.
, an element isolation insulating film (3), and a collector lead-out region (4), the collector region is made of a semiconductor layer of one conductivity type connected to the surface of the substrate under the step, and an emitter region of one conductivity type is formed inside the layer sequentially from the surface. (8), a base region (6) of the opposite conductivity type is formed, an element isolation insulating film is formed on the substrate surface along the step in contact with the periphery of the collector region, and a collector lead-out region is formed on the side surface of the collector region. 1. A semiconductor device comprising a semiconductor layer of one conductivity type formed on an element isolation insulating film in contact with and under a step.