JPH0379081A - Thin film transistor - Google Patents

Abstract

PURPOSE:To eliminate irregularity in ON current capacity by providing a pair of enlarged covering parts covering both a source film and a drain film as shape elements of a channel film and an equal width coupling part for coupling them, and exposing the superposed part of the coupling part only in a region along the inner edge of the source or drain film. CONSTITUTION:A channel film 14 is formed of a pair of right and left enlarged covering parts 12, 13, and an equal width coupling part 15 of a small width for coupling them. The part 15 is set to a narrower value than the difference between the length of opposed inner edges 2a, 3a of the films 2, 3 and the length of twice as long as the matching margin of the film 14 itself, and formed of superposed parts 15a, 15b superposed on the films 2, 3 and an effective channel part 15c extending to the intermediate between the parts 15a and 15b. On the other hand, the parts 12, 13 cover the outer steps 2b, 3b of the films 2, 3, but the small regions near the edges 2a, 3a are exposed. Thus, irregularity in ON current capacity due to the irregularity in the alignment accuracy can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor (TPT) with a staggered structure using polycrystalline silicon for a channel film, and specifically relates to an improvement in the planar shape of the channel film.

[Conventional technology]

Conventionally, the structure of a polycrystalline silicon thin film transistor with a staggered structure applied to TPT low-temperature process etc. is as shown in FIG. 5(a). A channel film 4 which is an undoped polycrystalline silicon film with an overlapping margin between the source film 2 and the drain film 3, and a channel film 4 on the channel film 4. A thin silicon oxide film 5, which is an insulating film in which a MOS (MIS) part is to be formed, and a gate electrode 6 made of N-type high concentration polycrystalline silicon, etc. are in conductive contact with the source film 2 and drain film 3 through contact holes. Aluminum source electrode 7 and pixel electrode (drain electrode) 8 as a transparent electrode
It is equipped with the following.

The channel film 4 is formed astride the source film 2 and the drain film 3 as shown in the fifth [ff1(b)], and its planar shape is similar to the opposing inner ends of the source film 2 or the drain film 3. It is narrower than the length W of the edge, and has a uniform cap shape with a narrow width dimension W. This means that even if mask misalignment occurs in the vertical direction in FIG. 5, the effective channel width of the formed channel inversion layer will always be the narrow width dimension W, taking into account mask misalignment of the channel film forming mask. This is to ensure that the on-resistance or on-current value varies.

On the other hand, the process to obtain the channel film 4 in a thin film transistor (TPT) having such a structure is first shown in FIG.
As shown in a), a phosphorus-doped polycrystalline silicon film is coated on a transparent insulating substrate 1 made of, for example, hard glass by low-pressure CVD or ion implantation, and then the film is phase-separated by buttering and etching. A source film 2 and a drain film 3 are then formed. Next, Fig. 6(b)
As shown in FIG. 6(C), after coating the entire surface of the source film 2 and drain film 3 with polycrystalline silicon 4', the source film 2 is coated with resist and buttered as shown in FIG. 6(C).
Then, a resist pattern 9 whose side surfaces are located on top of the drain film 3 is formed. Thereafter, as shown in FIG. 6(d), the exposed region of the polycrystalline silicon film 4' is removed by plasma etching using CF to expose the underlying source film 2 and drain film 3. As shown in Figure (e), a normal resist removal process (OX plasma.

Remove the resist pattern 9 with hot sulfuric acid) and remove the channel film 4.
get.

However, the thin polycrystalline silicon film 4' is made of CF.

Step of obtaining channel film 4 by plasma etching (
In FIG. 6(d), since it is necessary to leave the source film 2 and drain film 3, the plasma etching must be appropriately terminated in the middle of etching both films 2 and 3. Product (silicon fluoride compound) 1
0 adheres to the side surface of the resist 9, which serves as an etching mask.

This attached reaction product 10 is extremely difficult to remove even by the normal resist removal process (0! plasma, hot sulfuric acid) shown in FIG. This led to deterioration of transistor characteristics.

The following manufacturing method has been proposed as a measure to prevent surface contamination of the channel membrane 4 due to such reaction products.

First, as shown in FIG. 7(a), resist pattern 2
0 is formed on the source film 2 and drain film 3, and the side surface 20a of this resist pattern 20 is the outer step 2a of the source film 2 and drain film 3.

It is formed so as to completely cover both films 2.3 including up to 3a. Next, as shown in FIG. 7(b), plasma etching using CF is performed to remove the exposed region 4'a of the polycrystalline silicon film 4'. This plasma etching process does not end during the etching of the polycrystalline silicon film 4', but is continued until the surface of the substrate 1 is completely exposed, and then a slight overetch is performed. The silicon of the polycrystalline silicon film 4' reacts with CF a as an etchant, producing a reaction product that appears to be a silicon fluoride compound.
Plasma etching does not end during the etching of the exposed region 4'a of the polycrystalline silicon film 4', but over-etching is performed after the exposed region is completely removed, so the reaction products generated before then are wiped away. be done. therefore,
After over-etching, reaction products do not adhere to the side surfaces of the resist pattern 20.

Next, as shown in FIG. 7(C), a resist pattern 20
is removed by a conventional method (0, plasma, hot sulfuric acid) to obtain a channel film 4# having an outer step covering portion 4#a also on the outer steps 2a, 3a of the source film 2 and drain film 3. No residue of reaction products adheres to the surface of this channel film 4#, and a clean MOS interface is obtained. Therefore, the problem of deterioration of transistor characteristics due to MOS interface contamination is solved.

[Problem to be solved by the invention]

The cross-sectional structure of the thin film transistor manufactured in this way is shown in FIG. 8(a), and its planar structure is shown in FIG. 6(b), with the source film 2 and drain film 3 having no exposed areas. Since the channel film 4# covers the channel film 4#, a new problem occurs.

That is, due to variations in alignment accuracy of channel film 4#, channel film 4# may shift in the direction perpendicular to the effective channel length as shown in FIG. 9 from the normal position shown in FIG. 8(b). be. Here, if the width dimension of channel film 4# is W, and the protrusion width is dt, dz, then w,
Although the relational expression = W + dl + d2 always holds true, due to variations in alignment accuracy, the asymmetry of dl - Ihd -
For example, as shown in FIG. 9, dl
When the alignment is such that <dt, a bulging channel inversion layer is formed in the region 4'a of the protrusion width dt, and an electric field is concentrated at the corner edge of the source film 2 or drain film 3. As a result, variations in on-current capacity occur, leading to a decrease in the yield of thin film transistors.

The present invention solves the above-mentioned problems, and its object is to minimize the adhesion of reaction products to the channel film during patterning of the channel film itself by plasma etching by improving the planar shape of the channel film. To provide a thin film transistor in which there is no variation in effective channel length and effective channel width of a channel inversion layer, and there is no variation in on-current capacity, not only to prevent variation in alignment precision that inevitably occurs. It is in.

[Means to solve the problem]

In order to solve the above problems, the measures taken by the present invention include forming a channel inversion layer by integrally connecting a pair of enlarged covering parts that cover almost the entire source film and drain film during plasma etching. A polycrystalline silicon channel film consisting of a cap-shaped connecting portion is provided. The equicap-shaped connecting portion has an overlapping portion that overlaps and adheres to the source film or the drain film, and an effective channel portion that extends between these overlapping portions. The connecting enlarged covering portion covers, for example, only a region approximately corresponding to the length of the overlapping portion of opposing inner edges of the source film and the drain film other than the non-covered region. Another planar shape of the enlarged covering part is that in the above-mentioned non-covering area, a defective part is provided between the base and the overlapping part of the roots, and an overhanging covering part is provided to hide the corner part on the inner edge side. ing.

[Effect]

According to such a shape of the channel film, if variations in alignment accuracy occur in the direction perpendicular to the effective channel length direction, an equicap-like connection narrower than the length of the inner edge of the source film or drain film will occur. There is no variation in the effective channel width of the channel inversion layer formed depending on the region. In addition, if variations in alignment accuracy occur in the effective channel length direction, the inner edge of the enlarged covering part runs away from the inner edge of the source or drain film by the length of the overlapping part and does not protrude from it. , the formed channel inversion layer always has a uniform channel width in the effective channel length direction. Therefore, since the channel inversion layer always has an effective channel length, which is the distance between the source film and the drain film, and an effective channel width, which is the width dimension of the equicap-like connecting portion, it is possible to eliminate the dependency on alignment precision of the on-current capacity. I can do it. On the other hand, local regions along the inner edges of the source and drain films are not covered by the enlarged covering, but since this exposed region only occupies a relatively small area compared to the covering region, the channel In the buttering process by plasma etching of the film itself, there is little risk of reaction products adhering, and it is almost completely wiped out by removing the resist after etching.

Furthermore, if an overhanging covering part is formed in the enlarged covering part to hide the inner corner parts of the source film and drain film by providing a cutout part between the overlapping part and the overlapping part, the alignment accuracy will vary in the direction of the effective channel length. Even if the overhanging covering portion protrudes beyond the inner edge of the source film or drain film, the defective portion prevents the effective channel width from expanding. Furthermore, the exposed area of the source film or drain film is significantly reduced due to the presence of the overhanging covering portion. The exposed area is only a part of the defect.

〔Example〕

Next, embodiments of the present invention will be described based on the accompanying drawings.

FIG. 1(a) is a sectional view showing the structure of a thin film transistor according to a first embodiment of the present invention, and FIG. 1(b) is a plan view of the same structure. Note that the same parts in FIG. 1 as those shown in FIG. 8 are given the same reference numerals, and their explanations will be omitted.

The channel film 14 in this embodiment includes a pair of left and right enlarged covering parts 12 and 13 that almost entirely cover the source film 2 and drain film 3, and a narrow cap-like connecting part 1 that connects these parts.
It consists of 5. The equicap-shaped connecting portion 15 has a width equal to that of the opposing inner edges 2a of the source film 2 and drain film 3.
, 3b is set to be narrower than the difference between the length of the channel film 14 itself and twice the alignment margin of the channel film 14 itself, and overlaps and covers the source film 2 and drain film 3.
b, and an effective channel portion 15c extending in between.

On the other hand, the enlarged covering portion 12.13 covers the outer steps 2b and 3b of the source film 2 and drain film 3, but small regions near the inner edges 2a and 3b are exposed. That is, the inner edges 2a, 3 for the length of the overlapping portions 15a, 15b.
The area along line a is the non-covered area 12a.

13a.

In a structure having a channel film 14 having such a shape, even if a deviation occurs due to variations in alignment accuracy, for example in the arrow direction (direction perpendicular to the effective channel length direction) in FIG. Since the width of the portion 15 is narrower than the width of the source film 2 and drain film 3, a portion of the equicap-shaped connecting portion 15 does not protrude outside the width of the source film 2 and drain film 3, and is therefore shown with diagonal lines. A channel inversion layer with an unchanged channel length and channel width is formed only in the effective channel portion 15c in the region where the channel length and the channel width are unchanged. Also, for example, the second
Even if it deviates in the direction of the arrow (effective channel length direction) in FIG. 2B, the inner edge of the enlarged covering portion 14 does not protrude beyond the inner edge 2a of the source film 2 due to the presence of the non-covered regions 12a and 13a. . Therefore, the width dimension of the effective channel portion 15c in the shaded region is always uniform in its length direction. Therefore, even if variations in normal alignment accuracy inevitably occur during the manufacturing process (patterning process of the channel film 14), if the channel film 14 has such a shape, the variations will be reduced to the effective length and width dimensions of the channel portion. It does not cause any variation in the In other words, the shape of the channel film 14 has a function of breaking the causal relationship between variations in alignment accuracy and variations in the shape of the effective channel portion. Therefore, even if there is variation in alignment accuracy, a transistor with suppressed variation in on-current capacity can be obtained.

The uncovered region 12 of the channel film 14 is also in the normal position as shown in FIG.
Since the total area of a and 13a is always constant and this total exposed area is small compared to the area covered by the source film 2 and drain film 3, reaction products in the patterning process of the channel film 14 by plasma etching are The amount of adhesion to the resist is extremely small. The trace amounts of reaction products adhering to the resist are almost completely wiped out by the subsequent resist removal process. Therefore, a transistor with a clean MO3 interface and improved characteristics and quality can be obtained.

FIG. 3 is a plan view showing the structure of a thin film transistor according to a second embodiment of the present invention.

This embodiment is different from the first embodiment in that the enlarged covering portion 12.13 of the channel membrane 18 has overhanging covering portions 12a and 13b integrally connected to the inner edge thereof.
The protruding covering portions 12b and 13b hide the corner portions of the inner edges 2a and 2b of the source film 2 and drain film 3.

A slit-like cutout portion 12c is provided between the overhanging covering portions 12b, 13b and the overlapping portions 15a, 15b.

13c is formed. This slit missing portion 12c.

It is desirable to set the width dimension of 13c to a very small value close to the microfabrication limit.

According to the channel film 15 having such a shape, as shown in FIG. 4, even if the channel film 15 deviates in the direction of the arrow due to variations in alignment accuracy, the shape and dimensions of the formed channel inversion layer will remain the same as in the first embodiment. This remains unchanged, and the total area of the exposed regions (shaded regions) of the source film 2 and drain film 3 also remains unchanged. Even if the channel film 15 is displaced in the effective channel length direction due to the presence of the slit defects 12a and 13c, variations in on-current capacity are not caused, and the overhanging covering portion 1
2b.

Due to the presence of 13b, the exposed area of the source film 2 and drain film 3 can be reduced compared to the case of the first embodiment.

〔Effect of the invention〕

As explained above, the present invention has a pair of enlarged covering parts that cover both a source film and a drain film as a shape element of a channel film, and an equal-width connecting part that connects them. This structure is characterized in that only the regions along the inner edges of the source film and drain film are exposed for the length of the overlapping portion, so that the following effects are achieved.

■ Due to the existence of the narrow cap-like connecting portion and the uncovered region, the shape and dimensions of the formed channel inversion layer remain unchanged even if there are variations in alignment accuracy. It can be resolved. In other words, it can be said that the channel film having the above shape effectively absorbs variations in alignment accuracy.

■ The source and drain films are not completely hidden due to the presence of the uncovered region, but since the exposed region is extremely small, the reaction products that occur during the patterning process by plasma etching of the channel film will not adhere. Since it is so small, it can be thoroughly cleaned at the same time as the subsequent resist removal.

Therefore, contamination at the MO3 interface can be eliminated,
Contributes to improving transistor characteristics.

■Furthermore, if the enlarged covering part has an overhanging covering part with a defect in the overlapping part, only a part of the defect is exposed, so the above effect (■) becomes even more remarkable. Become.

[Brief explanation of drawings]

FIG. 1(a) is a sectional view showing the structure of a thin film transistor according to a first embodiment of the present invention, and FIG. 1(b) is a plan view of the same structure. FIGS. 2(a) and 2(b) are plan views showing a state in which the channel film is shifted due to variations in alignment accuracy in the same embodiment. FIG. 3 is a plan view showing the structure of a thin film transistor according to a second embodiment of the present invention. FIG. 4 is a plan view showing a state in which the channel film is displaced due to variations in alignment accuracy in the same embodiment. FIG. 5(a) is a cross-sectional view showing the structure of a conventional thin film transistor, and FIG. 5(b) is a plan view of the same structure. FIGS. 6(a) to 6(e) are cross-sectional views illustrating the process of obtaining a channel film in the same conventional structure. FIGS. 7(a) to 7(C) are cross-sectional views illustrating a process in which the patterning process of the channel film in the conventional structure is improved. FIG. 8(a) is a cross-sectional view showing the structure of a thin film transistor obtained by the improved process, and FIG. 8(b) is a plan view of the same structure. FIG. 9 is a plan view showing a state in which the channel film is shifted due to variations in alignment accuracy in a thin film transistor obtained by the improved process. [Explanation of symbols] Work...Transparent insulating substrate, 2...Source film, 2a, 3a
...Inner edge, 3...Drain film, 5...Silicon oxide film, 6...Gate electrode, 7...Source electrode, 8
...Pixel electrode (drain electrode), 12.13...
Enlarged covering section, 12a. 13a...uncovered area, 12b, 13b...overhanging covering part, 12c, 13c...slit missing part, 14.1
8... Channel membrane, 15... Isocap-shaped connection part, 15a
, 15b... Overlapping part, 15c... Effective channel part.

Claims (2)

[Claims] (1) In a thin film transistor having a source film and a drain film made of impurity-doped polycrystalline silicon that are spaced apart on an insulating substrate with their opposing inner edges parallel to each other, the source film and the drain film are straddled over the source film and the drain film. The polycrystalline silicon channel film formed by the method has a uniform width connecting portion narrower than the length of the inner edge, and a pair of left and right enlarged covering portions integrally connected to both ends of the connecting portion. The width-like connecting portion is composed of an overlapping portion overlappingly deposited on the source film and the drain film, and an effective channel portion extending between these overlapping portions, and the enlarged covering portion is configured to cover the overlapping portion about the inner edge. A thin film transistor characterized in that the source film or the drain film is hidden except for only a region approximately corresponding to the length of the mating portion. (2) An overhanging covering part is integrally connected to the enlarged covering part and providing a cutout part between the enlarged covering part and the overlapping part to hide a corner part on the inner edge side. The thin film transistor described in .