JPH0379057A - Temperature distribution evaluation method on wafer surface - Google Patents
Temperature distribution evaluation method on wafer surfaceInfo
- Publication number
- JPH0379057A JPH0379057A JP21674589A JP21674589A JPH0379057A JP H0379057 A JPH0379057 A JP H0379057A JP 21674589 A JP21674589 A JP 21674589A JP 21674589 A JP21674589 A JP 21674589A JP H0379057 A JPH0379057 A JP H0379057A
- Authority
- JP
- Japan
- Prior art keywords
- temperature distribution
- wafer surface
- wafer
- sheet resistance
- distribution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000011156 evaluation Methods 0.000 title abstract 3
- 238000000034 method Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 239000004615 ingredient Substances 0.000 abstract 1
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 241000257465 Echinoidea Species 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、ウェハ面内の温度分布の評価方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for evaluating temperature distribution within a wafer surface.
〈従来の技術、発明が解決しようとする課題〉最近、ラ
ンプ照射によシ短時間でウェハを加熱するＲ Ｔ Ａ
（Ｒａｐｉｄ Ｔｈｅｒｍａｌ Ａｎｎｅａｌ）技術が
活発に開発されているうしかし、熱的に非平衡な状態に
なっている為に、ウェハ面内の温度分布が大きくなる。<Prior art and problems to be solved by the invention> Recently, RTA has been developed to heat a wafer in a short time by lamp irradiation.
Rapid Thermal Anneal (Rapid Thermal Anneal) technology is being actively developed, but since the wafer is in a thermally non-equilibrium state, the temperature distribution within the wafer surface becomes large.
その為、ウエノ・面内の温度分布を評価する技術が必要
になる。９００〜１２００℃の高温領域の場合、ウェハ
を酸化し、酸化膜厚の分布より、ウェハ面内の温度分布
の評価が可能になる。しかし、４００〜６００℃の低温
領域での温度分布を評価する方法は、今まで見い出され
ていなかった。Therefore, a technology to evaluate the temperature distribution within the surface of the wafer is required. In the case of a high temperature region of 900 to 1200° C., the wafer is oxidized, and the temperature distribution within the wafer surface can be evaluated from the distribution of the oxide film thickness. However, a method for evaluating temperature distribution in a low temperature region of 400 to 600°C has not been found until now.
本発明は、上記低温領域に於けるウニ・・面内温度分布
の評価方法を提供するものである。The present invention provides a method for evaluating the in-plane temperature distribution of sea urchins in the above-mentioned low temperature region.
〈課題を解決するための手段〉
ＳｉウェハにＳｉ＋イオン注入を行い、ウェハ表面をア
モルファス化すると、固相エピタキシャル成長により結
晶性が回復するために、Ｂ＋イオン等が低温で活性化す
ることが知られている。<Means for solving the problem> It is known that when Si + ions are implanted into a Si wafer to make the wafer surface amorphous, B + ions etc. are activated at low temperatures because the crystallinity is restored by solid phase epitaxial growth. ing.
今回、Ｓｉ”＋Ｂ＋注入を行ったウェハを熱処理し、シ
ート抵抗のアーレニウス・プロットをとれば、良い直線
性が得られ、その傾き及びウェハ面内のシート抵抗分布
より、ウェハ面内の温度分布を評価することが可能にな
った。This time, if we heat-treat the wafer that has been implanted with Si''+B+ and take an Arrhenius plot of the sheet resistance, we can obtain good linearity, and from its slope and the sheet resistance distribution within the wafer surface, we can determine the temperature distribution within the wafer surface. It became possible to evaluate.
統計熱力学によれば、ある物理量Ａ（今回の場合は、シ
ート抵抗）は、アーレニウスの式に従う。According to statistical thermodynamics, a certain physical quantity A (in this case, sheet resistance) follows the Arrhenius equation.
■式の対数をとると、 ａ １ｏｇＡ””−７工＋ｌｏｇＡ０ ・・・・・■ となる。■If we take the logarithm of the equation, we get a 1ogA""-7t + logA0 ・・・・・・■ becomes.
すなわち、ｌｏｇＡと下のプロットを通常アーレニウス
・プロットと呼び、その直線の傾きから活性化エネルギ
ーＥａが求まる。That is, logA and the plot below are usually called an Arrhenius plot, and the activation energy Ea can be found from the slope of the straight line.
ａ
（７）および切片１ｏｇＡｏが求まれば、ＡとＴとの関
係は自動的に算出できる。If a (7) and the intercept 1ogAo are found, the relationship between A and T can be automatically calculated.
〈実施例〉 以下に、具体的実施例について説明する。<Example> Specific examples will be described below.
Ｓｉウエノ・を酸化後（酸化膜厚：２００人）、ｓｉ＋
注入（４８ＫｅＶ、 ３ ｘ １０” １ｏｎｓ／ｍ
） Ｌ、ひき続き、Ｂ＋注入（２０Ｋｅｙ、 ３ Ｘ
１０′５ｉｏｎｓ／ｃ＋＋りを行った。なお、注入エネ
ルギーは可変であるが、ＳｉとＢのＲｐ（飛程距離）を
同じにすることが望ましい。また、注入量はＩ Ｘ １
０１５１ｏｎｓ／−以上が必要になる。After oxidizing Si Ueno (oxide film thickness: 200 people), si+
Injection (48KeV, 3 x 10” 1ons/m
) L, followed by B+ injection (20Key, 3X
10'5 ions/c++ was performed. Although the implantation energy is variable, it is desirable that the Rp (range distance) of Si and B be the same. Also, the injection amount is I x 1
0151 ons/- or more is required.
第１図に、上記Ｓ ｉ” ＋Ｂ＋注入を行ったウニ・・
の熱処理後のシート抵抗値のアーレニウス・プロットを
示す。電気炉アニール（ｘ）及びＲＴ Ａ （ｏ）共に
、良い直線性が得られ、その活性化エネルギーＥａ＝１
，９ｅＶは、固相エピタキシャル成長の活性化エネルギ
ーと良い対応が得られている。直線の傾き及びシート抵
抗のウェハ面内分布より、ウェノ・面内の温度分布の評
価を行った。電気炉アニールの場合、熱平衡状態にある
為に、面内温度分布は良±１℃（１σ）である。一方、
ＲＴＡの場合、±８℃（１σ）の温度分布が見られた。Figure 1 shows the sea urchin that underwent the above-mentioned S i'' +B+ injection.
An Arrhenius plot of sheet resistance after heat treatment is shown. Good linearity was obtained for both electric furnace annealing (x) and RT A (o), and the activation energy Ea = 1
, 9 eV has a good correspondence with the activation energy of solid-phase epitaxial growth. The temperature distribution within the wafer surface was evaluated from the slope of the straight line and the distribution of sheet resistance within the wafer surface. In the case of electric furnace annealing, the in-plane temperature distribution is good ±1° C. (1σ) because it is in a state of thermal equilibrium. on the other hand,
In the case of RTA, a temperature distribution of ±8°C (1σ) was observed.
なお、今回の例では、ＲＴＡで４４０〜５２−０℃の温
度領域でのみしか温度分布の評価ができ、ないが、アニ
ール時間を変えることにより、直線が左右にシフトする
為、結果として４００〜６００℃の温度領域で温度分布
の評価が可能になる。第２図に示すように、温度分布が
評価できる領域は直線が傾斜している領域であり、温度
領域は限定されるが、第３図に示すように、シート抵抗
値（Ｐｓ ）は時間に対してもある一定の変化が見られ
る。すなわち、図中で点線Ａの時間よりも点線Ｃの短時
間処理の方が、より高い温度でｆ’ｓが飽和する。In this example, the temperature distribution can only be evaluated in the temperature range of 440 to 52-0℃ using RTA, but by changing the annealing time, the straight line shifts to the left and right, so as a result, the temperature distribution Temperature distribution can be evaluated in a temperature range of 600°C. As shown in Figure 2, the area where the temperature distribution can be evaluated is the area where the straight line is sloped, and the temperature range is limited, but as shown in Figure 3, the sheet resistance value (Ps) changes over time. Certain changes can also be seen. That is, f's is saturated at a higher temperature during the short-time processing indicated by dotted line C than during the time indicated by dotted line A in the figure.
すなわち、処理時間を変えることにより、評価可能領域
が多少ずれることになる。That is, by changing the processing time, the evaluable region will shift to some extent.
〈発明の効果〉
以上詳細に説明したように、本発明によれば、低温領域
に於けるウェノ・面内温度分布の評価が可能となるもの
であり、極めて有用な発明である。<Effects of the Invention> As explained in detail above, according to the present invention, it is possible to evaluate the temperature distribution in a plane in a low temperature region, and it is an extremely useful invention.
第１図はシート抵抗値のアーレニウス・プロットを示す
図、第２図及び第３図は本発明に係る評価可能温度領域
の説明に供する図である。
第２図FIG. 1 is a diagram showing an Arrhenius plot of sheet resistance values, and FIGS. 2 and 3 are diagrams for explaining the evaluable temperature range according to the present invention. Figure 2
Claims (1)
シート抵抗のアーレニウス・プロットをとり、その直線
の傾き及びウェハ面内のシート抵抗分布より、ウェハ面
内の温度分布を評価することを特徴とする、ウェハ面内
温度分布の評価方法。1. Heat-treat the wafer implanted with Si^++B^+,
A method for evaluating temperature distribution within a wafer surface, the method comprising: taking an Arrhenius plot of sheet resistance, and evaluating the temperature distribution within the wafer surface from the slope of the straight line and the sheet resistance distribution within the wafer surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1216745A JP2617228B2 (en) | 1989-08-22 | 1989-08-22 | Evaluation method of temperature distribution in wafer surface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1216745A JP2617228B2 (en) | 1989-08-22 | 1989-08-22 | Evaluation method of temperature distribution in wafer surface |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0379057A true JPH0379057A (en) | 1991-04-04 |
| JP2617228B2 JP2617228B2 (en) | 1997-06-04 |
Family
ID=16693265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1216745A Expired - Fee Related JP2617228B2 (en) | 1989-08-22 | 1989-08-22 | Evaluation method of temperature distribution in wafer surface |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2617228B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07248264A (en) * | 1993-11-09 | 1995-09-26 | Hughes Aircraft Co | Method and equipment for thermometry using ion implantation wafer |
| US6799888B2 (en) * | 2000-11-02 | 2004-10-05 | Matsushita Electric Industrial Co., Ltd. | Method for predicting temperature, test wafer for use in temperature prediction, and method for evaluating lamp heating system |
| JP2004335621A (en) * | 2003-05-02 | 2004-11-25 | Tokyo Electron Ltd | Heat treatment apparatus, temperature control method thereof and heat treatment system |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6328045A (en) * | 1986-07-07 | 1988-02-05 | バリアン・アソシエイツ・インコ−ポレイテッド | Apparatus and method for measuring temperature of semiconductor wafer |
-
1989
- 1989-08-22 JP JP1216745A patent/JP2617228B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6328045A (en) * | 1986-07-07 | 1988-02-05 | バリアン・アソシエイツ・インコ−ポレイテッド | Apparatus and method for measuring temperature of semiconductor wafer |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07248264A (en) * | 1993-11-09 | 1995-09-26 | Hughes Aircraft Co | Method and equipment for thermometry using ion implantation wafer |
| US6799888B2 (en) * | 2000-11-02 | 2004-10-05 | Matsushita Electric Industrial Co., Ltd. | Method for predicting temperature, test wafer for use in temperature prediction, and method for evaluating lamp heating system |
| JP2004335621A (en) * | 2003-05-02 | 2004-11-25 | Tokyo Electron Ltd | Heat treatment apparatus, temperature control method thereof and heat treatment system |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2617228B2 (en) | 1997-06-04 |
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