JPH0378064A - Input/output control system under integrated memory control of peripheral control part - Google Patents

Abstract

PURPOSE:To eliminate the overhead of postprocessing for an input/output request on an arithmetic processor by setting a dedicated area of each peripheral control part where control information on input/output processing of each peripheral control part on a main storage part. CONSTITUTION:When the arithmetic processor 10 sends out an input/output request, peripheral control parts 40-42 perform corresponding input/output processing. The states of the processing and pieces of input/output completion information are written in dedicated areas 25-27 of the main storage part 20 and when the input/output processing is completed, the peripheral control parts 40-42 sends completion information to the processor 10. The processor 10 reads pieces of status information out of the dedicated areas 25-27 of the main storage part 20 so as to check their completion states. Therefore, the processor 10 can read the input/output information out without sending any input/output request to read the statuses, and can know their last states even when a following status read is impossible as in the case of, for example, an abnormal end.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an input/output management system with a peripheral control unit, and more particularly to an integrated memory management system in which a dedicated area is set in a main storage unit.

2. Description of the Related Art In conventional input/output control systems, each peripheral control unit has a local memory, and input/output management information is contained in the local memory.

For example, as shown in FIG.
), an input/output (Ilo) request is issued from the peripheral control unit (p
The input/output processing unit (cu) performs the input/output processing based on the instruction, and upon completion, issues an input/output completion notification to the processing unit (EPU).6 Usually, this takes the form of an interrupt to the processing unit (EPU). This input/output completion notification includes summary information of the input/output process, but in the case of abnormal termination, subsequent processing may not be determined without seeing the detailed information1. It may be possible to retry depending on the state of It is necessary to issue a read request and read detailed information on the end status.

Problems to be Solved by the Invention In the conventional input/output control method described above, the input/output (Ilo)
It may be necessary to read the status after the completion of the request is notified, and since this is also performed using the I10 instruction, it occupies the arithmetic processing unit.

Furthermore, depending on the state of the peripheral control unit in that case (for example, if the process ends abnormally), the next status read may not be performed normally.

Therefore, the conventional method has the following problems: (1) Overhead on the arithmetic processing unit in post-processing of input/output requests; and (2) Inability to read status in case of abnormal termination.

The present invention has been made in view of the above-mentioned conventional situation,
Therefore, an object of the present invention is to provide a novel input/output control method that makes it possible to solve the above-mentioned problems inherent in the conventional technology.

Means for Solving the Problems In order to achieve the above object, an input/output control method based on integrated memory management of peripheral control units according to the present invention provides
pcu) is allocated a dedicated area divided on the main memory (HEM), and has the function of writing the input/output management information of each peripheral control unit to the dedicated area, and the function of writing the input/output management information of each peripheral control unit to the dedicated area. It is configured with a function that allows the arithmetic processing unit to refer to the written input/output management information.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Referring to FIG. 1, arithmetic processing unit 1 is connected to common bus 30.
0, main storage unit 20, peripheral control unit 40.41.42.・・・
・is connected.

Each peripheral control unit (pcui, PCU2, PCU3,
...) 40,41゜42, ... has firmware (F/%l) that controls input/output 50.51.52.
... are provided, and in order to perform input/output processing in response to input/output requests from the arithmetic processing unit 10, each peripheral bag f
f160.61.62. ...control.

The main storage unit 20 is divided and managed as shown in FIG.

In FIG. 2, the usage area of each peripheral control unit is 25°, 26.
27. . . , 28 is its size and main storage unit 20
The above location differs depending on the computer system. These used areas are the used area pointers 21, 22, 23, 21, 22, 23, 21, 22, 23, .
It is chained from 24 onwards. The positions of the used area pointers 21...24 are determined by each peripheral control unit 40, 41, 42, . . . regardless of the computer system. It is fixedly determined by...

The use area of each peripheral control section can be used by each peripheral control section as desired. Further, this used area is protected as shown in FIG. 3 so that its contents cannot be changed by other peripheral control units or arithmetic processing units.

Each peripheral control unit 40.41.42. ... writes information such as the completion status of input/output processing to this dedicated area.

FIG. 4 shows an example of input/output processing.

Referring to FIG. 4, first, when an input/output (Ilo) request is issued from the arithmetic processing unit (EPU), each peripheral control unit (
PCU ) executes the relevant input/output processing. Processing status and input/output completion information are written to a dedicated area of the main memory (MEM). This write process is performed by the arithmetic processing unit (EPU').
) is executed asynchronously with the processing unit fi (EP
It does not become the overhead of U).

Next, when the input/output processing is completed, each peripheral control unit (pcu
) issues a completion notification to the arithmetic processing unit (EPU).

In order to check the completion status, the arithmetic processing unit (EPU) reads the status information in the dedicated area of the peripheral control unit in the main memory (HEM).

As described in detail, according to the present invention, a dedicated area for each peripheral control unit is set on the main memory, and management information for input/output processing of each peripheral control unit is stored in the area. , the processing unit can read the input/output completion information without issuing a status read input/output request, and even when subsequent status reading is impossible, such as in the case of abnormal termination, This provides the advantage of being able to know the previous state of the peripheral control unit.

[Brief explanation of drawings]

FIG. 1 is an overall block configuration diagram showing an embodiment of the present invention;
FIG. 2 is a diagram showing the layout of the main memory section, FIG. 3 is a diagram showing an example of memory protection for each dedicated area of the main memory section, FIG. 4 is a timing chart of input/output processing in the present invention, and FIG. The figure is a timing chart of input/output processing in the conventional system. 10... Arithmetic processing unit (EPLI), 20... Main storage unit (MEN).

Claims (1)

[Claims] In a computer system in which an arithmetic processing unit and a peripheral control unit that controls peripheral devices can access a main memory unit via a common bus, each of the peripheral control units individually manages input/output completion status, etc. Integrated memory management of the peripheral control unit, characterized by including a function of writing information into a divided dedicated area of the main storage unit, and a function of allowing the peripheral control unit exclusive area to be referenced from the arithmetic processing unit. Input/output control method.