JPH0377494A - Video display device - Google Patents

Abstract

PURPOSE:To prevent synchronization disturbance based on a copy prevention signal by providing a mask signal forming means forming a mask signal of a pulse train signal and a mask gate means applying gate processing to a synchronizing signal and a mask signal and eliminating the pulse train signal. CONSTITUTION:A mask signal forming means comprising flip-flops 11a, 11e, a transistor 11b, NAND gates 11c, 11f, an inverter 11d, resistors R1-R5, and capacitors C1-C4 forms a mask signal of a pulse train signal for a multiplex period of the pulse train signal as a copy prevention signal at least at the later part in a vertical blanking period of the video signal. Then a mask gate means comprising an inverter 11d and a NAND gate 11g eliminates a pulse train signal for a multiplex period from the synchronizing signal by the gate processing between the synchronizing signal and the mask signal. Thus, no synchronization disturbance is generated based on the copy prevention signal at the initial period of each field and the video signal multiplexed with the copy prevention signal is reproduced stably without disturbance based on the output of the mask gate means.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video display device that reproduces a video signal on which a copy protection signal is added during the vertical blanking period.

[Conventional technology]

Conventionally, in order to particularly prevent dubbing recording of video cassettes, regular synchronization pulses such as equivalent pulses and vertical and horizontal synchronization pulses are set at intervals of 0.5 during the vertical blanking period of the video signal.
Alternatively, it has been proposed to multiplex a pulse train signal with a sufficiently short minute pulse interval as a copy prevention signal by IH (H is a horizontal scanning period).

This copy protection signal is multiplexed into an fcNTsc video signal, in which the waveform of the vertical blanking period of a negative synchronization signal (composite signal) obtained by synchronous separation is a multiplex of the negative polarity pulse train signal as the copy protection signal. According to trc, approximately Fig. 3 (as shown in al, in the case of ta+ in the same figure,
The pulse train signal as a copy protection signal is multiplexed by a length τ (τ × IH) from the trailing edge of the horizontal synchronizing pulse in the 8H multiplexing period Tb after the vertical blanking period Ta, and also in the 8H multiplexing period Tb after the vertical blanking period Ta. IH during the first equivalent pulse period also has a large amount of t.
be done.

The above-mentioned prevention of dubbing recording is achieved by providing the recording-side video tape recorder with a control mechanism that self-locks to prohibit recording upon detection of a copy prevention signal.

On the other hand, double-sided playback of video signals multi-supported with copy protection signals has conventionally been achieved using television receivers having CRTs, liquid crystal panels, etc.
O4N 9/31), a video display device such as a liquid crystal video projector is used to control the display of the synchronization signal in the same way as a normal video signal without a copy protection signal.

[Problem to be solved by the invention]

In the case of the conventional video display device, there are many copy protection signals.
When playing back a video signal, there is a problem in that the synchronization of each field is disrupted at the beginning of the field due to the copy protection signal.

When button 7 is pressed on the device using a liquid crystal panel, a disturbance in the playback screen due to synchronization error always occurs at the beginning of the display of per fee/l/)' based on the so-called full scan display.

This disturbance in the playback screen is particularly noticeable in a liquid crystal video projector that displays a large screen, and the display performance of the projector deteriorates.

However, even in devices that reproduce the screen using double scan display using a CRT or the like, disturbances in the reproduced screen occur, although this is less noticeable than in full scan display.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a video display device that prevents synchronization errors based on copy protection signals and prevents disturbances in the playback screen when a video signal with a large number of copy protection signals is reproduced. shall be.

[Means to solve the problem]

In order to achieve the above object, the video display device of the present invention includes a method based on detecting a pulse edge interval of a synchronization signal that is synchronously separated from a video signal multiplexed with a copy protection signal.
mask signal forming means for forming a mask signal of the pulse train signal in a multiplexing period of the pulse train signal as the copy prevention signal at least after the vertical blanking period of the video signal; and mask gate means for performing gold gate processing to remove the pulse train signal of the multi-i periods of the synchronization signal.

[Effect]

In the case of the video display device of the present invention configured as described above,
The mask signal forming means forms a mask signal of the pulse train signal at least during the multiplex period of the pulse train signal after the vertical blanking period of the video signal.

Further, the mask gate means performs gate processing on the synchronization signal and the mask signal to remove the pulse train signal of the multiple i periods from the synchronization signal.

Therefore, at least the copy protection signal of the multi-electronic period of the synchronization signal output from the mask gate means is removed,
Initial synchronization errors in each field based on the copy protection signal are prevented, and disturbances in the playback screen are prevented.

〔Example〕

One embodiment will be described with reference to FIG. 1 and the following drawings.

Figure 2 shows the entire groove when applied to a color liquid crystal video projector with an image receiving function.
+1 is an antenna, (2) is a tuner, (3) is an external video input terminal, (4) is a display selection switch, (5) is a video detection circuit, (6) is an audio detection circuit, and (7) is an audio output circuit. , (8) l″lclc speaker.

(9) is a video processing circuit, αI is a synchronous separation circuit, (II)
is an unnecessary signal removal circuit that removes a copy protection signal, αη is a display timing control circuit, and a phase detector (12a)
.

It consists of a voltage controlled oscillator (12b), a counter (12C) and an output gate circuit (12d).

(13r), (13g), (13b) are the three primary colors R,
Transmissive LCD panel for G and B, (14r), (14
g), (14b) f'i, horizontal drive circuit (X driver) for liquid crystal panel (13r), (13g), (13b) consisting of shift register, (15r), (15g
), (15b) are liquid crystal panels (13r), (13g
), (13b) vertical drive circuit (Y dry glue).

Also, in Figure 1, which shows the unnecessary signal removal circuit, (R1) and (CI) are integrating resistors and capacitors, and (lla) is a D-input type flip-flop (hereinafter referred to as a flip-flop) for forming gate signals. (called P'kFF)
, (llb) indicates that the output signal of the synchronous separation circuit αQ is connected to the resistor (R
3) is an inverting buffer transistor whose base is supplied through the inverting buffer.

(R3) and (C2) are resistors and capacitors for the charge/discharge circuit connected in series between the power terminal (+B) and ground.

CIIC) ij low resistance R3) is a Nant gate for shaping the signal at the connection point of the capacitor (C2).

(R, 4), (C3) is a Nant gate (11,,C)
(Ild) is the inverter; (R5) and (C4) are the differential resistors and capacitors that detect the fall of the output signal of the inverter (lid). be.

(lie) is an R8 type FF, (llf) is a Nant gate for forming a mask signal, and CILg) is a Nant gate forming mask gate means.

And, Fig. 1 0FF (Ila), (lie), I
- transistor (1xb), Nant gate (Ilc),
(llf), inverter (lid) and resistor (R1) ~
(R5) and capacitors (C1) to (C4) constitute mask signal forming means, and an inverter (Hd) and a Nant gate (Ilg) constitute mask gate means.

Next, a case will be described in which the reproduced video signal 1-1 of a video cassette on which a copy protection signal is multiplexed is reproduced.

In this case, the display selection switch (4) is switched to the external video input terminal (3), and the playback video signal of the video cassette supplied to this input terminal (3) is detected via the display selection switch (4). It is input to the circuit (5).

Furthermore, the reproduced video signal via the video detection circuit (5) is
It is supplied to the audio detection circuit (6), the video processing circuit (9), and the synchronous separation circuit (IQ).

Then, the detected audio signal of the audio detection circuit (6) is supplied to the speaker (8) via the audio output circuit (7), and reproduced audio is output from the speaker (8).

Brightness/color separation of video processing circuit (9), Ma) IJ
The reproduced video signal is converted into three primary color signals of R, G, and B based on the processing, etc., and these three primary color signals are used as display signals in the horizontal drive circuits (14r), (14g), (14).
b).

Furthermore, the synchronous separation circuit αO synchronously separates the reproduced video signal and supplies it to the synchronous signal Sl and unnecessary signal removal circuit . . . 1 in FIGS. 3(a) and 3f.

At this time, in the unnecessary signal removal circuit (11), the synchronizing signal 8i is supplied to the clock terminal (ck) of the FF (Ila) and the inverter (lid), and the resistor (R2
)yk to the base of the transistor (llb), and the FF (lla) latches the level of the data terminal (dl) at the falling edge of the synchronization signal Si, and
lb) is turned on and off at the falling edge and rising edge of the synchronization signal Si.

The display timing control circuit Q power output gate circuit (
From 12d) to the integrating circuit of resistor (R, 1) and capacitor (C1), the vertical blanking period Ta is slightly shorter, approximately 15
A vertical blanking pulse Sv of period Tc of H is supplied.

Then, due to the integration of the resistor (R1) and the capacitor (C1), the vertical blanking pulse Sv is shifted in the delay direction by about 2H to include the multi-i period Tb of the pulse train signal as a copy prevention signal, and the FF (lla) Data terminal (dl
is supplied to

Therefore, the Q output terminal +Q+ of FF (xia) or 6 NAND gate CIIC), (txg) is connected to Fig. 3 (C1
As shown in , the pulse train signal removal period T included in the 15H multitone period Tb' starting almost immediately after the vertical synchronization pulse period
d gate pulse S1 is output.

! In addition, the capacitor (C2) is used for switching the transistor (llb) based on the synchronization signal Si.
It is timely discharged at the falling edge of i and charged at the rising edge of i.

At this time, based on the time constant settings of the resistor (R, 3) and capacitor (C2), the charge/discharge signal S2 at the connection point of the resistor (R3) and capacitor (C2) is as shown in Figure 3 (dl).
Depending on the charging and discharging of the pulse train signal as a copy protection signal, the signal does not reach the threshold level Vr of the Nandt gate (11C).

Then, the Nant gate (1) to which the charge/discharge signal S2 is supplied
As shown by the solid line in FIG. 3, the output signal S3 of 1C) becomes an inverted signal after being shaped by the charge/discharge signal 82k threshold level Vr only during the removal period Td, and becomes an inverted signal during the removal period Td.
Other than that, it is locked at a high level.

At this time, in the period Tb, the output signal S! The falling edge of is delayed by approximately the length τ of the pulse train signal.

Furthermore, the fall of the output signal S3 of the Nant gate (llc) is detected by the differentiation of the resistor (R4) and the capacitor (C3), and the resistor (R4) and capacitor (C3) are connected in synchronization with the fall of the output signal Ss. )'
The reset terminal (r) of F(Ile) is inverted to low level, and FF(lie) is reset.

-rfc, synchronization signal Sik inverted inverter (lid
) The falling edge of the output signal of the resistor (R5) and capacitor (C
4) is detected by the differentiation of 1. The falling edge of the signal at the connection point of the resistor (R5) and capacitor (C4) is synchronized with the rising edge of the synchronizing signal Si. pl'i'' (lie) set terminal f
sl is inverted to low level and FF (lie) is set.

Therefore, the output signal S4 of the Q output terminal (q) of the FF (lie) is generated during the removal period T, as shown by the solid line in FIG.
d, changes in synchronization with the rise of the trailing edge of the synchronization pulse of the synchronization signal S1 and the fall of the output signal Ss, and is locked at a high level except during the removal period Td.

Then, the -output signal S4 is supplied to the Nant gate (11f), and the output signal S4 of the removal period Td is inverted and extracted based on the gate signal S1 by the gate 1- (llf), as shown in FIG. A mask signal S5 shown by the solid line is formed.

During the removal period Td, this mask signal S5 falls in synchronization with the rising edge of the trailing edge of the synchronizing pulse of the synchronizing signal Si, and at times other than the multiplexing period Tb, the mask signal S5 falls to a very low level based on the charging time constant of the capacitor (C2). stand up after an hour,
During the multiplexing period Tb, the falling edge rises with a delay of approximately the length τ of the pulse train signal.

That is, the mask signal S5 is a portion where the pulse train signal as a copy prevention signal is multiplexed, and is made long so as to mask the multiplexed portion of the low level period from the trailing edge of the synchronization pulse of the synchronization signal Si.

Then, the synchronization signal S is inverted by an inverter (lid).
i and the mask signal S5 are supplied to the Nands gate (l1g) and subjected to gate processing, and based on this gate processing, the output signal SO of the Nands gate (l1g) is the same as that of the mask signal Ss, as shown in FIG. 3 (hl). When it is at a high level, it changes in the same way as the synchronizing signal Si, and when the mask signal S5 is at a low level, it is locked at a high level.

When the output signal So is locked to a high level based on the low level of the mask signal S5, the pulse train signal of the multiplex period Tb is masked and removed, and the output signal So becomes the synchronizing signal Si.
This is a signal obtained by removing the copy protection signal of the multiplexing period Tb from .

Then, the output signal So is supplied to the phase comparator (12a) at the display timing control circuit, and this phase comparator (iz
By a), the output signal So and the output gate circuit (12d)
The horizontal blanking pulse sh for vertical driving having a period of 0.5H is compared in phase with the output signal Saf as a reference.

The oscillation frequency of the voltage controlled oscillator (12b) is controlled by the phase difference signal of the phase comparator (12a), and the oscillation output counter (12c) of the oscillator (12b) synchronized with the synchronization signal Si counts.

Further, the count output of the counter (12C) is supplied to the output gate circuit (12d), and this gate circuit (12d
), the timing clock pulse P of the pixel period for horizontal driving, the horizontal blanking pulse sh'' for horizontal driving reset, and the horizontal blanking pulse Sh for vertical driving,
A vertical blanking pulse Sv for vertical drive reset is formed.

A timing clock pulse P and a horizontal blanking pulse Sh' are supplied to each horizontal drive circuit (14r).

(14g), (14b), horizontal blanking pulse Sh, vertical blanking pulse sv
are each vertical drive circuit (1st), (1sg), Dsb
) Supplied.

! In addition, the horizontal blanking pulse Sh is transmitted to the phase comparator (12
a), and based on the above phase comparison, each bar/L/
Sh+Sv is synchronized with the synchronization signal Si by so-called PLL control.

At this time, since the copy protection signal of the multiplex period Tb near the start of each field is removed from the synchronization signal Si and the output signal So is formed, the PLL control of each field is based on the copy prevention signal of the multiplex period Tb. No synchronization hole, LCD panel (13r), (13g).

(13b) Each pulse P+ Sh'+ S for display driving
h+ Sv is the shadow of the copy protection signal! ＃It is stably formed without being affected.

And each horizontal drive circuit (Hr), (14g), (
14b) applies display signals of three primary colors to each liquid crystal panel (13r), (13g), (13b) at the pixel period for each line of the video signal based on the timing clock pulse P and horizontal blanking pulse Sh'. .

In addition, each vertical drive circuit (15r), (15g), (
15b) Based on Fi, horizontal blanking pulse Sh, and vertical blanking/curse Sv, each liquid crystal channel (13r), (13g), (13b) is synchronized with the video signal.
Select each line.

And horizontal drive circuit (14r), (14g), (
14b), vertical drive circuit (15r), (15g),
(15b), each LCD 7 inch panel (13r), (1
3g) and (13b) are driven for full scan display.

At this time, each liquid crystal panel (13r), (13g),
(13b) is provided, for example, in the optical path of the white light color gold dispersion fc of the light source and the three primary color lights, and each liquid crystal/N11 channel (
13r), (13g).

The seven transmitted light beams (13b) are combined and the color reproduction image light is projected onto a screen from the projection lens, and the color image of the video signal is displayed on a large screen on this screen.

Next, a case will be described in which a video signal received by the tuner (2), that is, a normal video signal not multiplexed with a copy protection signal, is reproduced on the screen based on switching of the display selection switch (4).

In this case, based on the received video signal of the tuner (2) output from the display selection switch (4), the synchronization signal Si of the synchronization separation circuit Ql is generated as a pulse train as a copy prevention signal during the multiplexing period Tb etc. of FIG. The signal becomes a non-multiplexed signal.

Therefore, the charge/discharge signal S2. The output signals Ss and Sa are the third
As shown by the broken lines fdl, tel, and ffl in the figure, the low level period of the multiplex period Tb of the mask signal S5 becomes shorter as shown by the broken line tg+ in the figure.

The masking of the synchronization signal Si by the mask signal S5 is almost always negative, and the output signal SO becomes almost the synchronization signal Si itself.

Furthermore, based on the limitations of the removal process of the gate signal S1, the synchronization signal 8i is output as is as the output signal SO except for the removal period Td. This also prevents this level change from being inadvertently erased, so-called synchronization signal loss.

Further, a timing control circuit d21 based on the output signal SO
, each liquid crystal/f channel (Iar), (x3g), (1
3b) is stably driven to display in the same way as when the copy protection signal is applied, and the color image of the received video signal is displayed on a large screen.

In the above embodiments, the application is applied to a color liquid crystal video projector, but various types of reproduction of video signals in color or monochrome are possible using a full scan display using a liquid crystal display panel or fC?≦ scan display using a CRT or the like. It can be applied to video display devices.

Further, the present invention can also be applied to cases where the multiplex format and video signal system of the /f pulse train signal as a copy protection signal are different from those of the embodiment.

Furthermore, the circuit configuration etc. are not limited to the embodiments.

(lla) I omit Nantes Gate CIIC),
(Ilf) A mask signal may be formed during the entire period of the video signal without limiting the removal process based on the gate signal S by replacing the k inverter with t.

In this case, for example, the pulse train signal as a copy protection signal at the beginning of the vertical blanking period shown in FIG. 3 (al) is also removed.

〔Effect of the invention〕

Since the present invention is configured as described above, it produces the effects described below.

The mask signal forming means forms a mask signal of the pulse train signal during a multiplex period of the pulse train signal as a copy prevention signal at least after the vertical blanking period of the video signal.

Further, the pulse train signal of the multiplex period is removed from the synchronization signal by gate processing of the synchronization signal and the mask signal by the mask gate means.

Therefore, synchronization disturbance based on the copy protection signal does not occur at the beginning of each field, and the 4 video signals on which the copy protection signal is multiplexed can be stably reproduced without disturbance based on the output signal of the mask gate means. This is particularly effective when performing large-screen playback using full-scan display such as on a liquid crystal video projector.

[Brief explanation of drawings]

The drawings show one embodiment of the uninvented video display device, FIG. 1 is a wiring diagram of the main parts, FIG. 2 is a block diagram, and FIG.
(hl is a timing chart for explaining the operation. αG... Synchronization separation circuit, (... Unnecessary signal removal circuit, 1121... Display timing M control circuit, (13r)
, (13g), (13b)...Liquid crystal panel.

Claims (1)

[Claims] (1) In a video display device that plays back a video signal in which a pulse train signal with minute pulse intervals is multiplexed as a copy prevention signal during a vertical blanking period, detecting the pulse edge interval of a synchronization signal that is synchronously separated from the video signal. a mask signal forming means for forming a mask signal of the pulse train signal in a multiplexing period of the pulse train signal at least after the vertical blanking period; gate processing the synchronization signal and the mask signal; A video display device comprising mask gate means for removing the pulse train signal in the multiplex period of a synchronization signal.