JPH0377321A - Formation of electrode connecting hole in semiconductor device - Google Patents

Formation of electrode connecting hole in semiconductor device

Info

Publication number
JPH0377321A
JPH0377321A JP21381889A JP21381889A JPH0377321A JP H0377321 A JPH0377321 A JP H0377321A JP 21381889 A JP21381889 A JP 21381889A JP 21381889 A JP21381889 A JP 21381889A JP H0377321 A JPH0377321 A JP H0377321A
Authority
JP
Japan
Prior art keywords
electrode connection
insulating film
connection hole
connecting hole
electrode connecting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21381889A
Other languages
Japanese (ja)
Inventor
Yoshihiro Tabuchi
田渕 良弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP21381889A priority Critical patent/JPH0377321A/en
Publication of JPH0377321A publication Critical patent/JPH0377321A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To make a coverage of an electrode interconnection layer good in a part of an electrode connecting hole and to reduce a danger of a disconnection and the like in the part by a method wherein a recessed part which is larger than the electrode connecting hole to be formed is formed in a definite depth on an insulating film by a photolithographic operation and, after that, the electrode connecting hole is formed in a position where the recessed part has been formed by executing the photolithographic operation again. CONSTITUTION:A patterning operation of an electrode connecting hole is executed by using a photomask having an opening pattern which is larger than the electrode connecting hole to be formed. By adopting an RIE operation, an insulating film 2 is etched down to a definite depth from its surface to form a recessed part 3. Then, the BPSG film 2 in which the recessed part has been formed is annealed in a steam atmosphere; side faces of the vertically steep recessed part 3 are made to reflow; a gentle curve-shaped recessed part 4 is formed. By a second photolithographic operation, an electrode connecting hole 5 which has pierced the insulating film 2 is formed in the recessed part 4.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、さらに詳しくは
、半導体基板上に形成された絶縁膜に、電極接続孔を形
成する方法に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming electrode connection holes in an insulating film formed on a semiconductor substrate. .

〔従来の技術〕[Conventional technology]

半導体装置、例えばシリコン半導体装置では、そのウェ
ハ表面に形成されたダイオードやトランジスタなどのエ
レメントを相互に結線して回路を構成するために、AI
などによる電極配線が必要である。この電極配線は、ウ
ェハ表面に形成されたSin、などの酸化膜からなる絶
縁膜上に形成され、このように形成された電極配線は、
絶縁膜に開けた電極接続孔を介して、ウェハ表面に形成
された各エレメントの側に接続されるようになっている
In semiconductor devices, such as silicon semiconductor devices, AI is used to interconnect elements such as diodes and transistors formed on the wafer surface to form a circuit.
electrode wiring is required. This electrode wiring is formed on an insulating film made of an oxide film such as Sin formed on the wafer surface, and the electrode wiring formed in this way is
It is connected to each element formed on the wafer surface through electrode connection holes drilled in the insulating film.

従来におけるこのような電極接続孔の形成方法としては
フォトリソグラフィ法が一般的である。
Photolithography is generally used as a conventional method for forming such electrode connection holes.

この方法では、良く知られでいるように、電極接続孔に
対応するパターンを有するフォトマスクを用いて電極接
続孔のバターニングを行ない、しかる後に、RIE(反
能性イオンエツチング)によって絶縁膜に対して垂直に
電極接続孔をエツチングするようにしている。さらに、
この後は、形成された電極接続孔のりフローを行い、あ
るいは他の方法を用いて形成された電極接続孔のテーパ
ーエツチングを行い、これによって、電極接続孔の側面
をなだらかな傾斜面とするようにしている。
In this method, as is well known, the electrode connection holes are patterned using a photomask having a pattern corresponding to the electrode connection holes, and then the insulating film is etched by RIE (reactive ion etching). Electrode connection holes are etched perpendicularly to the surface. moreover,
After this, taper etching is performed on the electrode connection hole that has been formed using a glue flow process or other methods, so that the side surface of the electrode connection hole has a gently sloped surface. I have to.

ここに、このように電極接続孔の側面をなだらかな傾斜
面とすることによって、この部分を覆う電極配線層の段
差被覆性を良くし、これによって、このような電極接続
孔の部分で電極配線が断線する危険性を回避するように
している。
By forming the side surface of the electrode connection hole into a gently sloped surface, the step coverage of the electrode wiring layer that covers this area is improved, and as a result, the electrode wiring can be formed in such a part of the electrode connection hole. This is to avoid the risk of disconnection.

(発明が解決しようとする課題) しかしながら、このように電極接続孔の側面をなだらか
な傾斜面とした場合においても、形成されている電極接
続孔の高さと幅との比(アスペクト比)は、傾斜面を付
ける、付けないにかかわらず一定である。従って、絶縁
層の厚さが一定であり、電極接続孔の高さが一定である
場合には、電極接続孔の幅が小さくなるのに伴って、ア
スペクト比は大きくなってしまう。このようにアスペク
ト比が大きくなると、それだけ電極配線層の被覆性が悪
化して、電極接続孔部分での配線が断線状態になってし
まう危険性が増大するので好ましくない。
(Problem to be Solved by the Invention) However, even when the side surface of the electrode connection hole is formed into a gently sloped surface, the ratio between the height and width (aspect ratio) of the formed electrode connection hole is It remains constant regardless of whether an inclined surface is attached or not. Therefore, when the thickness of the insulating layer is constant and the height of the electrode connection hole is constant, the aspect ratio increases as the width of the electrode connection hole decreases. Such a large aspect ratio is undesirable because the coverage of the electrode wiring layer deteriorates accordingly, increasing the risk that the wiring at the electrode connection hole will become disconnected.

本発明の課題は、このような従来の問題点に鑑みて、絶
縁膜の厚さおよび形成する電極接続孔の大きさが同一の
場合においても、従来の電極接続孔形成方法に比べて、
形成される電極接続孔の実効アスペクト比を小さくする
ことの可能となった電極接続孔形成方法を提案すること
にある。
In view of these conventional problems, it is an object of the present invention to provide a method for forming electrode connection holes that is better than the conventional method for forming electrode connection holes, even when the thickness of the insulating film and the size of the electrode connection holes to be formed are the same.
The object of the present invention is to propose a method for forming electrode connection holes that makes it possible to reduce the effective aspect ratio of the electrode connection holes that are formed.

〔課題を解決するための手段〕[Means to solve the problem]

上記の課題を解決するために、本発明における方法にお
いては、フォトリソグラフィ法を複数回、通常は二回行
って電極接続孔を形成するようにしている。すなわち、
第一回目のフォトリソグラフィにおいては、電極接続孔
形成位置に、電極孔を包含する大きな寸法の開口形成部
を有するフォトマスクを用いてバターニングを行い、次
に、絶縁膜を貫通しない深さにエツチングを行って、電
極接続孔形成位置に、電極接続孔よりも大きな寸法の凹
部を形成するようにしている。この後は、絶縁膜をリフ
ローさせて、形成された凹部を全体として湾曲状凹部と
する0次に、第二回目のフォトリソグラフィを行なって
、凹部形成位置をテーパエツチングして、電極接続孔を
形成する。このときには、電極接続孔に対応するパター
ンを有するフォトマスクを使用して行い、これによって
、凹部が形成された絶縁膜の部分に電極接続孔を開ける
In order to solve the above problems, in the method of the present invention, photolithography is performed multiple times, usually twice, to form electrode connection holes. That is,
In the first photolithography, patterning was performed at the electrode connection hole formation position using a photomask with a large opening forming part that encompassed the electrode hole, and then patterning was performed to a depth that did not penetrate the insulating film. Etching is performed to form a recessed portion larger than the electrode connection hole at the electrode connection hole formation position. After this, the insulating film is reflowed and the formed recess is made into a curved recess as a whole.A second photolithography is performed to taper-etch the recess formation position and form an electrode connection hole. Form. At this time, a photomask having a pattern corresponding to the electrode connection hole is used to make the electrode connection hole in the portion of the insulating film where the recess is formed.

〔作用〕[Effect]

上記の方法においては、第一回目のフォトリソグラフィ
によって、厚さTの絶縁膜における電極接続孔形成位置
には、電極接続孔よりも大きな一定の深さの凹部が形成
される。この部分では絶縁膜の厚さはt (<T)と薄
くなっている。このように薄くなっている絶縁膜の部分
に、第二回目のフォトリソグラフィによって電極接続孔
が形成されるので、この場合の接続孔の実効アスペクト
比は、電極接続孔の幅をWとすると、はぼt/Wとなり
、従来の方法による接続孔のアスペクト比T/Wに比べ
て小さくなっている。このように、本発明の方法におい
ては、第一回目のフォトリソグラフィにおいて形成され
る凹部の深さを深くして、電極接続孔形成部分の絶縁膜
の厚さtを小さくすることによって、実質的にアスペク
ト比を小さくすることができる。よって、このような電
極接続孔の部分における電極配線層の段差被覆性の低下
を防止することができる。
In the above method, by the first photolithography, a recess with a constant depth larger than the electrode connection hole is formed at the electrode connection hole formation position in the insulating film having the thickness T. In this part, the thickness of the insulating film is as thin as t (<T). Since the electrode connection hole is formed in the thinned insulating film part by the second photolithography, the effective aspect ratio of the connection hole in this case is as follows, where W is the width of the electrode connection hole. The aspect ratio is T/W, which is smaller than the aspect ratio T/W of the connection hole according to the conventional method. As described above, in the method of the present invention, by increasing the depth of the recess formed in the first photolithography and reducing the thickness t of the insulating film in the electrode connection hole forming part, The aspect ratio can be reduced. Therefore, it is possible to prevent the step coverage of the electrode wiring layer from deteriorating in such a portion of the electrode connection hole.

〔実施例〕〔Example〕

以下に、図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.

第1図(A)ないし第1図(E)には本発明の一実施例
を示してあり、第1図(A)に示すように、Si基Fi
1の表面上に形成された絶縁膜2に1μm角の電極接続
孔を形成する工程を示しである。本例の絶縁膜2は、厚
さが1μmのBPSG膜(P:5wt%、B:2wむ%
)である。
FIG. 1(A) to FIG. 1(E) show an embodiment of the present invention, and as shown in FIG. 1(A), Si-based Fi
1 shows the process of forming electrode connection holes of 1 μm square in an insulating film 2 formed on the surface of a semiconductor device 1. The insulating film 2 of this example is a BPSG film (P: 5wt%, B: 2wt%) with a thickness of 1 μm.
).

まず、第1図(B)に示すように、BPSG膜2に対し
て第一回目のフォトリソグラフィにより、電極接続孔形
成位置に凹部3を形成し、た。本例では、使用するフォ
トマスクとして、電極接続孔形成位置に、形成すべき電
極接続孔の4倍の大きさの2μm角の開ロバターンを有
するものを使用して電極接続孔のバターニングを行った
。そして、エツチング法としてRYEを採用して、絶縁
膜2の表面から約0.6μmの深さまでエツチングした
。このようにして、図に示すよ・うな、2μm角で深さ
0゜6μmの凹部3を形成した。
First, as shown in FIG. 1(B), a recess 3 was formed in the BPSG film 2 at the electrode connection hole formation position by a first photolithography process. In this example, patterning of the electrode connection holes is performed using a photomask that has an open pattern of 2 μm square, four times the size of the electrode connection hole to be formed, at the electrode connection hole formation position. Ta. Then, RYE was employed as the etching method, and the insulating film 2 was etched to a depth of about 0.6 μm from the surface. In this way, a recess 3 having a square size of 2 μm and a depth of 0.6 μm was formed as shown in the figure.

次に、凹部が形成されたBPSG膜2を、950°Cの
スチーム雰囲気中で30分間アニール処理し、垂直に切
り立った凹部3の側面3aをリフローさせて、第1図(
C)に示すよ・)に、なだらかな湾曲状の凹部4を形成
した。この結果、凹部4が形成された位置のBPSC;
膜の厚さtは約0゜5μmとなった。
Next, the BPSG film 2 in which the recesses have been formed is annealed for 30 minutes in a steam atmosphere at 950°C, and the side surfaces 3a of the vertical recesses 3 are reflowed, as shown in FIG.
As shown in C), a gently curved recess 4 was formed. As a result, the BPSC at the position where the recess 4 is formed;
The thickness t of the film was approximately 0.5 μm.

この後は、第二回目のフォトリソグラフィにより、凹部
4の部分に、電極接続孔を形成した。この場合には、フ
ォトマスクとしては、形成すべき電極接続孔に対応した
1μm角の開ロバターンを有するものを使用して電極接
続孔のバターニングを行った。そして、RIEによるテ
ーパエツチングを行い、第1図(D)に示すように、絶
縁膜を貫通した1μm角の電極接続孔5を形成した。
Thereafter, electrode connection holes were formed in the recessed portions 4 by a second photolithography process. In this case, patterning of the electrode connection holes was performed using a photomask having a 1 μm square open pattern corresponding to the electrode connection holes to be formed. Taper etching was then performed by RIE to form a 1 μm square electrode connection hole 5 penetrating the insulating film, as shown in FIG. 1(D).

このようにして形成された電極接続孔5番ごおいては、
その深さである絶縁膜2の厚さもが約0゜5μmであり
、その幅Wが1μmであり、この場合の実効アスペクト
比は0.5と見なすことができる。従って、従来のよう
に単に一回のフォトリソグラフィによって厚さ1μmの
絶縁膜に1μm角の電極接続孔を形成する場合のアスペ
クト比■に比べて半分の値となっている。
In the electrode connection hole No. 5 formed in this way,
The thickness of the insulating film 2, which is the depth thereof, is approximately 0.5 μm, and the width W thereof is 1 μm, and the effective aspect ratio in this case can be considered to be 0.5. Therefore, the aspect ratio (2) is half of the conventional case where a 1 .mu.m square electrode connection hole is formed in a 1 .mu.m thick insulating film by a single photolithography process.

最後に、第i図(E)に示すように、電極接続孔5が形
成されたBPSG膜2の表面上に、1%のSiを含有し
たA1合金(A、1−1%Si)の配線6を0.8μm
だけ堆積させた。この結果、電極接続孔4を介しての配
線側とSN基板とのコンタクト部7での断線は生じず、
電極接続孔部分のAl−1%St配線のステップカバレ
ッジ率は約60%と良好な結果が得られた。
Finally, as shown in FIG. 6 to 0.8μm
only deposited. As a result, disconnection at the contact portion 7 between the wiring side and the SN substrate through the electrode connection hole 4 does not occur.
The step coverage rate of the Al-1%St wiring in the electrode connection hole portion was about 60%, which was a good result.

ここで、上記の例では、第一回目のフォトリソグラフィ
によって、形成すべき電極接続孔の2倍の幅で、深さが
絶縁膜の約半分の凹部を形成するようにしている。しか
し、本発明は、これらの数値に限定されるものではない
。凹部の大きさとしては、形成すべき電極接続孔を包含
し、これよりも大きな寸法であればよい。この寸法とし
ては、例えば電極接続孔の幅に対して約1.5ないし約
3倍の範囲のものが望ましいことが確認された。
Here, in the above example, the first photolithography is performed to form a recess that is twice the width of the electrode connection hole to be formed and has a depth that is approximately half the depth of the insulating film. However, the present invention is not limited to these values. The size of the recess may be any size that includes the electrode connection hole to be formed and is larger than this. It has been confirmed that this dimension is desirably in a range of, for example, about 1.5 to about 3 times the width of the electrode connection hole.

また、凹部の深さとしては、絶縁膜の厚さの約1/3な
いし約2/3の範囲のものが望ましいことが確認された
Furthermore, it has been confirmed that the depth of the recess is desirably in the range of about 1/3 to about 2/3 of the thickness of the insulating film.

なお、上記の例は本発明の一実施例を示すものであり、
本発明をこの実施例に限定することを意図したものでは
ない。例えば、形成する電極接続孔の寸法、絶縁膜の厚
さなどは上記の例とは異なるものであっても良いことは
勿論であり、また、形成された凹部あるいは電極接続孔
の側面をなだらかな傾斜面に形成するための方法も上記
以外の方法を用いても良いことは勿論である。
Note that the above example shows one embodiment of the present invention,
It is not intended that the invention be limited to this example. For example, it goes without saying that the dimensions of the electrode connection hole to be formed, the thickness of the insulating film, etc. may be different from those in the above example, and the sides of the formed recess or electrode connection hole may be smoothed. Of course, methods other than those described above may also be used for forming the inclined surface.

(発明の効果) 以上説明したように、本発明の方法においては、まずフ
ォトリソグラフィによって絶縁膜上に一定の深さで、形
成すべき電極接続孔より大きな凹部を形成し、しかる後
に再びフォトリソグラフィによって、凹部形成位置に電
極接続孔を形成するようにしている。従って、本発明の
方法によれば、絶縁膜の厚さが薄くなっている凹部形成
位置に電極接続孔が形成されるので、形成された電極接
続孔のアスペクト比は、凹部形成位置の薄くなった絶縁
膜の厚さに応じて実質的に小さくなる。よって、電極接
続孔部分での電極配線層の被覆性が良くなり、この部分
での断線などのおそれが減少し、電極配線の信頼性が向
上するという効果が得られる。
(Effects of the Invention) As explained above, in the method of the present invention, first, a recess larger than the electrode connection hole to be formed is formed at a certain depth on the insulating film by photolithography, and then again by photolithography. Accordingly, an electrode connection hole is formed at the position where the recess is to be formed. Therefore, according to the method of the present invention, since the electrode connection hole is formed at the recess formation position where the thickness of the insulating film is thinner, the aspect ratio of the formed electrode connection hole is lower than the thickness of the insulating film at the recess formation position. It becomes substantially smaller depending on the thickness of the insulating film. Therefore, the coverage of the electrode wiring layer in the electrode connection hole portion is improved, the possibility of disconnection in this portion is reduced, and the reliability of the electrode wiring is improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(A)は絶縁膜が形成されたSi基板を示す構成
図、第1図(B)は第一回目のフォトリソグラフィによ
って絶縁膜上に凹部が形成された状態を示す構成図、第
1図(C)は絶縁膜上の凹部の側面をなだらかな傾斜面
とした後の状態を示す構成図、第1図(D)は第二回目
のフォトリソグラフィによって凹部形成位置に電極接続
孔を形成した後の状態を示す構成図、第1図(E)は電
極接続孔が形成された絶縁膜上に電極配線層を堆積した
状態を示す構成図である。 符号の説明 1・・・・St基板 2・・・BPSG膜(絶縁膜) 3・・−凹部 3a−・−・凹部の切り立った側面 4・−湾曲状の凹部 5・−・電極接続孔 6−・−配線。
FIG. 1(A) is a block diagram showing a Si substrate on which an insulating film is formed, FIG. 1(B) is a block diagram showing a state in which a recess is formed on the insulating film by the first photolithography, Figure 1 (C) is a configuration diagram showing the state after the side surfaces of the recess on the insulating film are made into gently sloped surfaces, and Figure 1 (D) is a configuration diagram showing the state after the side surfaces of the recess on the insulating film are made into gentle slopes. FIG. 1(E) is a block diagram showing the state after formation, and FIG. 1(E) is a block diagram showing the state in which the electrode wiring layer is deposited on the insulating film in which the electrode connection hole is formed. Explanation of symbols 1... St substrate 2... BPSG film (insulating film) 3... - Recess 3a - - Sharp side surface of the recess 4 - Curved recess 5 - Electrode connection hole 6 −・−Wiring.

Claims (1)

【特許請求の範囲】 半導体基板上に形成されたリン、ボロンを含む酸化膜か
らなる絶縁膜に、電極接続孔を形成する方法において、 前記電極接続孔の形成位置にこの電極接続孔よりも大き
な寸法の開口形成部を有するフォトマスクを用いたフォ
トリソグラフィによって、前記絶縁膜上に、前記電極接
続孔を包含する大きさで、前記絶縁膜を貫通するには至
らない深さの凹部を形成する工程と、 前記凹部が形成された絶縁膜をリフローさせる工程と、 前記電極接続孔形成用のフォトマスクを用いたフォトリ
ソグラフィによって、前記絶縁膜上に形成した凹部をテ
ーパエッチングして、前記電極接続孔を形成する工程、 からなる半導体装置の電極接続孔形成方法。
[Claims] In a method for forming an electrode connection hole in an insulating film made of an oxide film containing phosphorus and boron formed on a semiconductor substrate, a hole larger than the electrode connection hole is provided at a position where the electrode connection hole is formed. forming a recess on the insulating film with a size that includes the electrode connection hole and a depth that does not penetrate the insulating film by photolithography using a photomask having an opening forming part with the same dimensions; a step of reflowing the insulating film in which the recess is formed; and taper etching the recess formed on the insulating film by photolithography using a photomask for forming the electrode connection hole to form the electrode connection. A method for forming an electrode connection hole in a semiconductor device, comprising the steps of forming a hole.
JP21381889A 1989-08-19 1989-08-19 Formation of electrode connecting hole in semiconductor device Pending JPH0377321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21381889A JPH0377321A (en) 1989-08-19 1989-08-19 Formation of electrode connecting hole in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21381889A JPH0377321A (en) 1989-08-19 1989-08-19 Formation of electrode connecting hole in semiconductor device

Publications (1)

Publication Number Publication Date
JPH0377321A true JPH0377321A (en) 1991-04-02

Family

ID=16645539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21381889A Pending JPH0377321A (en) 1989-08-19 1989-08-19 Formation of electrode connecting hole in semiconductor device

Country Status (1)

Country Link
JP (1) JPH0377321A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003060603A1 (en) * 2002-01-17 2003-07-24 Iljin Diamond Co., Ltd Thin film transistor substrate for liquid crystal display(lcd) and method of manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5698832A (en) * 1980-01-08 1981-08-08 Mitsubishi Electric Corp Preparation of semiconductor device
JPS6432651A (en) * 1987-07-29 1989-02-02 Hitachi Ltd Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5698832A (en) * 1980-01-08 1981-08-08 Mitsubishi Electric Corp Preparation of semiconductor device
JPS6432651A (en) * 1987-07-29 1989-02-02 Hitachi Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003060603A1 (en) * 2002-01-17 2003-07-24 Iljin Diamond Co., Ltd Thin film transistor substrate for liquid crystal display(lcd) and method of manufacturing the same

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