JPH0376590B2 - - Google Patents
Info
- Publication number
- JPH0376590B2 JPH0376590B2 JP12386482A JP12386482A JPH0376590B2 JP H0376590 B2 JPH0376590 B2 JP H0376590B2 JP 12386482 A JP12386482 A JP 12386482A JP 12386482 A JP12386482 A JP 12386482A JP H0376590 B2 JPH0376590 B2 JP H0376590B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- electrode
- film transistor
- drain
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010409 thin film Substances 0.000 claims description 38
- 239000004065 semiconductor Substances 0.000 claims description 25
- 239000010408 film Substances 0.000 description 13
- 239000000758 substrate Substances 0.000 description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 229910000077 silane Inorganic materials 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Description
【発明の詳細な説明】
本発明は薄膜トランジスターの構造に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a thin film transistor.
従来、薄膜トランジスターとして第１図、第２
図に示すスタガ型電極構造のものと第３図、第４
図、第５図に示すコプレーナ型電極構造のものが
知られている。各図において、１は絶縁基板、２
はゲート電極、３は絶縁体層、４は薄膜半導体
層、５はソース電極、６はドレイン電極を示す。
薄膜トランジスターではソース・ドレイン間距離
つまりチヤンネル長によつて出力特性が大きく変
化する。特に動作特性における最大動作速度を速
くするためにはできるだけチヤンネル長を短かく
するのが好ましい。しかしながら、ソース・ドレ
イン間距離を形成するのに蒸着マスクを用いる方
法やフオトエツチングを用いる方法では製造上の
制約からチヤンネル長は、数μｍ程度で限界があ
る。一方、薄膜半導体層の移動度はバルクの半導
体の移動度に比較して小さく特に低温で形成した
場合には極端に移動度が低下してしまう。例え
ば、基板温度300℃でシランのグロー放電分解法
により形成したアモルフアスシリコン膜や、基板
温度500℃で分子線成長法により形成した多結晶
シリコン膜では数cm2／ｖ・sec以下の小さい移動
度しか得られていない。したがつて第１図〜第５
図に示すようなスタガ型またはコプレーナ型電極
構造薄膜トランジスターではチヤンネル長が数μ
ｍ程度までにしか短かくならないので最大動作速
度は、数ＭHz以下と低い値しか得られない。 Conventionally, thin film transistors are shown in Figures 1 and 2.
The staggered electrode structure shown in the figure, Figures 3 and 4
A coplanar electrode structure shown in FIG. 5 is known. In each figure, 1 is an insulating substrate, 2
3 represents a gate electrode, 3 represents an insulator layer, 4 represents a thin film semiconductor layer, 5 represents a source electrode, and 6 represents a drain electrode.
The output characteristics of thin film transistors vary greatly depending on the distance between the source and drain, that is, the channel length. In particular, in order to increase the maximum operating speed in the operating characteristics, it is preferable to shorten the channel length as much as possible. However, in the method of using a vapor deposition mask or the method of using photoetching to form the distance between the source and drain, the channel length is limited to about several μm due to manufacturing constraints. On the other hand, the mobility of a thin film semiconductor layer is smaller than that of a bulk semiconductor, and particularly when formed at a low temperature, the mobility is extremely reduced. For example, an amorphous silicon film formed by glow discharge decomposition of silane at a substrate temperature of 300°C or a polycrystalline silicon film formed by molecular beam growth at a substrate temperature of 500°C has a small movement of several cm 2 /v・sec or less. I have only gained degrees. Therefore, Figures 1 to 5
In a thin film transistor with a staggered or coplanar electrode structure as shown in the figure, the channel length is several microns.
Since the length can only be shortened to about m, the maximum operating speed can only be as low as several MHz or less.
本発明の目的は上記の欠点を改善した最大動作
スピードの速い薄膜トランジスターを提供するこ
とにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor which improves the above-mentioned drawbacks and has a high maximum operating speed.
本発明によれば、絶縁基板上に少なくとも薄膜
半導体層と絶縁層とからなる２層構造を備え、該
２層構造の前記薄膜半導体層を挾んでソース電極
とドレイン電極が設けられてなり、かつ該ソース
電極もしくはドレイン電極と対向する位置に前記
絶縁層と前記半導体層とを挟んでゲート電極が設
けられていることを特徴とする薄膜トランジスタ
ーが得られる。 According to the present invention, a two-layer structure including at least a thin film semiconductor layer and an insulating layer is provided on an insulating substrate, and a source electrode and a drain electrode are provided sandwiching the thin film semiconductor layer of the two-layer structure, and A thin film transistor is obtained, characterized in that a gate electrode is provided at a position facing the source electrode or the drain electrode with the insulating layer and the semiconductor layer interposed therebetween.
本発明の薄膜トランジスターは、第６図、第７
図に示すように薄膜半導体４を挾んで対向するソ
ース・ドレイン電極の間のチヤンネル層を、ソー
ス電極５ないしはドレイン電極６のどちらか一方
と絶縁体層を挾んで対向するゲート電極により形
成するためチヤンネル長は薄膜半導体の膜厚とな
る。薄膜半導体の膜厚は数＋ηｍ程度から正確に
制御でき、しかもゲート電極に電圧印加を行なつ
たときの薄膜半導体中に広がるチヤンネル層の縦
方向への広がりは数百ηｍ程度である。したがつ
てフオトエツチング法等により形成した薄膜トラ
ンジスターに比較してチヤンネル長を数十分の一
と短くできる。動特性における最大動作速度はチ
ヤンネル長の二乗に反比例するから本発明の薄膜
トランジスターは従来のものよりも最大動作速度
を数百倍上げることができる。またソース・ドレ
イン電流は、チヤンネル長に反比例するから従来
の薄膜トランジスターと同じソース・ドレイン電
流を得るのに薄膜トランジスターの大きさを数十
分の一程度に小さくできる。 The thin film transistor of the present invention is shown in FIGS.
As shown in the figure, the channel layer between the source and drain electrodes facing each other with the thin film semiconductor 4 in between is formed by either the source electrode 5 or the drain electrode 6 and the gate electrode facing with the insulator layer in between. The channel length is the thickness of the thin film semiconductor. The thickness of the thin film semiconductor can be accurately controlled from about several + ηm, and when a voltage is applied to the gate electrode, the vertical spread of the channel layer in the thin film semiconductor is about several hundred ηm. Therefore, the channel length can be shortened to several tenths of that of a thin film transistor formed by photoetching or the like. Since the maximum operating speed in terms of dynamic characteristics is inversely proportional to the square of the channel length, the thin film transistor of the present invention can increase the maximum operating speed several hundred times over conventional thin film transistors. Furthermore, since the source-drain current is inversely proportional to the channel length, the size of the thin-film transistor can be reduced to about a few tenths of the size to obtain the same source-drain current as a conventional thin-film transistor.
以下本発明を実施例をもつて説明する。実施例
では、薄膜半導体層としてシランのグロー放電分
解法によるアモルフアスシリコン膜を用いたが、
他の薄膜製造可能な半導体たとえばCdSやCdSe
等の−半導体、SeやTe等の半導体、Ge等
の半導体や他の製造方法による薄膜シリコン半
導体たとえば分子線成長法による多結晶シリコン
薄膜やレーザアニーリングによる多結晶シリコン
膜も使用できることはいうまでもない。 The present invention will be explained below with reference to Examples. In the example, an amorphous silicon film made by glow discharge decomposition of silane was used as the thin film semiconductor layer.
Other semiconductors that can be manufactured in thin films such as CdS and CdSe
It goes without saying that semiconductors such as - semiconductors, semiconductors such as Se and Te, semiconductors such as Ge, and thin film silicon semiconductors produced by other manufacturing methods, such as polycrystalline silicon thin films produced by molecular beam growth and polycrystalline silicon films produced by laser annealing, can also be used. do not have.
実施例 １
第６図に示すように絶縁基板１上にゲート電極
２を形成し、この基板上に水素ベース20％シラン
およびアンモニア、窒素を含む混合ガスを200
c.c.／min流し、圧力0.3torr高周波電力20W、基板
温度30℃で窒化シリコン膜を形成した。次にゲー
ト電極２の一部を覆わないようにソース電極５を
形成し、さらにその上に水素ベース20％シランを
流量100c.c.／min流し圧力0.2torr、高周波電力
10W、基板温度300℃でアモルフアスシリコンを
形成した。この半導体膜上にソース電極５に覆わ
れていないゲート電極２を覆うようにドレイン電
極６を形成し薄膜トランジスターとした。窒化シ
リコン膜厚0.3μｍアモルフアスシリコン膜厚0.5μ
ｍでチヤンネル長は0.5μｍ、チヤンネル幅は50μ
ｍとした。このようにして製造した薄膜トランジ
スターは、ゲート電圧10V、ドレイン電圧10Vの
オン状態で105Ωcm以下、ゲート電圧0V、ドレイ
ン電圧10Vのオフ状態で109Ωcm以上最大動作速
度100MHz以上であつた。これらの値は例えば液
晶のスイツチング素子に十分であるばかりでな
く、スイツチング素子をテレビ信号によつて駆動
するときの駆動回路素子としても十分な値であつ
た。これは、本発明の薄膜トランジスターが、薄
膜半導体層４を界して対向して存在するソース電
極５とドレイン電極６、およびソース電極５と絶
縁体層３を界して対向するゲート電極２とからな
るためチヤンネル長が半導体膜厚できまるため、
チヤンネル長を短くできたためと考えられる。Example 1 As shown in FIG. 6, a gate electrode 2 is formed on an insulating substrate 1, and a mixed gas containing 20% hydrogen-based silane, ammonia, and nitrogen is poured onto this substrate at 200%
A silicon nitride film was formed at a flow rate of cc/min, a pressure of 0.3 torr, a high frequency power of 20 W, and a substrate temperature of 30°C. Next, a source electrode 5 is formed so as not to cover a part of the gate electrode 2, and then hydrogen-based 20% silane is poured over it at a flow rate of 100 c.c./min at a pressure of 0.2 torr and high frequency power.
Amorphous silicon was formed at 10W and substrate temperature of 300℃. A drain electrode 6 was formed on this semiconductor film so as to cover the gate electrode 2 not covered by the source electrode 5 to form a thin film transistor. Silicon nitride film thickness 0.3μm Amorphous silicon film thickness 0.5μm
m, channel length is 0.5μm, channel width is 50μm
It was set as m. The thin film transistor manufactured in this manner had a resistance of 10 5 Ωcm or less in an on state with a gate voltage of 10 V and a drain voltage of 10 V, and a resistance of 10 9 Ωcm or more in an off state of a gate voltage of 0 V and a drain voltage of 10 V, and a maximum operating speed of 100 MHz or more. These values were not only sufficient for, for example, a switching element of a liquid crystal, but also as a driving circuit element when a switching element is driven by a television signal. This is because the thin film transistor of the present invention has a source electrode 5 and a drain electrode 6 facing each other across a thin film semiconductor layer 4, and a gate electrode 2 facing each other across a source electrode 5 and an insulator layer 3. Since the channel length is determined by the semiconductor film thickness,
This is thought to be due to the channel length being shortened.
実施例 ２
第７図に示すように絶縁基板１上にソース電極
５を形成して、この基板上にアルゴンベース10％
シランを流量100c.c.／min流し、圧力0.3torr高周
波電力10W、基板温度300℃でアモルフアスシリ
コンを形成した。次にソース電極５の一部を覆わ
ないようにドレイン電極６を形成しさらに半導体
層を酸素プラズマ処理したのち同一真空系中でア
ルゴンベース10％シランおよびアルゴンベース10
％酸素を含む混合ガスを100c.c.／min流し、圧力
0.1torr、高周波電力20W、基板温度300℃で酸化
シリコン膜を形成した。この絶縁体膜上にドレイ
ン電極６に覆われていないソース電極５を覆うよ
うにゲート電極２を形成し薄膜トランジスターと
した。酸化シリコン膜厚は0.3μｍ、アモルフアス
シリコン膜厚は0.5μｍでチヤンネル長は0.5μｍ、
チヤンネル幅は50μｍとした。このようにして製
造した薄膜トランジスターも実施例１と同等の良
好な特性が得られた。これは実施例１と同様の理
由によると思われる。Example 2 As shown in FIG. 7, a source electrode 5 is formed on an insulating substrate 1, and a 10% argon base is applied on this substrate.
Amorphous silicon was formed by flowing silane at a flow rate of 100 c.c./min, at a pressure of 0.3 torr, at a high frequency power of 10 W, and at a substrate temperature of 300°C. Next, a drain electrode 6 is formed so as not to cover a part of the source electrode 5, and the semiconductor layer is further treated with oxygen plasma.
A mixed gas containing % oxygen is flowed at 100c.c./min, and the pressure
A silicon oxide film was formed at 0.1 torr, high frequency power of 20 W, and substrate temperature of 300°C. A gate electrode 2 was formed on this insulator film so as to cover the source electrode 5 not covered by the drain electrode 6 to form a thin film transistor. The silicon oxide film thickness is 0.3 μm, the amorphous silicon film thickness is 0.5 μm, and the channel length is 0.5 μm.
The channel width was 50 μm. The thin film transistor manufactured in this manner also had good characteristics equivalent to those of Example 1. This seems to be due to the same reason as in Example 1.
以上のように本発明の薄膜トランジスターによ
れば動特性での最大動作速度を速くできると同時
に素子形状を小さくすることが可能となる。 As described above, according to the thin film transistor of the present invention, it is possible to increase the maximum operating speed in terms of dynamic characteristics, and at the same time, it is possible to reduce the size of the element.
第１図、第２図は従来のスタガ型電極構造薄膜
トランジスターの断面図、第３図、第４図、第５
図は従来のコプレーナ型電極構造薄膜トランジス
ターの断面図、第６図、第７図は本発明の薄膜ト
ランジスターの断面図である。
図において、１は絶縁基板、２はゲート電極、
３は絶縁体層、４は薄膜半導体層、５はソース電
極、６はドレイン電極を示す。
Figures 1 and 2 are cross-sectional views of conventional staggered electrode structure thin film transistors, Figures 3, 4, and 5.
The figure is a sectional view of a conventional thin film transistor with a coplanar electrode structure, and FIGS. 6 and 7 are sectional views of a thin film transistor of the present invention. In the figure, 1 is an insulating substrate, 2 is a gate electrode,
3 is an insulator layer, 4 is a thin film semiconductor layer, 5 is a source electrode, and 6 is a drain electrode.
Claims (1)
とからなる２層構造を備え、該２層構造の前記薄
膜半導体層を挟んでソース電極とドレイン電極が
設けられてなり、かつ該ソース電極もしくはドレ
イン電極と対向する位置に前記絶縁層と前記半導
体層とを挟んでゲート電極が設けられていること
を特徴とする薄膜トランジスタ。1 A two-layer structure consisting of at least a thin film semiconductor layer and an insulating layer on an insulating plate, a source electrode and a drain electrode are provided with the thin film semiconductor layer of the two-layer structure sandwiched therebetween, and the source electrode or the drain A thin film transistor characterized in that a gate electrode is provided at a position facing the electrode with the insulating layer and the semiconductor layer interposed therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12386482A JPS5914675A (en) | 1982-07-16 | 1982-07-16 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12386482A JPS5914675A (en) | 1982-07-16 | 1982-07-16 | Thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5914675A JPS5914675A (en) | 1984-01-25 |
| JPH0376590B2 true JPH0376590B2 (en) | 1991-12-05 |
Family
ID=14871268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12386482A Granted JPS5914675A (en) | 1982-07-16 | 1982-07-16 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5914675A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5221631A (en) * | 1989-02-17 | 1993-06-22 | International Business Machines Corporation | Method of fabricating a thin film transistor having a silicon carbide buffer layer |
| JP2839529B2 (en) * | 1989-02-17 | 1998-12-16 | 株式会社東芝 | Thin film transistor |
-
1982
- 1982-07-16 JP JP12386482A patent/JPS5914675A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5914675A (en) | 1984-01-25 |
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