JPH0376480A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To attain excellent error correction by providing a direction ranking means comparing output values from a correction error calculation means while excluding corrected error output values whose intermediate value or output value is larger than a prescribed threshold level and ranking the correction direction in response to the comparison result. CONSTITUTION:An output of each error arithmetic circuit is fed respectively to each mean value/selector circuit and each mean value/selector circuit obtains a mean value (correction error in each direction) of outputs of two error arithmetic circuits respectively and the output of each error arithmetic circuit is compared with a prescribed threshold level, and when the output is larger than the prescribed threshold level, the corresponding direction is excluded from the direction of the error correction. The output of each mean value/selector circuit is fed to a ranking decision circuit 45 and remaining correction errors are compared among outputs of correction accuracy output circuits 41-44 and the error correction direction is ranked in response to the result of comparison. The ranking result (ranking flag) is fed to a 2-dimension error correction circuit.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B1 Overview of the invention C0 Prior art 1 Problem to be solved by the invention E0 Means for solving the problem 11 Effect G. Examples G-1゜G-2゜Basic structure (No. Figure 1) Configuration of the entire error correction device to which the present invention is applied (Figure 2) One-dimensional error correction circuit (Figures 3 and 4) Ranking control circuit (Figures 1, 5, and 6) 2 Dimensional error correction circuit (FIGS. 7 to 10) G-3゜G-4゜G-5゜B1 Effects of the invention A, Industrial application field The present invention relates to a video signal processing circuit, and in particular to a video signal processing circuit. The present invention relates to a video signal processing circuit that performs error correction.

B1 Summary of the Invention The present invention relates to a video signal processing circuit, and relates to a video signal processing circuit that, when sample data of a video signal is supplied and the sample data is erroneous, corrects the error sample data using surrounding sample data. , a plurality of correction error calculation means for calculating correction errors in a plurality of mutually different error correction directions using sample data around the error sample data, and a correction error calculation means among the output values from these correction error calculation means. and direction ranking means for excluding correction error output values whose intermediate values or output values are larger than a predetermined threshold value, comparing them with each other, and ranking the correction directions according to the comparison results. In addition to determining the correction error to determine the direction of correction, if at least one of the correction errors on both sides of the error sample data is larger than a predetermined threshold, this direction is excluded from error correction, and the correction errors in the remaining directions are calculated. This method ranks the direction of error correction based on the following.

C0 Prior Art For example, for errors in sample data of a video signal reproduced from a VTR (video tape recorder), error correction processing is performed using an error detection code or an error correction code. Furthermore, for sample data that cannot be corrected by these error correction processes, errors are corrected (error correction) by methods such as interpolation processing and replacement processing using other sample data without errors (error-free sample data).
It is carried out. This error correction is performed in the video signal processing process, after error detection and error correction processing, and before outputting the video signal.

As a type of error correction method, as shown in Fig. 5, interpolation (horizontal (H) interpolation (direction interpolation) using sample data at the same position on the upper and lower lines of error sample data PO (vertical (V)
Error sample data P
A method of interpolating using neighboring sample data on the diagonal line downward to the left of O (one-way interpolation of D), a method of replacing the error sample data using sample data around the error sample data PO, and a method of replacing the error sample data one field earlier or 1
Replacement using sample data at the same position before the frame (
Methods such as temporal replacement) are known.

Furthermore, when performing the above interpolation and replacement processing, as described in U.S. Pat. No. 4,419,693, for example,
In order to determine the direction of interpolation or replacement, the accuracy of error correction is predicted based on correction errors in each direction in the vicinity of error sample data.

In other words, the results of interpolation or replacement processing (accuracy of error correction) are predicted based on correction errors in each direction,
Interpolation processing and replacement processing are performed in the direction in which the result of error correction has the least difference from surrounding sample data.

For example, as shown in FIG. 5, the sample data PPI on the line above the sample data PO to which error correction is applied
, PPO,, PMI and the sample data NPI, NPO, NMI on the lower line to correct the horizontal correction error; (l PP0- (PP1+PM1)/2 l + l
NPO-(NP1+NM1)/2l)/2 is calculated, and sample data P1, Ml on both sides of the sample data PO to be subjected to error correction, and sample data PPI, NPI, PMI, above and below these sample data, are calculated.
Vertical correction error using NMI; (PI-(PP1+NP1)/2 + Ml-(P
P1+NP1)/2)/2, etc. are determined, these correction errors are compared, and interpolation processing is performed in the direction of the smaller correction error.

D5 Problem to be Solved by the Invention By the way, when a corrected error is determined using the sample data on the lines above and below the error sample data to which error correction is applied as described above, for example, if the sample data on the upper line The modified error I PP0-(P
P1+PMri/2 1 is large and the correction error l obtained from the sample data on the lower line NPO-(NP1
+NM1)/2 When 1 is small, the correction error in the horizontal direction, which is the average value of these, may be smaller than the correction errors in other directions. As a result, even though the correction error on the upper line is large, or in other words, the error correction result predicted from the correction error on the upper line is not good, this horizontal interpolation process and replacement Processing was selected and good interpolation or replacement processing could not be performed.

The present invention has been made in view of the above-mentioned circumstances, and when performing error correction of error sample data using interpolation processing or replacement processing, it is possible to optimally rank the direction of error correction. The purpose is to provide a video signal processing circuit.

83 Means for Solving the Problems In the video signal processing circuit according to the present invention, as shown in FIG. 1, when sample data of a video signal is supplied and the sample data is incorrect, peripheral sample data is used to This = Pig error sample data A plurality of correction error calculation means (H correction accuracy output circuit 41, ■ Correction accuracy output Out of the output values from the circuits 42, D. correction accuracy output circuit 43, D-correction accuracy output circuit 44) and the correction error calculation means, intermediate values in the correction error calculation means (for example, H(υ) error calculation circuit 41a,
H(D) error calculation circuit 4 lb, V(L) error calculation circuit 42a, V(R) error calculation circuit 42b, D.
(L) Error calculation circuit 4 3 a, D. (R) Error calculation circuit 4 3 b, D-(L) Error calculation circuit 4 4
a, D-(R) output value of the error calculation circuit 44b) or the modified error output values whose output values are larger than a predetermined threshold value are excluded and compared with each other, and the rank in the above-mentioned modification direction is determined according to the comparison result. It is characterized by having a direction ranking means (ranking determination circuit 45) that performs ranking.

F. Function In the video signal processing circuit according to the present invention, when determining the direction of error correction such as interpolation processing or replacement processing, the correction error is determined to predict the accuracy of error correction in each direction, and the error When at least one of the correction errors on both sides of the sample data is larger than a predetermined threshold, this direction is excluded from error correction, and the directions for error correction are ranked based on the correction errors in the remaining directions.

G. Embodiment Hereinafter, one embodiment of a video signal processing circuit according to the present invention will be described with reference to the drawings.

G-1. Basic structure e. <FIG. 1) FIG. 1 is a block circuit diagram of an embodiment of a video signal processing circuit according to the present invention. This circuit will hereinafter be referred to as a ranking control circuit.

For example, for errors in sample data of a video signal played from a VTR (video tape recorder),
Error correction processing using an error correction code or the like is performed. Further, for sample data that cannot be corrected by these error correction processes (error sample data), interpolation processing and replacement processing are performed using sample data without errors (error-free sample data). By the way, when performing the above-mentioned interpolation processing or replacement processing, it is necessary to determine in which direction the interpolation processing or replacement processing should be performed using sample data around the error sample data.

That is, when performing interpolation processing, for example, as shown in Figure 5, the average value of the sample data on both sides on the same line as the error sample data is calculated, and this average value is used to determine the horizontal Interpolation processing in the (H) direction, interpolation processing in the vertical (V) direction in which the average value of the sample data above and below the error sample data is used as the sample data of the error sample data, samples on both sides of the diagonal line downward to the right of the error sample data Interpolation processing in the direction of the downward diagonal line (D.) in which the average value of the data is used as the sample data of the error sample data, and the average value of the sample data on both sides of the diagonal line downward to the left of the error sample data is used as the sample data of the error sample data. The video processing circuit (ranking control circuit) according to the present invention preferably performs interpolation processing in the best direction among these interpolation processings. The priority order of the direction of these interpolation processes and replacement processes is determined based on correction errors obtained from sample data surrounding the error sample data.

In FIG. 1, an H correction accuracy output circuit 41, which serves as correction error calculation means in each direction, a correction accuracy output circuit 42,
D. The correction accuracy output circuit 43 and the D correction accuracy output circuit 44 are supplied with sample data around the error sample data to which error correction is applied and an error flag indicating the error state of these sample data. The modified precision output circuits 41 to 44 include two error calculation circuits (represented by subscripts a and b) and an average value/selector circuit (
It is represented by the subscript C. ), and in these error calculation circuits, corrected errors are determined using sample data around the error sample data. The output of each error calculation circuit is supplied to each average (I/selector circuit), and the average value (correction error in each direction) of the outputs of the two error calculation circuits is determined in each average (!/selector circuit). The output of each error calculation circuit is compared with a predetermined threshold, and if the output is greater than the predetermined threshold, the corresponding direction is excluded from the direction of error correction.The output of each average value/selector circuit is compared with a ranking determination circuit. 45, the remaining correction errors among the outputs of the correction accuracy output circuits 41 to 44 are compared with each other, and a ranking of the direction of error correction is performed according to the comparison result.This ranking is performed. The results of the ranking (ranking flags) are supplied to the two-dimensional error correction circuit 3, as shown in FIG.

In addition, the modified precision output circuit 41 to the modified precision output circuit 44
, the error status (error flag) of the sample data used to calculate the correction error in each direction above.
is determined, and a computation possible signal indicating whether or not a compensation error in that direction can be computed is supplied to the two-dimensional error compensation circuit 3.

G-21 Overall configuration of error correction device to which the present invention is applied (
FIG. 2) FIG. 2 is a diagram showing the overall configuration of an error correction device using the present invention. This error correction device includes a one-dimensional error correction unit that performs error correction using sample data without errors in the vicinity of the error sample data on the same line as the error sample data; It can be roughly divided into two-dimensional error correction units that perform error correction using sample data around the error sample data on the line and sample data at the same position in the previous frame.

In this FIG. 2, input terminal 1 has, for example, a VTR.
Sample data of a video signal after error correction processing and the like are performed on a reproduced video signal from a video tape recorder (video tape recorder) and an error flag corresponding to the sample data are supplied. Normally, this manual sample data includes error sample data that could not be completely corrected by the error correction process, and the error flag is used to identify these error sample data.

These error flags are set in the error correction processing circuit when there is an error in the sample data.
(N''), and when there is no error in the sample data, the reset state ti('Oi) is set.

These sample data and error flags are supplied to the one-dimensional error correction circuit 2, and the one-dimensional error correction circuit 2
In this step, error correction (one-dimensional error correction) in the horizontal direction (line direction) is performed. The sample data subjected to one-dimensional error correction is supplied to a two-dimensional error correction circuit 3, a line delay circuit 4, and a ranking control circuit 7.

The two-dimensional error correction circuit 3 includes the one-dimensional error correction circuit 2.
Sample data from the line delay circuit 4 delayed by 1 line (IH-1 horizontal scanning period) with respect to the output of , sample data from the line delay circuit 5 delayed by 2 lines with respect to the output of the one-dimensional error correction circuit 2 Sample data from a frame delay circuit 6 delayed by one frame (lF=2 vertical scanning times) with respect to the output of the line delay circuit 4 is also supplied. That is, based on the sample data from the line delay circuit 4, the sample data from the one-dimensional error correction circuit 2 is advanced by IH, the sample data from the line delay circuit 5 is delayed by IH, and the sample data from the frame delay circuit 6 is advanced by IH. The sample data from is delayed by IF. In other words, each sample data of the current line, the upper line, the lower line, and the line corresponding to the current line one frame before is supplied to the two-dimensional error correction circuit 3.

In this two-dimensional error correction circuit 3, optimal error correction is performed using the sample data on the four lines. That is, this two-dimensional error correction circuit 3 performs, for example, interpolation processing in multiple directions, replacement processing for replacing error sample data using sample data at the same position in the previous frame, and replacement processing for error sample data using neighboring sample data. It has various error correction functions such as replacement processing, and in this two-dimensional error correction circuit 3, the control signal (ranking flag) from the ranking control circuit 7, etc., is used to select ( 1) Error correction will be performed. That is,
The ranking control circuit 7 includes a one-dimensional error correction circuit 2,
Sample data and each error flag are supplied from the line delay circuit 4.5, and in this ranking control circuit 7, an optimal two-dimensional error correction direction is determined based on each sample data and each error flag. The result is supplied to the two-dimensional error correction circuit 3 as a control signal.

By the way, each of the above-mentioned human sample data can be obtained from, for example, 8-pinto, takes values from "01" to "FE" in hexadecimal, and performs calculations and judgments on these 8-bit data to obtain the above-mentioned data. This is to correct errors. The sample data after error correction is “00j” in hexadecimal.
From rFF.

The value may be set to . Further, in the case of a color video signal, error flags corresponding to sample data of a luminance signal, sample data of a color difference signal, and each sample data of a luminance signal and a color difference signal are supplied to terminal 1 for one pixel. Ru. At this time, the sampling frequency of the luminance signal is twice the sampling frequency of the color difference signal, and the sample data of the luminance signal has a wider band and contains more detailed information than the sample data of the color difference signal. That is, the sample data and error flag of the luminance signal have good predictability for determining the direction of error correction for error correction of the luminance signal and color difference signal. Therefore, sample data of the luminance signal and error flags are typically used to determine the optimal error correction direction. Note that when the error flag of the luminance signal and the error flag of the color difference signal for one pixel are different, the error correction of the luminance signal and the error correction of the color difference signal are respectively performed in the optimal direction.

As described above, error correction is performed on the error sample data that could not be corrected in the previous error correction process.

G-3, 1-dimensional error correction circuit (Fig. 3, Fig. 4) 2nd
The details of the one-dimensional error correction circuit 2 shown in the figure are shown in Figs. 3 and 4.
This will be explained using figures.

As shown in FIG. 3, the one-dimensional error correction circuit is a variable length error correction circuit that performs error correction using the weighted average value of a plurality of sample data on both sides of the error sample data on the same line as the error sample data. It can be roughly divided into an interpolation processing section and a replacement processing section that replaces the error sample data using one of the sample data near the error sample data on the same line as the error sample data. The variable length interpolation processing section is a variable length interpolation processor that calculates a weighted average value using a plurality of sample data on both sides of error sample data PO to which error correction is applied, which is input through terminal 1 shown in FIG. The processing circuit 11 and the second
A sample number control circuit 13 that determines the error flag corresponding to each sample data inputted through the terminal l shown in the figure, and controls the number of sample data used for weighted averaging and the coefficient of the weighted average based on the determination result. It consists of The replacement processing unit also includes a replacement processing circuit 12 that replaces the error sample data using one of the sample data without errors among the sample data, and a replacement processing circuit 12 that determines the error flag and performs replacement processing based on the determination result. Replacement mode control circuit 14 that determines sample data to be used for
It consists of Each error-corrected sample data from the variable length interpolation processing circuit 11 and replacement processing circuit 12 is supplied to the selector 16, and when interpolation processing is possible, the sample data obtained by interpolation processing is When data is taken out from the terminal 18 and interpolation processing is not possible, sample data obtained by replacement processing is taken out from the terminal 18. Of course, if there is no error in the sample data, the sample data is taken out from the terminal 18. It will be done.

This output sample data is supplied to a two-dimensional error correction circuit 3 shown in FIG.

Next, the specific operation of this one-dimensional error correction circuit will be explained.

As shown in FIG. 3, this one-dimensional error correction circuit 2 stores, for example, seven sample data P3, P2, Pl, PO, Ml, M2, M3 on the same line of the video signal, and these sample data. Corresponding error flag FP3,
FP2, FPI, FPOlFMI, FM2, and FM3 are supplied. The sample data PO is sample data to which error correction is applied, and the sample data P1. ．． P
2. P3 are three pieces of sample data in order from the one closest to the left of the sample data PO, and the sample data Ml,
M2 and M3 are three pieces of sample data in order from the one closest to the right of the sample data po.

These sample data P3, P2, Pi, Ml, M2
, M3 is a variable length interpolation processing circuit 11 and a replacement processing circuit 12
supplied to On the other hand, error flags FP3, FP2, FP
I, FMI, FM2, FM3 are sample number control circuit 1
3 and the replacement mode control circuit 14. In addition, sample data PO and error flag FPO are stored in latch 1.
5 and selector 16.

In the sample number control circuit 13, the state of the error flag of a plurality of sample data on both sides of the error sample data PO to be subjected to error correction is determined, and the sample data whose error flag is "1" (error present) is determined. A control signal is supplied to the variable length interpolation processing circuit 11 to perform weighted average processing while excluding . In the specific example shown in FIG. 3, six error flags FP3, FP2, FPI, FMI
, FM2, and FM3, and a control signal is supplied to the variable length interpolation processing circuit 11 to exclude sample data that is "l" (with error) and perform weighted average processing. Then, in the variable length interpolation processing circuit 11, weighted average processing is performed by excluding sample data whose error flag is "1" (error present) among the sample data P3, P2, Pi, Ml, M2, and M3. be exposed. here,
A specific example shown in FIG. 4 will be explained. In addition, ○ shown in this figure
indicates error-free sample data, × indicates error sample data, Δ indicates that at least one of the left and right pair of sample data is error sample data, and open indicates sample data that does not take into account error conditions.

As shown in FIG. 4a, error flag data FP3, FP
2.FPI, FMI, FM2, and FM3 are all “0” (
6 sample data P3, P on both sides of the error sample data PO to which error correction is applied (no error).
2. Pl, Ml, M2, and M3 are all error-free (
(using 6 samples), the coefficient of the weighted average is set to Kl, by 2
, K3, and the weighted average value P is P = KI
2) Add 3 X (P3+M3) to +.

As shown in FIG. 4b, the error flags FP2, FPI,
FMI and FM2 are all “0” (no error),
At least one of error flags FP3 and FM3 is "l"
(There is an error), and the four sample data P2 on both sides of the error sample data PO to which error correction is applied
, Pi, Ml, and K2 are error-free (using 4 samples), the weighted average value P is set to P- by I
2).

As shown in Figure 4C, the error flags FPI and FMI
is “O” (no error), and the error flag FP2
, FM2 is rlJ (with error), and two sample data PiM1 on both sides of the error sample data PO to which error correction is applied are in an error-free state (two samples are used), the weighted average value P is , p , KI X (P1+M1).

The weighted average value P obtained by the variable length interpolation processing circuit 11 as described above is supplied to the selector 16. by the way,
Regarding the values of 1, K2, and K3 in the above coefficient group, the following values are specifically used in consideration of ease of circuit configuration, number of component parts, etc.

When using 2 samples, K1・1/2・0.5. 2・K3=0.

When using 4 samples, K1・1/2+1/8+1/16・0.6875°K2
--(1/2+1/4)/4・-0,1875,K3・
Set to 0.

When using 6 samples, Kl・1/2+1/4-0.75. K2=-(1/2
+1/8)/2=-0,3125°K3=1/16・0
．． 0625.

Next, the replacement processing section (replacement processing circuit 12, replacement mode control circuit 14) shown in FIG. 3 will be explained.

In cases other than the three error modes shown in aS b and c in FIG.

In the replacement mode control circuit 14, the error flag FPI
, the state of FMI is determined and the error flag FPI, FM
When at least one of I is "1" (there is an error),
Among the sample data P1 and Ml, error-free sample data is used to replace the error sample data PO.

When error flags FPI and FMI are "l" (error present) and at least one of error flags F'P2 and FM2 is "0" (no error), error-free sample data among sample data P2 and K2 is selected. The error sample data PO is replaced using .

Note that both error flags FP2 and FM2 are “OJ (
(No error), sample data P2 is used in preference to sample data M2.

Error flag FP2, FPI, and FMIS FM2 are all "1" (error exists), and error flag FP3
, FM3 is "0" (no error), error-free sample data among the sample data P3 and K3 is used to replace the error sample data PO.

Note that when both error flags FP3 and FM3 are "0" (no error), sample data P3 is used with priority over sample data M3.

Error flag FP3, FP2, FPI, FMI, FM2
, when all of FM3 is "1" (error exists),
The last error-free sample data is used to replace the error sample data PO. Here, the last error-free sample data refers to the sample data stored in the memory provided in the latch 14 for 1 sample data, which is sequentially updated with error-free sample data on the same line. .

As described above, the sample data subjected to the replacement process is supplied to the selector 16. That is, the selector 16
is supplied with three sample data: sample data (weighted average value) obtained by the variable length interpolation processing circuit 11, sample data obtained by the replacement processing circuit 12, and sample data PO, and the interpolation/replacement processing control circuit One sample data is selected based on the control signal from 17 and the error flag FPO state and is retrieved via terminal 18. That is, in the selector 16, the error flag FP
When O is "0" (no error), sample data PO is selected and taken out from terminal 18, and when error flag FPO is "l" (error present) and the above interpolation process is possible, The weighted average value P (sample data subjected to interpolation processing) from the variable length interpolation processing circuit 11 is taken out, and if interpolation processing cannot be performed, the sample data obtained by the above replacement processing from the replacement processing circuit 12 is output to the terminal. It is taken out from 18. This output sample data is
The signal is supplied to the two-dimensional error correction circuit 3 shown in FIG. 2, etc.

G-4, Ranking control circuit (Fig. 1, Fig. 5, Fig. 6) The sample data after one-dimensional error correction has been applied as described above is the two-dimensional error correction circuit 3 shown in Fig. 2. Two-dimensional error correction is performed at. This two-dimensional error correction circuit 3 uses sample data around the error sample data on the same line and above and below the error sample data, sample data at the same position in the previous frame, etc. to correct errors caused by interpolation processing and replacement processing. Corrections will be made. For example, interpolation processing in multiple directions using sample data surrounding error sample data, replacement processing that replaces error sample data using sample data at the same position in the previous frame, error sample data using neighboring sample data, etc. A replacement process is performed to replace the .

The ranking control circuit 7 that predicts the (optimal) direction in which the results of these interpolation processing and replacement processing will have the least change from neighboring sample data and determines the priority order (ranking) of these directions will be described. Here, ■dimensional error correction circuit? , line delay circuit 4.5, and frame delay circuit 6 are shown in FIG. 5, and error flags corresponding to these sample data are shown in FIG. 6. Six sample data on both sides of the sample data PO on the same line (current line) as the sample data PO to be modified,
P3, P2, Pi, Ml, M2, M3, and each sample data on the upper line is PP3, PP2, PPI, P
P.O., P.M.I.

PM2 and PM3, and each sample data on the lower line is NF2, NF2, NPI, NPOlNMl, NM2
, NM3, and each sample data on the line corresponding to the current line before the frame is LP3, LP2, LP.
I, LPO, LMI.

Let them be LM2 and LM3. In addition, as shown in FIG. 6, error flags corresponding to each of the above sample data are set to FPO, PP3, PP2, FPI, FMI, FM2,
FM3, FPP3, FPP2, FPP 1, FPPO,
FPMI, FPM2, FPM3, FNP3, FNP2,
FNP 1, FNPOlFNMI, FNM2, FNM3
, FLr'3, FLP2, FLPI, FLPOlFLM
I, FLM2, and FLM3. Each circuit will be specifically explained below using FIG. 1.

The H correction accuracy output circuit 41 is for predicting the accuracy of error correction in the H direction based on correction errors in the H direction in the vicinity of error sample data, and is used to predict error correction accuracy in the H direction based on correction errors in the H direction in the vicinity of error sample data. Calculate the correction error using the sample data on the line above H (U)
An error calculation circuit 41a, an H(D) error calculation circuit 41b which also calculates a correction error using the sample data of the lower line, and an output of the H(U) error calculation circuit 41a and an H(D) error calculation circuit. It is composed of an average value/selector circuit 41c that calculates an average value with the output of 41b.

That is, the H(U) error calculation circuit 41a is supplied with sample data PPI, PPO, PMl and error flags FPPI, FPPOSFPM1 of the line above the sample data PO to be subjected to error correction, for example, and is supplied with the first line in the H direction. The corrected error PPo-(PP1+PM1)/2 is obtained. The H(D) error calculation circuit 41b also includes, for example, sample data NPI, NPOSNMI of the line below the sample data PO to which error correction is applied, and error flags FNP1. ．． FNPO1FNMI is supplied, and the second correction F-NPO-(NP1+NM1)/2 in the H direction is determined. These first and second corrected errors are supplied to an average value/selector circuit 41c. In this average value/selector circuit 41c, calculation is performed to obtain the average value of the first and second correction errors in the H direction. That is, the correction error in the H direction E (H); E (H)・(l PP0− (PP1+PM1)/2
1+NPO-(NP1+NM1)/2)/2 is obtained. This correction error E (H) in the H direction is supplied to the ranking determining circuit 45. The correction error E (H) in the H direction can be calculated as E(H)・0.5 x (I PpO−(0,75×
(PP1+P river 1) -0,3125X (PP2+P
M2)+0.0625X (PP3+PM3)) 1+
NPO-(0,75X (NP1+NM1)-O,
3125x (NP2+NM2)+0.0625X (
NP3+NM3)) l) may also be used. Also, for example, the first correction error I PP0- (PP
1+PM1)/2 When the error flag FPP1 of the sample data PPI used for the calculation of 1 is "l" (error present), the correction knife in the H direction -E (H) is [! ()l)=I NPO-(NP1+NM1)/2
shall be. Also, for example, the first correction error I in the H direction
PP0- (PP1+Pkawa1)/2 Error flag FPP1 of sample data PP1 used for calculation of 1
And the second correction in the H direction above! Ra-I NPO-(N
When the error flag FNP1 of the sample data NPI used for the calculation of P1+NMl)/21 is "1" (error present), the correction error E (H) in the H direction cannot be calculated, but the H calculation in the H direction is possible. The signal is sent via the output terminal 46 to the two-dimensional error correction circuit 3 shown in FIG.

Further, the first and second correction errors in the H direction are compared with a predetermined threshold T. As a result of this comparison, if at least one correction error is greater than or equal to the predetermined threshold T, the H direction is not considered as the optimal direction for two-dimensional error correction. That is, this H direction is excluded from the direction of error correction, and error correction is performed in other directions. In addition,
The value of the threshold T is variable and can be set externally. By reducing this threshold T, it is possible to increase the accuracy of determining the direction of optimal two-dimensional error correction, but the direction of error correction cannot be determined at many positions. On the other hand, by increasing the threshold T, the accuracy of determining the direction of error correction becomes worse at many positions.

The correction accuracy output circuit 42 is for predicting the accuracy of error correction in the direction ■ based on correction errors in the V direction in the vicinity of error sample data. For example, error sample data to which error correction is applied A V(L) error calculation circuit 42a that calculates a correction error using the sample data Pl on the left side of PO, sample data PP1 above and below the sample data P1, and NPI, and the sample data M1 and NPI on the right side of the sample data PO. A V (R) error calculation circuit 42b that calculates a correction error using the sample data PMI and NMI above and below the sample data Ml.
And the corresponding V(L)! ! The output of the 4-difference calculation circuit 42a and V(R
) An average value/selector circuit 42c that calculates an average value with the output of the entertainment difference calculation circuit 142b.

That is, in the V(L) error calculation circuit 42a, the V(R) error calculation circuit 42b, and the average value/selector circuit 42C, for example, the first correction error Pt-(PP1+
NPl)/2 Second correction error Ml-(PM1+NM1)/2 in direction ① Correction error E(V) in direction ②.

Em-(l PI-(PP1+NP1)/2 l +
I Ml-(PM1+NM1)/21 )/2 are respectively determined. This correction error E (V) in the direction of V′ji
is supplied to the ranking determination circuit 45.

Note that, similarly to when determining the correction error in the H direction, when the correction error cannot be calculated, a V calculation enable signal is outputted to the two-dimensional error correction circuit 3 shown in FIG. 2 via the output terminal 47. Further, it is determined whether the first and second correction errors are larger than a predetermined threshold T, and when they are larger than the threshold T, the V direction is not considered as the optimal direction for two-dimensional error correction.

D. The correction accuracy output circuit 43 is for predicting the accuracy of error correction in D and the direction based on the correction error in the direction in the vicinity of the error sample data. (L) Error calculation circuit 4
3a, the sample data M1 on the right side of the sample data PO, and the sample data PPO, NM2 on both sides of the diagonal line downward to the right of the sample data M1 to calculate a correction error; (11) error calculation circuit 43b; (L) Output of error calculation circuit 43a. (R)i
It is composed of an average value/selector circuit 43c that calculates an average value with the output of the jI difference calculation circuit 43b.

That is, as described above, (L) error calculation circuits 43a, D;

(R) Error calculation circuit 43b, average value/selector circuit 43
In c, for example, a first correction error in the direction Pl-(PP2+NPO)/2D, a second correction error in the direction Ml-(PPO+NM2)/2D, a correction error in the direction E(D, ).

E([1ya)・(I Pl−(PP2+NPO)/2
++ old-(PPO+NM2)/2 )/2 are obtained, respectively. This direction correction error E (D,
) is supplied to the ranking determination circuit 45. Note that, similarly to when determining the correction error in the H direction, when the correction error cannot be calculated, a computation possible signal is outputted via the output terminal 48 to the two-dimensional error correction circuit IM3 shown in FIG. Further, the first and second correction errors are set to a predetermined threshold (IT
If it is larger than the threshold T, then yes, the direction is not considered as the optimal direction for two-dimensional error correction.

The D-correction accuracy output circuit 44 is for predicting the accuracy of error correction in one direction of D based on the correction error in one direction of D in the vicinity of error sample data, and for example, when error correction is performed. IC(L) error calculation circuit 4 that calculates a correction error using the sample data P1 on the left side of the error sample data PO and the sample data PP01NP2 on both sides on the diagonal line downward to the left of the sample data Pi.
4a, and a D-(R) error calculation circuit 44b that calculates a correction error using the sample data Ml on the right side of the sample data PO and the sample data PM2 and NPO on both sides of the diagonal line downward to the left of the sample data Ml, The D
- It is composed of an average value/selector circuit 44c that calculates the average value of the output of the (L) error calculation circuit 44a and the output of the IC (R) error calculation circuit 44b.

That is, the D-(L) error calculation circuit 44a, D-
(R) Error calculation circuit 44b, average value/selector circuit 44
In c, for example, the first correction error in the D direction F - Pl - (PPO + NP2) / 2, the second correction error in the D direction - (PM2 + NPO) / 21, the correction error in the D direction E (D -); E(DJ=(I
Pl-(PPO+NP2)/2+ M1~(PM2
+NPO)/2 )/2 are respectively calculated. This D one-way correction error E (D-) is supplied to the ranking determination circuit 45. Note that, similarly to when calculating the correction error in the H direction, if the correction error cannot be calculated, use D-
The computable signal is transmitted via the output terminal 49 to the 2 signal shown in FIG.
It is output to the dimensional error correction circuit 3. Also, the first and second
It is determined whether the correction error is larger than a predetermined threshold T, and if it is larger than the threshold T, the corresponding direction is not considered as the optimal direction for two-dimensional error correction.

Next, in the ranking determination circuit 45, the remaining modified errors E(H), E(V), E
(D, ) and E (D-) are compared with each other, and a modification direction ranking (priority order) is determined in order of decreasing value. Note that when the correction error values in each direction are the same, priority is given in the order of the H direction, the {circle around (2)} direction, the D direction, and the D direction. The ranking flag (multiple bits) from this ranking determination circuit 45 is supplied to the two-dimensional error correction circuit 3 shown in FIG.

G-5. Two-dimensional error correction circuit (FIGS. 7 to 1O) A specific circuit configuration of the two-dimensional error correction circuit 3 shown in FIG. 2 will be described with reference to FIG. 7.

This two-dimensional error correction circuit 3 corrects errors around the error sample data PO, which is corrected using the ranking flag from the ranking control circuit 7 shown in FIG. An optimal interpolation direction determining circuit 51 and a high-precision temporal direct conversion determining circuit 52 that judge the state and determine the optimal error correction method.
, optimal replacement direction determining circuit 53, arbitrary interpolation direction determining circuit 5
4. A part consisting of a low-precision temporal replacement determination circuit 55, a nearest neighbor replacement determination circuit 56, an iterative replacement determination circuit 57, and an error correction method selector 58, and performs actual interpolation processing and replacement based on the determined error correction method. ■ Interpolation circuit 61, D+ interpolation circuit 62, D- interpolation circuit 63 that performs processing
, selectors 64, 65, and 66. Each of the above circuits will be explained in order below.

In FIG. 7, the optimum interpolation direction determining circuit 51 stores error flags FPPL, FPPO, FPM of sample data around error sample data 520 to which error correction is applied.
I, FPI, FMI, FNPl, FNPO5FNMI,
The ranking flag and computable signals in each direction are supplied from the ranking control circuit 7, and the states of these error flags, ranking flags, and computable signals are determined, and the optimal interpolation direction is determined. Specifically, exclude directions where the error flag is "1" (error present),
The highest priority direction is determined based on the ranking flag. A control signal indicating this highest priority direction is supplied to the error correction method selector 5.

In other words, even if the ranking control circuit 7 determines that the correction error is the smallest in the direction, if the sample data used for interpolation processing in this direction is in an error state, this direction will not be selected and will be given the next priority. The direction where is higher is selected.

The high-precision temporal replacement determining circuit 52 includes six sample data P3, P2, Pl, Ml, M2, M3 on both sides of the error sample data PO to be subjected to error correction, and seven sample data on the corresponding line of the previous frame. Sample data LP3
,LP2,LPI,LPO,,LMISLM2,LM3
, these sample data error flags FP3, PP
2, FPl, FMI, FM2, FM3, FLP3, FL
P2, FLP 1, FLPO, FLMl, , FLM2,
FLM3 is supplied, the error flag is judged, and it is determined whether temporal (on the time axis) replacement processing is possible. When all of the above error flags are rQJ (no error) and the difference between the corresponding sample data is less than or equal to a predetermined threshold HT, a control signal is sent to replace the error sample data PO using the sample data LPO of the previous frame. The error correction method selector 58 is provided. Specifically, PP3. FP2yu FPI engineering FM1=FM2・RM3=
FLP3=FLP2・FLPI・IILPO=PL old・
FLM2=FL gate 3; 0I LP3-P3 ≦HT, L gate 1-Ml ≦HT
LP2-P2 ≦HT, LM2-M2
≦HT.

LPI-PI I≦IIT, l LM3-? 131
When all the conditions of ≦IIT are satisfied, the error sample data PO is replaced with the sample data LPO. That is, when the six sample data on both sides of the error sample data PO do not change much over time, replacement is performed on the assumption that the error sample data PO also does not change over time. Note that the threshold value HT is a small value.

The optimum replacement direction determining circuit 53 includes an error flag FPPI.
, FPPO, FPMI, FPI, FMI, FNP 1,
FNPO, FNMI, ranking flags from the ranking circuit 7, and computable signals in each direction are supplied, and the states of these error flags, ranking flags, and computable signals are determined, and the optimal replacement direction is determined. Specifically, directions with an error flag of "1" (error present) are excluded, and the highest priority direction is determined based on the ranking flags of the remaining directions. A control signal indicating this highest priority direction is supplied to the error correction method selector 58.

The arbitrary interpolation direction determining circuit 54 includes an error flag FPPI.
,FPPO,FPMI,FPI,FMI,FNPI,F
NPO and FNMI are supplied, and the states of these error flags are determined. In other words, the error flag is "0"
(no error) is selected, and a control signal that enables interpolation processing in this direction is supplied to the error correction method selector 5.

Note that when multiple directions are selected, the H direction, ■ direction, and D direction. Priorities are set in the order of D direction and D direction.

The low precision temporal replacement determining circuit 55 includes six sample data P3, P2, Pl/ML M2, M3 on both sides of the error sample data PO to be subjected to error correction, and seven samples of the corresponding line of the previous frame. data LP3
, LP2, LPI.

LPOlLMI, LM2, LM3 and error flags of these sample data FP3, FP2, FPl, FMI
, FM2, FM3, FLP3, FLP2, FLP 1,
FLPO1FLMI, FLM2, and FLM3 are supplied. In this low precision temporal replacement determining circuit 56, the above error flag is determined, and the error flag FLPO is "
O” (no error), and the error sample data P
At least one set of the three sets of corresponding error flags on each side of O is "0" (no error), and
And the difference between the two sets of sample data is determined by a predetermined threshold (i
When less than L T, sample data LPO of the previous frame
A control signal for replacing the error sample data PO using the error correction method selector 58 is provided to the error correction method selector 58. That is, FLPO=O.

FP3・PLP3=O or FP2=FLP2・O or F
P1=FLPI=O.

FMbFLMl・0 or FM2=FLM2・O or FM
3・FLM3=O.

LPn-Pn l ≦LT, l LMm-
When the condition of Mix I≦LT (n and m represent error-free numbers) is satisfied, the error sample data PO is replaced with the sample data LPO.

In other words, in the high-precision temporal replacement circuit 52, the six sample data on both sides of the error sample data PO and the sample data of the corresponding previous frame must all be in an error-free state, and the error rate is low. The high-precision temporal replacement is effective when the error rate is high, and the low-precision temporal replacement □ is effective when the error rate is high. Note that the threshold value LT is a small value.

The nearest neighbor replacement determining circuit 56 includes four error flags F on both sides of the error sample data PO to be subjected to error correction.
P2, FPI, FMI, FM2, 3 error flags on the upper line FPPISFPPO, FPMI and 3 error flags on the lower line FNP 1, FNPO, FNM
I is supplied and the state of these error flags is determined. In other words, the error flag is "0" (no error)
The nearest (nearest neighbor) sample data among the sample data is used to replace the error sample data PO. A control signal for replacing the error sample data PO with this nearest neighbor sample data is supplied to the error correction method selector 58. Note that when multiple sample data are available, sample data P1, ML P2,
M2, PP05NPO1PP L PMI, NPISN
Priorities are set in the order of MI.

The repeat replacement determination circuit 57 is supplied with the error flag FPO and the recursion count from the recursion count memory 60. Here, repeated replacement refers to repeatedly replacing the error sample data PO using sample data subjected to error correction. For example, the first generation is sample data obtained through replacement processing using error-corrected sample data,
The sample data obtained by performing the replacement process again using this first generation sample data is defined as the second generation.

Furthermore, the states of these generations are expressed by recursion counts. That is, for example, as shown in FIG. 8, sample data P5 is in an error-free state jIq
(○), sample data P4, P3, P2, Pl
, po are all in the error state (x), sample data P4 is replaced with error-free sample data P5, and sample data P3 is replaced with sample data P4 to become the first generation. Sample data P2 is replaced with sample data P3 and becomes the second generation. Sample data P
1 is replaced with sample data P2 and becomes the third generation.

The sample data PO is replaced with the sample data Pl and becomes the fourth generation. FIG. 9 shows a specific example of sample data of the 8th generation. As for the specific value of the above recursion coefficient, an initial value is set according to each error correction method as shown in Table 1, and 2 is added to this initial value each time the above repeated substitution is performed. . (Margin below) Table 1 Note that default temporal replacement in Table 1 refers to replacing the error sample data PO using the sample data LPO of the previous frame when all of the above error correction methods cannot be used. In addition, an externally variable upper limit value is provided to the recursion count to limit the generation of the repeated substitutions. That is, for example,
The maximum value of the recursion count is set to 7, and the generations of repeated replacement are limited to 4. Further, the maximum value of the recursion count is set to I5, and the number of generations of repeated replacement is limited to eight. By the way, this recursion count is stored in a recursion count memory 60 shown in FIG. 7, and a recursion count is provided corresponding to all sample data.

In the repeated W conversion determination circuit 57, the recursion counts of the sample data PI before the sample data to which error correction is applied, the sample data PPI of the upper line, and the position of PPOlPMI are determined, and are, for example, 7 or less, and the recursion count is the minimum recursion count. The position of the count is selected and a control signal is provided to the error correction method selector 5 to effect this repeated substitution. Also,
The recursion count of the selected position is sent from the repeat replacement determination circuit 57 to the recursion count generator 59. This recursive run count generator 59 is supplied with a signal indicating that the repetitive replacement has been selected in the error correction method selector 58, and when the repetitive replacement method is selected, the recursion count at the selected position is increased by 2.
is added, and this added recursion count is newly stored in the recursion count memory 60 as the recursion count at the position where the permutation has been performed. Note that when the recursion coefficients at the positions of the sample data P1, PPI, PPOlPMI are the same value, the sample data PI, ppo, ppi,
Priority is set in order for each position of PMI.

Here, a specific circuit configuration of the iterative replacement determining circuit 57 is shown in FIG. In this figure, comparators 110 to 113 include H-direction recursion counts of sample data P1, PPO, PPI, and PMI near sample data PO to which error correction is applied via terminals 100 to 103, respectively; ■Directional recursion counting, D. directional recursion count,
D one-way recursion counts are provided respectively. In these comparators 110 to 113, a comparison is made with the maximum value of the recursion coefficients that can be made externally variable, for example, 7, which is supplied via the terminal 104, and at least one recursion coefficient is set to 7. When it is smaller, a repeatable replaceable signal is taken from terminal 105 that allows repeatable replacement from NAND gate 114. Also,
Each of the above recursion counts is supplied to a recursion direction selection circuit 115,
In this recursion direction selection circuit 115, the position with the minimum recursion count is selected, and a signal indicating this position is taken out from the terminal 106. These repeatable replacement signals and signals indicating the position are supplied to the error correction method selector circuit 58 shown in FIG. 7 as control signals for performing the above-mentioned repeat replacement.

As described above, the optimal interpolation direction determining circuit 51, the high-precision temporal replacement determining circuit 52, and the optimal replacement direction determining circuit 5
3. Control signals for performing various error corrections from the arbitrary interpolation direction determination circuit 54, the low-precision temporal replacement determination circuit 55, the nearest neighbor replacement determination circuit 56, and the iterative replacement determination circuit 57 are supplied to the error correction method selector 58. Ru. In this error correction method selector 58, the optimum error correction method is selected based on the priority order (from top to bottom) shown in Table 2.

Table 2 The error rates in Table 2 indicate the applicable range of each error correction method, and indicate that a plurality of error correction methods can be applied to the same error rate. However, the error rate is not used to determine the error correction method, but the error correction method is determined by the state of the error flags (error pattern) around the sample data to be error corrected as described above. The error correction method is determined by the error correction method selector 58 as described above, and error correction is performed in response to a control signal from the error correction method selector 58.Each error correction method will be explained below.

When interpolation in the optimum interpolation direction is possible, a signal is sent from the error correction method selector 58 to control the selectors 64 and 66. In response to this control signal, the selector 64 selects one of the interpolated sample data (interpolated value P). That is, the selector 64 has the terminal 73
A weighted average value (interpolated value) P in the H direction obtained by the one-dimensional error correction circuit 2 shown in FIG.

Further, for example, the V interpolation circuit 61 is supplied with sample data PP01NPO above and below the sample data PO to be interpolated via terminals 74 and 75, and this
In the interpolation circuit 61, the interpolation value p ((PPO
+NPO)/2) is calculated, and this interpolated value P in the V direction is
is supplied to the selector 64.

Also, D, interpolated diagram N! Sample data PPI and NM1 on the downward diagonal line of the sample data PO to be interpolated are supplied to the interpolation circuit 62 through terminals 76 and 77, respectively, and the interpolation circuit 62 performs interpolation in the D direction. The value P ((PP1+NM1)/2) is calculated. The interpolated value P of the direction is supplied to the selector 64. The D-interpolation circuit 63 is supplied with sample data PMI and NPI on the diagonal line downward to the left of the sample data PO to be interpolated through terminals 78 and 79, respectively.
In this D-interpolation circuit 63, the interpolation value P(
(PM1+NP1)/2) is obtained, and this D one-way interpolation value P is supplied to the selector 64. As described above, the interpolation value P in each direction is supplied to the selector 64, and based on the control signal from the error correction method selector 5, the direction determined by the optimum interpolation direction determining circuit 51 (in which the correction error is the minimum direction) is selected, and the selector 66
It is output to terminal 8 via.

When high precision temporal replacement is selected in the error correction method selector 58, the selector 66 is controlled and the sample data LPO of the previous frame inputted via the terminal 88 is outputted to the terminal 8.

When the error correction method selector 58 selects the W replacement based on the optimal replacement direction, the selectors 65 and 66 are controlled, and the sample data PPI, PPO, PMI, PI, Ml inputted via the terminals 80 to 87, respectively.
.

When interpolation in an arbitrary interpolation direction is selected in the error correction method selector 58, the selectors 64 and 66 select ! l
J? 21, and among the interpolated values P in each direction inputted to the selector 64, the interpolated value P in the direction determined by the arbitrary interpolation direction determining circuit 54 is selected and outputted to the terminal 8 via the selector 66.

When low precision temporal replacement is selected in the error correction method selector 58, the selector 66 is controlled;
The sample data LPO of the previous frame, which is input manually via the terminal 88, is output to the terminal 8.

When nearest neighbor replacement is selected in error correction method selector 58, selectors 65 and 66 are controlled, and terminal 8
Sample data PPI, PPO, PMl, PI, Ml, NPI, N input via terminals 0 to 87, respectively.
The sample data determined by the nearest neighbor replacement determination circuit 56 is selected from the POSNMI and output to the terminal 8 via the selector 66.

When repeat replacement is selected in the error correction method selector 58, the selectors 65 and 66 are controlled, and the repeat replacement determining circuit 57 selects the sample data PPI, PPO1PM1, and PI input via the terminals 80 to 83, respectively. The determined sample data is selected and output to the terminal 8 via the selector 66.

Note that when the error correction method selector 58 determines that all of the above error correction methods cannot be used, default replacement is performed, and the selector 66 is controlled to replace the previous frame manually through the terminal 8. Sample data LPO is output to terminal 8.

As is clear from the above explanation, when error correction is performed by interpolation processing or W conversion processing, among the correction errors in each direction used to determine the direction of error correction, the errors on both sides of the error sample data are When at least one of the correction errors is larger than a predetermined threshold, this direction is excluded from the direction of error correction, which allows for more accurate prediction of the error correction result, which is different from conventional error correction. By comparison, better error correction can be performed.

By setting a threshold value for the output value of each correction accuracy output circuit shown in FIG. 1 (V correction error, H correction error, D. correction error, D-correction error), all correction errors are larger than this threshold value. In this case, interpolation processing using surrounding sample data may not be performed. The present invention also applies to a case where the circuit is simplified by using only one error calculation circuit for each correction accuracy output circuit so as to rank the direction of error correction using correction errors on only one side of error sample data. Can be applied.

H1 Effects of the Invention According to the video signal processing circuit according to the present invention, when performing error correction by interpolation processing, replacement processing, etc., when determining the direction of these corrections, correction errors on both sides of error sample data in any direction are detected. When at least one of the correction errors on both sides is larger than a predetermined threshold, the direction is excluded from the direction of error correction, and the correction errors in the remaining directions are compared with each other. do,
By setting the direction in which the correction error is minimum as the direction of optimal error correction, better error correction can be performed compared to conventional error correction.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of a video signal processing circuit according to the present invention (
2 is a block circuit diagram of an error correction device to which the video signal processing circuit according to the present invention is applied, FIG. 3 is a block circuit diagram of a one-dimensional error correction circuit, and FIG. 4 is a block circuit diagram of a one-dimensional error correction circuit. Figure 5 is a diagram showing the arrangement of sample data used in two-dimensional error correction, and Figure 6 is a two-dimensional error correction circuit. Diagram showing the arrangement of error flags used during error correction, No. 7
The figure is a block circuit diagram of a two-dimensional error correction circuit, No. 8 rf
! J and FIG. 9 are diagrams showing specific examples of repeated substitution, 1st
FIG. 0 is a block circuit diagram of the iterative replacement determination circuit. 41 ・ ・ ・ 42 ・ ・ ・ 43 ・ ・ ・ 44 ・ ・ ・ 45 ・ ・ ・ H modified precision output circuit V modified precision output circuit. Modified accuracy output circuit D--modified accuracy output circuit ranking determination circuit Figure 4 shows the error of ``>L date ``7.

Claims (1)

[Claims] In a video signal processing circuit that, when sample data of a video signal is supplied and the sample data is erroneous, corrects the error sample data using surrounding sample data, a plurality of correction error calculation means for calculating correction errors in a plurality of mutually different error correction directions using sample data of the correction error calculation means; 1. A video signal processing circuit comprising: direction ranking means for excluding correction error output values that are larger than a predetermined threshold value, comparing them with each other, and ranking the correction directions according to the comparison results.