JPH1079943A - Motion vector detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a motion vector detector which reduces erroneous detection of a motion vector, also reduces an operation amount that is needed to detect a motion vector and also decreases the size of a circuit of a hardware. SOLUTION: A motion vector detector which detects a motion vector by using a block matching method is provided with a 1st motion vector detecting means 100A which operates an estimated error by using high order bits of image data and detects a motion vector candidate group based on the operated result and a 2nd motion vector detecting means 100B which operates an estimated error by using the high order bits that correspond to the motion vector candidate group and low order bits of the bits and detects a motion vector in the motion vector candidate group based on the operated result, hierarchizes the search of motion vectors and detects a vector.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MPEG (Moving
The present invention relates to a motion vector detecting device for detecting a motion vector in compression coding of moving image data such as a Picture coding Experts Group.

[0002]

2. Description of the Related Art Conventionally, motion compensation prediction is one of the elemental technologies constituting a compression encoding technique for moving image data such as MPEG. In this motion compensation prediction, the current image is predicted assuming that a certain part of the current image has moved from another part of the previous image, and the direction and distance of the motion of the moving image are detected as a motion vector. As described above, in the motion compensation prediction, the amount of image data to be encoded is reduced by expressing the image information as a motion vector.

One method for detecting a motion vector is a block matching method. This block matching method refers to a current image (hereinafter, “encoding target image frame”).
Is divided into a plurality of small blocks composed of, for example, 16 × 16 pixels, and a region of a previous image (hereinafter, referred to as a “reference image frame”) most similar to the image of each small block is searched for. The motion vector of each small block is detected. The block matching method includes a full search method for performing a detailed search for everything within a range to be searched, and a simple search method for narrowing a search range in advance. This simple search method includes a telescopic search method and a simple search method. There is a two-step search method. In these search methods, a "prediction error" representing the degree of similarity between a small block image of an encoding target image frame and a certain region of a reference image frame is calculated, and the prediction error is evaluated to detect a motion vector. . The prediction error is an index that means that the smaller the value is, the higher the similarity is.

Hereinafter, with reference to FIGS. 18 and 19,
The full search method and the simple search method will be described. Here, FIG. 18 is an explanatory diagram for explaining the concept of the full search method.
FIG. 19 is an explanatory diagram for describing a method for detecting a motion vector by the simple search method (two-step search method). First,
The full search method is the most general method of calculating a prediction error for all regions within a range to be searched for a reference image frame, and searching for a region where the prediction error is minimized to detect a motion vector. For example, in FIG. 18, when trying to detect the motion vector of the small block 504 in the encoding target image frame 502, first, the block 50
It is assumed that a search block 503 having the same size as 4 is on the reference image frame 501.

Next, a position on the reference image frame 501 corresponding to the center position of the small block 504 is set as a reference point (hereinafter, referred to as a reference point).
(Referred to as "search reference point") 511 as -i
Search block 503 in search area 505B of + j pixels
Is moved in pixel units, and a prediction error representing the similarity between the block 504 and the search block 503 is sequentially calculated. Then, the position of the search block 503 at which the prediction error is minimized (hereinafter referred to as “search point”) is specified, and the relative position of the search point with respect to the search reference point is detected as the motion vector of the small block 504.

[0006] In contrast to the full search method, a simple search method such as a telescopic search method or a two-step search method is one of methods devised for the purpose of reducing the amount of computation. Are searched for some predetermined representative points, and the search range is narrowed down based on the search results. For example, the small block 5 shown in FIG.
As shown in FIG. 19, the range that any one pixel 03 can take (hereinafter referred to as “search range”) is -6 in both the vertical and horizontal directions with respect to the search reference point 511 of the reference image frame 501.
According to the two-step method, when the range 505 is set to the range 505 of +6 pixels, first, the search range 50 centered on the search reference point 511 is obtained.
From among the pixels in 5, 25 pixel points for every three pixels are selected as first representative points 512 (all pixel points indicated by numeral 1 in FIG. 18).

Next, a prediction error is calculated for the 25 first representative points 512, and one having the minimum prediction error is detected as a first search point 513 from the 25 first representative points. I do. Next, 24 pixel points within a range of −2 to +2 pixels in both the vertical and horizontal directions (hereinafter referred to as “secondary search range”) 505 </ b> A based on the first search point 513 are referred to as second representative points 51.
4 (pixel point indicated by numeral 2 in FIG. 18). Next, a prediction error is calculated for 24 second representative points 514 and one first search point 513 in the secondary search range 505A, and a pixel point having the minimum prediction error is calculated from these. It is determined as the second search point 515, and the relative position of the second search point 515 with respect to the search reference point 511 is detected as the motion vector of the small block 504 shown in FIG.

[0008]

However, according to the above-described full search method, when searching for a pixel point with a minimum prediction error, the prediction error is obtained for all the pixel points in the search area of the reference image frame. However, there is a problem that an enormous amount of calculation is required and the circuit scale of the hardware becomes extremely large.

Although the simplified search method reduces the amount of calculation for detecting a motion vector as compared with the full search method, if a wrong search point is selected in the initial search stage, the subsequent search The motion vector detected at the stage is different from the motion vector detected by the full search method, and there is a problem that coding efficiency is significantly reduced.

The present invention has been made in view of such a problem, and it is possible to reduce erroneous detection of a motion vector,
It is an object of the present invention to provide a motion vector detecting device capable of reducing the amount of calculation required for detecting a motion vector and reducing the circuit scale of hardware.

[0011]

Means for Solving the Problems The present invention has the following arrangement to achieve the above object. That is, claim 1
The motion vector detection device according to the invention described in (1), in a motion vector detection device that detects a motion vector using a block matching method, calculates a prediction error using the upper bits of the image data, the result of the calculation A first motion vector detecting means for detecting a motion vector candidate group based on the first and second bits, and a prediction error is calculated by using the upper bits and lower bits of the image data corresponding to the motion vector candidates. And a second motion vector detecting means for detecting a motion vector from the motion vector candidate group based on the result of the calculation.

According to a second aspect of the present invention, in the motion vector detecting apparatus according to the first aspect, the first and second motion vector detecting means determine the number of upper bits of the image data. A plurality of prediction error calculation means for inputting a bit string having a bit length and calculating a prediction error are provided in common, and the plurality of prediction error calculation means function independently of each other to form a first motion vector detection means. And a plurality of prediction error calculation means functioning vertically through a carry to calculate a prediction error as second motion vector detection means.

Further, the motion vector detecting device according to a third aspect of the present invention is the motion vector detecting device according to the second aspect, wherein the carry is generated by a ripple carry method.

Furthermore, a motion vector detecting device according to a fourth aspect of the present invention is configured such that, in the motion vector detecting device according to the second aspect, the carry is generated by a carry look ahead method.

Hereinafter, the operation of the present invention will be described. That is, according to the motion vector detecting device of the first aspect of the present invention, the first motion vector detecting means calculates the prediction error using the upper bits of the image data. And a plurality of pixel points are detected as a group of motion vector candidates. next,
The second motion vector detection means calculates a prediction error for image data corresponding to the group of motion vector candidates detected by the first motion vector detection means. In this case, in the second motion vector detecting means, in addition to the upper bits used in the first motion vector detecting means,
Since the calculation is performed using data including the lower bits, a more detailed prediction error is required.

According to the motion vector detecting device of the present invention, first, each of the plurality of prediction error calculating means functions independently, and uses the upper bit of the image data to perform the second processing. A prediction error is calculated as one motion vector detecting means. Then, the first motion vector detecting means selects, for example, a plurality of pixel points having a small prediction error based on the calculation result, and detects the plurality of pixel points as a motion vector candidate group. Next, each of the plurality of prediction error calculation means functions in a cascading manner via a carry, and the plurality of prediction error calculation means perform one prediction error calculation with an extended input data bit length. Configure means. The prediction error calculation means having an extended data bit length (a plurality of prediction error calculation means functioning subordinately)
A prediction error is calculated for image data corresponding to a group of motion vector candidates detected by the first motion vector detection means. In this case, the second motion vector detecting means performs the calculation using data including the lower bits in addition to the upper bits used in the first motion vector detecting means. A prediction error is determined.

Further, according to the motion vector detecting apparatus of the present invention, for example, each first prediction error calculating means assigned in order from the lower bit side to the upper bit side transmits the first prediction error calculating means from the lower side. The obtained carry is taken in, a prediction error is calculated, and the carry generated based on the calculation result is sent to the upper side. Thus, the plurality of first prediction error calculation means function subordinately via the carry, and function as second prediction error calculation means having an expanded data width.

Further, according to the motion vector detecting device of the invention, for example, the first prediction error calculating means assigned to the lower bit side includes all the prediction error calculating means assigned to the upper bit side. The carry is sent to one of the prediction error calculation means, and the first prediction error calculation means assigned to the upper side receives the carry from all the first prediction error calculation means on the lower side. Thereby, a plurality of first
The prediction error calculation means functions subordinately via the carry and functions as a second prediction error calculation means having an expanded data width.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first and second embodiments of the present invention will be described below with reference to FIGS. A motion vector detection device according to a second embodiment will be described. Here, FIG. 1 is a configuration diagram of the motion vector detection device of the first embodiment, and FIGS. 2 and 3 are detailed configuration diagrams of a first-stage motion vector detector that configures the device of the first embodiment. 4 and 5 are detailed configuration diagrams of a second-stage motion vector detector which also constitutes the device of the first embodiment, and FIGS.
It is operation | movement explanatory drawing of the apparatus of 2nd Embodiment. FIG. 9 is a configuration diagram of a motion vector detection device according to the second embodiment.
FIG. 10 to FIG. 17 are detailed configuration diagrams of each unit constituting the device of the second embodiment.

(First Embodiment) The apparatus according to the first embodiment shown in FIG. 1 uses the upper bits of the image data composed of the reference image data and the encoding target image data to determine each pixel point. , A primary motion vector detecting section 100A (first motion vector detecting means) for calculating a prediction error and detecting a motion vector candidate group based on the result of the calculation.
And calculating a prediction error using the upper and lower bits of the image data for the motion vector candidate group, and determining a motion vector candidate having the smallest prediction error from the motion vector candidate group based on a result of the calculation. And a secondary motion vector detecting section 100B (second motion vector detecting means) for specifying and detecting a motion vector.

Here, the primary motion vector detecting section 100A
Is a reference frame first memory 1 for storing reference image data.
01, a target frame first memory 102 for storing encoding target image data, and the reference frame first memory 101.
A first data controller 103 that controls reading of image data from the target frame first memory 102 and controls a first-stage motion vector detector 104 to be described later; 1
A first-stage motion vector detector 104 for obtaining a prediction error and a set of motion vector candidates using upper bits of the encoding target image data and the reference image data read from the memory 102; And a vector storage device 105 for storing the motion vector candidate group obtained by the detector 104 and the prediction error.

The secondary motion vector detecting section 100B
Is a reference frame second memory 1 for storing reference image data.
06, a target frame second memory 107 for storing encoding target image data, a reference frame second memory 106 and a target frame second memory 1 based on the motion vector candidate group and the prediction error stored in the vector storage device 105.
07, a second data controller 108 that controls reading of image data corresponding to the motion vector candidate group and controls a second-stage motion vector detector 109, which will be described later, and the reference frame second memory 106 and the target frame. Second
A second method of reading the encoding target image data and the reference image data from the memory 107 and detecting a motion vector,
And a step motion vector detector 109.

Here, the first-stage motion vector detector 10
4, a reference image data distributor 111 that cuts out upper two bits from the input 8-bit reference image data and outputs the cut-out two bits as one input of the operation unit group 113G, as shown in FIG. A coded image data distributor 112 that cuts out the upper 2 bits from the input 8-bit image data to be coded and outputs it as the other input of the subsequent operation unit group 113G; the reference image data distributor 111 and the coded image An operation unit group 113G for calculating a prediction error by using reference image data composed of upper two bits and image data to be encoded which are respectively input from the data distributor 112;
And a comparison selector 114 that selects the motion vector candidate group by comparing the magnitudes of the prediction errors obtained in (1). Here, the operation unit group 113G is composed of 36 operation units 113, and one operation unit 113 is assigned to each of 36 pixel points (first candidate points) shown in FIG. I have.

The arithmetic unit 113 shown in FIG.
As shown in detail in FIG. 3, a difference calculator 12 that calculates the difference between the input upper two-bit reference image data and the encoding target image data and outputs 3-bit difference data.
1, an absolute value calculator 122 for calculating the absolute value of the 3-bit difference data, a full adder 123 for adding the absolute value of the difference data to the contents of a register 124 described later, and an output of the full adder 123 Register 124 that holds
And the content of the register 124 is output as a prediction error which is a calculation result.

The second-stage motion vector detector 109 shown in FIG. 1 can handle 8-bit data as shown in detail in FIG. Different from the vector detector 104. That is, the second-stage motion vector detector 109 shown in FIG. 4 outputs a reference image data distributor 131 which outputs 8-bit reference image data per pixel to a group of operation units 133G described later.
And a target image data distributor 132 that outputs 8-bit encoding target image data per pixel to an operation unit group 133B, which will be described later; and the reference image data distributor 131 and the target image data distributor 132, An operation unit group 133G for inputting image data to be encoded and calculating a prediction error;
And a comparison selector 134 for detecting a motion vector based on the prediction error obtained in step (1). Here, the operation units 133 constituting the operation unit group 133G
, One group is assigned to each of the nine second candidate points shown in FIG.

Further, the operation unit 13 shown in FIG.
Reference numeral 3 denotes a difference calculator 141 for obtaining a difference between the input reference image data and the encoding target image data and outputting 9-bit difference data, as shown in FIG. Absolute value calculator 1 for calculating the absolute value of data
42 and the absolute value of the difference data
4 and a full adder 143 for adding the content of
And a register 144 for accumulatively storing the output.

The operation of the motion vector detecting device according to the first embodiment thus configured will be described with reference to FIGS.
This will be described in detail with reference to FIG. In addition, about a structure, FIGS. 1-5 are referred suitably. The device of the present embodiment is:
In detecting a motion vector, a pixel point (search point) having the smallest prediction error is searched. This search is performed in two stages. In the following description of the operation, first, a first-stage motion vector search is performed, and then, a second-stage motion vector search is sequentially performed.

The first stage motion vector search is performed by the primary motion vector detecting section 100A shown in FIG. 1 operating as follows. First, the reference frame first memory 1 shown in FIG.
01 and the target frame first memory 102 are controlled by the first data controller 103 to input reference image data as image data of the previous frame and encoding target image data as image data of the current frame, respectively. And store. Next, the first-stage motion vector detector 104
Under the control of the data controller 103, as shown in FIG.
For example, 36 pixel points within a search range 505C of -3 to +2 pixels in both the vertical and horizontal directions are set as first candidate points 152 (all the pixel points indicated by numerals 0 and 1 in FIG. 6), and the reference frame first memory 101 and The reference image data and the encoding target image data corresponding to the 36 first candidate points are read from the target frame first memory 102.

Next, the first-stage motion vector detector 104
Calculates the prediction error for the 36 first candidate points shown in FIG. 6 using the read reference image data and the upper two bits of the encoding target data. Then, as shown in FIG. 7, nine first candidate points (all pixel points indicated by numeral 2 in FIG. 7) are selected from the 36 candidate points in ascending order of prediction error, It is detected as a candidate point, that is, a motion vector candidate group. This detection result is stored in the vector storage device 105 together with the prediction error.

Here, the first-stage motion vector detector 10
Operation 4 will be described in further detail. In the first-stage motion vector detector 104 whose detailed configuration is shown in FIG. 2, the reference image data distributor 111 and the coded image data distributor 112 perform coding corresponding to the 36 first candidate points shown in FIG. The upper two bits of the image data and the reference image data are cut out, respectively, and the subsequent operation unit group 113G
Give to. Each of the 36 arithmetic units 113 assigned in association with each of the 36 candidate points,
From the reference image data distributor 111 and the target image data distributor 112 at the preceding stage, the upper two bits of the corresponding coded image data of the first candidate point and the reference image data are input.

At this time, in the arithmetic unit 113 having a detailed configuration shown in FIG. 3, the difference calculator 121 calculates the difference of the upper two bits between the reference image data and the image data to be encoded, and calculates the difference data of three bits. To the absolute value calculator 122
Give to. The absolute value calculator 122 calculates the absolute value of the difference data and supplies it to the full adder 123. Full adder 123
Adds the absolute value of the difference data provided from the absolute value calculator 122 to the previous addition result stored in the register 124 at the subsequent stage, and provides the addition result to the register 124 at the subsequent stage again. The register 124 updates the content by replacing the content with the content newly provided from the adder 123.

In this way, each arithmetic unit 113 shown in FIG. 2 sequentially inputs image data corresponding to all pixel points (36 first candidate points) in the search range 505C shown in FIG. As a result of the arithmetic processing, the absolute value of the difference data is cumulatively added to the register 124 of the arithmetic unit 113 shown in FIG. 3, and each arithmetic unit 113 outputs this as a prediction error. Each of these prediction errors is compared in magnitude by the comparison selector 114 shown in FIG. 2, and nine out of the 36 first candidate points are selected as the second candidate points in ascending order of the prediction error. This 9
The second candidate points are stored in the vector storage device 105 shown in FIG. 1 together with the prediction error as a group of motion vector candidates, and are subjected to a second-stage motion vector search described below.

Hereinafter, the second stage motion vector search will be described. This second-stage motion vector search is performed as shown in FIG.
Is performed by operating as follows. As described above, when a motion vector candidate group is selected as a result of the first-stage motion vector search in the primary motion vector search unit 100A, the second motion vector detection unit 100B shown in FIG. The two data controller 108 refers to the vector recording device 105, and stores the reference image data and the encoding target image data of each of the nine second candidate points 153 shown in FIG. Target frame first memory 10
2 to the reference frame second memory 106 and the target frame second memory 107.

When writing the contents of the reference frame first memory 101 and the target frame first memory 102 into the reference frame second memory 106 and the target frame second memory 107, the image data of the nine second candidate points is used. The present invention is not limited to this, and may be configured to write all. With this configuration, the second data controller 108 reads the nine second candidate points 153 when the second-stage motion vector detector 109 at the subsequent stage reads the image data of the necessary nine candidate points. The reference frame second memory 106 and the target frame second memory 107 are accessed by designating the address at which the image data is stored.

Next, the second-stage motion vector detector 109
Are the nine second candidate points 153 written in the reference frame second memory 106 and the target frame second memory 107.
A prediction error is calculated using all the bits (8 bits / 1 pixel) of the image data, and as shown in FIG. 8, one of the nine second candidate points 153 that minimizes the prediction error is searched. Point 1
It is specified as 54. Then, the specified search point 1
The motion vector is detected from the relative position between the search reference point 151 and the search reference point 151.

Here, the operation of the motion vector detector 109 will be described in more detail. The second-stage motion vector detector 109 having a detailed configuration shown in FIG. 4 uses the image data (8 bits / 1 pixel) of the nine second candidate points 153 shown in FIG. The same operation as the step motion vector detector 104 is performed to specify the search point 154 shown in FIG. That is, the arithmetic unit 133 shown in FIG. 4 that constitutes the second-stage motion vector detector 109 operates in the same manner as the above-described arithmetic unit 113, and outputs the accumulated prediction error. This prediction error is obtained by comparing the selector 1 shown in FIG.
34, the magnitude is compared with each other. One of the nine second candidate points having the smallest prediction error (second prediction error) is specified as the search point 154, and the relative position with respect to the search reference point 151 is determined. A motion vector is detected.

The above-described apparatus according to the present embodiment has a first
In the motion vector search at the stage, the prediction error is calculated for all the pixel points within the search range 505C. However, the candidate point may be thinned out at the search at the first stage. . In the first stage motion vector search, a search is performed using the upper two bits of image data, and in the second stage motion vector search, a search is performed using all bits (8 bits / pixel). However, the number of bits of image data used in each stage may be any distribution as long as the subsequent stage is large,
The number of stages may be further increased.

In the conventional two-step search or three-step search, which is a hierarchical search method, the detection accuracy of a motion vector is reduced due to the thinning out of candidate points. Is searched for all candidate points while increasing the number of effective bits of the image data step by step, so while reducing the scale of hardware,
At the same time, high detection accuracy can be maintained.

(Regarding the Second Embodiment) Next, FIG.
A motion vector detecting device according to a second embodiment of the present invention will be described with reference to FIGS. The device of the present embodiment shown in FIG. 9 performs the detection of the motion vector in a stepwise manner, similarly to the device of the first embodiment described above. It is characterized in that the arithmetic unit and the arithmetic unit used in the second stage search are shared.

That is, the apparatus of this embodiment shown in FIG. 9 has a reference frame memory 161 for storing reference image data and a target frame memory 162 for storing encoding target image data.
A data controller 163 for controlling reading of image data from the reference frame memory 161 and the target frame memory 162 and for controlling a multi-stage motion vector detector 164 described later; and the reference frame memory 161 and the target frame memory 162 A multi-stage motion vector detector 164 that reads out the encoding target image data and the reference image data from the CPU and obtains a prediction error and a motion vector, and a vector that stores the motion vector and the prediction error obtained by the multi-stage motion vector detector 164 The storage device includes a storage device 166 and a multi-stage vector detection controller 165 for controlling the operation of the multi-stage motion vector detector 164.

Here, a multi-stage motion vector detector 164 shown in FIG. 9 is a reference image data distributor which outputs input reference image data to a later-described operation unit group 173G, as shown in FIG. 171, a target image data distributor 172 that outputs the input encoding target image data to each of the operation unit groups 173 </ b> G described later, the reference image data distributor 171 and the reference image data and codes input from the target image data distributor 172. The operation unit group 173G that calculates the prediction error from the image data to be converted and the prediction error obtained by the operation unit group 173G are compared with each other.
Comparison arithmetic unit 1 for detecting one or more motion vectors
74. Here, the operation unit group 173G includes a plurality of operation units 17, as described later.
3 is comprised.

The operation unit 173 shown in FIG.
As shown in FIG. 11, the upper two bits of encoding target image data and reference image data for four pixels input in a time-division manner are referred to as
Calculation and input / carry controller 1 for relaying image data to a difference calculator group 183G to be described later and relaying carry.
82, a group of difference calculators 183G for calculating a difference between the input coded image data and the reference image data and outputting 3-bit difference data, and a group of absolute value calculators 184G for calculating the absolute value of the difference data. The adder input / relay relays the carry of the adder group 186G, which will be described later, and relays the absolute value of the difference data output by the absolute value calculator group 184G.
A carry controller 185, an adder 186 that adds the absolute value of the difference data relayed to the adder input / carry controller 185 to the contents of a register group 187G described below, and stores the addition result of the adder group 186G. Register group 18
7G, and an integration unit 188 that controls the outputs of the register group 187G and outputs the sum of absolute differences. The bit slice control group 181G is composed of two bit slice control units 181 that cut out the upper two bits of the reference image data of four pixels input in a time-division manner and the upper two bits of the image data to be encoded, and output them. I have.

Here, a group of difference calculators 183G, a group of absolute value calculators 184G, a group of adders 186G, and a group of registers 18
7G, a difference calculator 183, an absolute value calculator 184, an adder 186a or 186b, and a register 18
A series of paths formed by 7 form a prediction error calculation unit (prediction error calculation means). Further, the difference arithmetic unit group 183
When the four difference calculators 183 constituting G are connected in a cascaded manner via a carry, the difference calculators 183 form one difference calculator having an input bit width extended from 2 bits to 8 bits. Function. Similarly, in each group of the absolute value calculator group 184G, the adder group 186G, and the register group 187G, when the respective components are connected in cascade via the carry,
The above-described prediction error calculation unit is connected vertically via a carry, and functions by extending the input bit width from 2 bits to 8 bits. When the carry is not relayed, the constituent elements of each group function independently, and the prediction error calculation unit functions independently.

For example, the adder 186 forming the adder group 186G shown in FIG. 11 divides 8-bit data input from the outside into upper 6 bits and lower 2 bits as shown in FIG. A distributor 191 for inputting each to a half adder 192 and a full adder 193, which will be described later,
Half adder 192 for calculating the sum of 6-bit data distributed from distributor 191 and 1-bit carry from full adder 193, lower 2-bit data distributed from distributor 191 and 2-bit externally input And a full adder 193 for calculating the sum with the data.

As shown in the figure, when each adder 186 constituting the adder group 186G functions independently, the carry from the lower side is forcibly fixed to "0" and the 8-bit data is Functions as an adder for the 2-bit data. In addition, in the case of functioning by being connected in cascade via a carry, the configuration of the adder group 186G shown in FIG. 12 is equivalently modified to the configuration shown in FIG. That is, in this case, the carry generated by the full adder 193 constituting the adder 186 is given to the upper full adder 193, and the four adders 186 are connected in cascade via the carry.
In this case, except for the top adder 186, the half adder 1
The output 92 is ignored, and 2-bit data input from outside is added to the lower 2 bits of 8-bit data input from outside to output 2-bit data. The carry input to the lowest adder 186 is forcibly fixed to "0".

As described above, as a result of connecting the four adders 186 in cascade via the carry, the uppermost adder 18
6 except for the 8-bit data input from the outside to the distributor 191 of the 6th adder 186.
Since only the lower 2 bits of the 8-bit data input from outside are valid, the adder group 186G consequently generates the 14-bit data and the 8-bit data as shown in FIG. Function as one adder for adding 14 bits to output 14-bit data.

Further, two bit slice control units 181 constituting the bit slice control group 181G shown in FIG.
As shown in FIG. 14A, a distributor 201 divides input 8-bit data into four 2-bit data in order from the lower bit side, A switch group 202G that switches to and outputs either one of the three systems on the side or one of the highest systems, and the two bits of the highest system divided by the distributor 201 and the outputs of the three switches 202. And a register group 203G for inputting and holding each of them.

Further, the integrating unit 188 shown in FIG. 11 includes, as shown in detail in FIG. 15A, a switching unit 211 for selecting and switching one system from among the inputted four 8-bit data, A switch 212 that selects and switches the lower 2 bits or 0 of the lower 3 systems of 8-bit data from the 4 systems of 8-bit data, and a register 213 that holds the outputs of the switches 211 and 212 Have been.

Hereinafter, similarly to the above-described first embodiment,
As shown in FIG. 6, the search range of the motion vector in the vertical and horizontal directions is a range 505 of -3 to +2 pixels with respect to the search reference point 151.
C, the image data is composed of 8 bits per pixel, and the size of the divided small block is 8
× 8 pixels, and a multi-stage motion vector calculator 1 shown in FIG.
The operation of the apparatus according to the present embodiment will be described in detail by taking, as an example, a case where 64 has nine arithmetic units 173. In the description, the above-described FIG. 6 to FIG. 8 are used as necessary.

As will be described in detail below, the apparatus of this embodiment calculates a prediction error using the upper two bits of the image data for all candidate points in the first-stage motion vector search. The points are narrowed down to nine points, and in the second stage motion vector search, prediction errors are calculated for the nine candidate points narrowed down in the first stage search, and finally one candidate point (search point ) To perform a search.

First, in the first stage motion vector search,
A prediction error is calculated for the 36 first candidate points 152 shown in FIG. That is, the multi-stage motion vector detector 164 illustrated in FIG. 9 detects a motion vector candidate group using the upper two bits of each of the reference image data and the encoding target image data. At this time, as shown in FIG. 10, the prediction error calculation corresponding to the four first candidate points 152 is assigned to one operation unit 173, and by using all the nine operation units 173, a total of 36 First candidate points 15
The calculation of the prediction error of No. 2 is performed in parallel.

In the motion vector search at the first stage, the bit slice control section 181 shown in FIG. 11 sequentially assigns the upper two bits of the reference image data and the encoding target image data for four pixels input in a time-division manner. It is cut out and given to a difference calculation input / carry controller 182 at the subsequent stage. At this time, the bit slice control unit 181
The state of the switch group 202G shown in FIG. 11A is controlled such that the configuration of the bit slice control unit 181 shown in detail in FIG. 10A is equivalent to the configuration shown in FIG. As a result, the distributor 201 sets the bit slice control unit 181
The upper two bits of the 8-bit data input to the register 203 are cut out, and this is commonly input to the register 203 at the subsequent stage.

The input of the image data to the bit slice control unit 181 is performed by time-dividing the image data to be encoded and the reference image data for four pixels into four times, respectively. , The upper two bits of each image data for four pixels are held in a register group 203G composed of four registers and output to the difference calculation input / carry controller 182 shown in FIG.

Next, as shown in FIG. 16A, the difference calculation input / carry controller 182 shown in FIG. 11 has an input terminal group [a0, a1, b0, b1, c0, c1, d0,
d1], and relays the four sets of 2-bit reference image data and coded image data input to the output terminal group [a].
2, a3, b2, b3, c2, c3, d2, d3], and supplies the result to the difference calculator group 183G at the subsequent stage. At this time, the carry input terminals [b5, c4, d4] are not relayed, and the carry output terminal groups [a5,
b5, c5], “0” is output, and each difference calculator 183 functions independently.

Each of the difference calculators 183 shown in FIG. 11 receives the upper two-bit reference image data and the coded image data for four pixels, calculates the difference, and outputs the three-bit difference data at the subsequent stage. It is given to the absolute value calculator 184. The absolute value calculator 184 calculates the absolute value of the input 3-bit difference data, and supplies the result to the subsequent adder input / carry controller 185 as 2-bit absolute value data. At this time, the carry between the absolute value calculators 184 in FIG. 9 is not used, and each absolute calculator 184 functions independently.

Next, the input and carry controller 185 for the adder shown in FIG. 17 has an input terminal group [e0, e1, f0, f1, g0, g1, h0, h] as shown in FIG.
1] is output to the output terminal group [e2,
e3, f2, f3, g2, g3, h2, h3], and provides it to the subsequent adder group 186G. At this time, the carry input to the carry input terminal group (f4, g4, h4) is not relayed, and the carry output terminal group [e5, f5, g5] is not relayed.
Forcibly outputs "0" to each of the adders to function independently. As a result, each adder 186 shown in FIG. 11 calculates the sum of the output (2 bits) of the absolute value calculator 184 and the output (8 bits) of the register 187, and the calculation result is accumulated in the register 187. . The accumulation result of each register 187 becomes the prediction error of the corresponding candidate point. That is, the prediction errors of the four candidate points are stored in the four registers 187.

The integrating unit 188 shown in FIG.
The switching units 211 and 212 are configured such that the configuration of the integration unit 188 illustrated in FIG. 5A is equivalent to the configuration illustrated in FIG.
Is controlled. That is, as shown in FIG. 7B, the integrating unit 188 selects only one system from the input four-system 8-bit data by the switch 211 and inputs the selected system to the upper eight bits of the register 213. Also, register 2
"0" is input to the lower 6 bits of the upper 13 bits and
These are connected to the bits to form a 14-bit output (sum of absolute values of differences) of the arithmetic unit 173 shown in FIG. By repeating this four times, the sum of absolute values of the differences as the prediction errors of the four candidate points is sequentially output from each arithmetic unit 173 shown in FIG.

Therefore, when four prediction errors are output from each of the nine arithmetic units 173, prediction errors are obtained for all 36 candidate points. From these candidate points, the comparison selector 174 shown in FIG.
As a result, nine candidate points are selected in ascending order of prediction error, and these nine candidate points are used as second candidate points 153 shown in FIG. 7 which are search targets in the second-stage motion vector search.
The first-stage motion vector search ends.

Next, a second-stage motion vector search is performed on the nine second candidate points 153 obtained in the above-described first-stage motion vector search. In the motion vector detection at the second stage, the prediction error is calculated for the nine second candidate points 153 shown in FIG. 7, and the candidate point with the minimum prediction error is specified, and the search point 154 shown in FIG. And a motion vector is detected.

Hereinafter, the second stage motion vector search will be described. First, one arithmetic unit 1 shown in FIG.
The calculation of the prediction error of one second candidate point 153 is assigned to 73, and the calculation of the prediction error of the nine second candidate points 153 is performed by nine operation units 173. That is, the difference operation unit group 183G and the adder group 18 of the operation unit 173 in FIG.
6G and the registers in the register group 187G are connected in a cascaded manner via a carry so as to function so as to calculate a prediction error for one second candidate point 153. At this time, the calculation of the prediction error is performed using all the bits (8 bits / 1 pixel) of the image data, and among the prediction errors of all nine candidate points shown in FIG.
The magnitude of the prediction error is compared by the comparison selector 174 shown in (1), the candidate point with the smallest prediction error is specified, and the final motion vector is detected.

The details will be described below. First, in the motion vector search at the second stage, the bit slice control unit 181 shown in FIG.
The reference image data of the pixel) and the image data to be encoded are divided into four groups of two bits from the upper side, and are input to the differential calculation input / carry controller 182 at the subsequent stage. At this time, the bit slice control unit 181 controls the state of the switch group 202G so that the configuration of the bit slice control unit 181 shown in FIG. 14A is equivalent to the configuration shown in FIG. Out of the input 8-bit data,
The register group 20 of the subsequent stage is divided every two bits from the upper side.
Output to each register constituting 3G.

The input / carry controller for difference calculation 182 shown in FIG. 11 has an input terminal group [a0, a1, b0, b1, c0, c1, d0,
d1], the four sets of 2-bit reference image data and the encoding target image data are relayed and output terminal groups [a2, a3, b2, b3, c2, c3, d2, d]
3], and is provided to the difference calculator group 183G at the subsequent stage.

The difference calculation input / carry controller 182 inputs the carry output of each difference calculator 183 to the carry input terminal group (b4, c4, d4), and outputs the carry output terminal group (a5 , B5, c5). As a result, the carry from the lower side is transmitted to the upper side by the ripple carry method, and the four difference calculators 183 function in cascade and operate as one 8-bit calculator. Difference operation unit group 1 functioning in this manner
The 83G performs an 8-bit difference operation using all bits (8 bits / 1 pixel) of the reference image data and the encoding target image data, and outputs the operation result to the absolute value operation unit group 18 in the subsequent stage.
Give to 4G.

The absolute value calculator group 184G calculates the absolute value of the difference data given from the preceding difference calculator group 183G, and supplies it to the subsequent input / carry controller 185 for the adder. At this time, the four absolute value calculators 184 are subordinately connected to each other via the carry, and function as one absolute value calculator. At this time, the input / carry controller 185 for the adder shown in FIG. 11 outputs the input terminal group [e0, e1, f0, f1, g0, g, as shown in FIG.
1, h0, h1] is directly output to the output terminal group [e2, e3, f2, f3, g2, g3, h2, h
3] to the adder group 186G at the subsequent stage.

The carry output of the adder group 186G at the subsequent stage is input to the carry input terminal group [f4, g4, h4], and is output from the carry output terminal group [e5, f5, g5]. Is transmitted to the adder 186 on the upper side by the ripple carry method, and the adder group 1
The four adders 186 constituting the 86G are made to function vertically as one adder.

That is, the adder group 186G shown in FIG.
As shown in FIG. 13A, the four adders 186 are subordinately coupled via a carry, and function as one adder with an expanded bit width. Here, the three adders 186 that perform the operation of the lower bits operate as full adders of the 2-bit data, and the uppermost adder 186 that performs the operation of the upper 2 bits is 8
It operates as an adder for bit data and 2-bit data. In this way, the adder group 186G functions as a single adder having 14-bit and 8-bit inputs and a 14-bit output, as shown in FIG. 13B as a whole.

The 14-bit output of the adder group 186G is stored in the register group 187G shown in FIG.
At this time, each of the four registers 187 shown in the figure uses only 8 bits, 2 bits, 2 bits, and 2 bits from the upper side, and operates as a 14-bit register as a whole. Therefore, in FIG. 11, the adder group 186G and the register group 1 which are subordinately integrated via the carry
87G functions as an accumulator of 8-bit input,
This accumulation result becomes a prediction error of the candidate point of the input image data.

The integrating unit 188 shown in FIG.
The states of the switches 211 and 212 are controlled so that the configuration of the integration unit 188 shown in detail in FIG. 5A is equivalent to the configuration shown in FIG. The output of the working register group 187G is
Register 2 constituting integration unit 188 shown in FIG.
13 and this is the arithmetic unit 17 shown in FIG.
As an output (prediction error) of the comparator 174 shown in FIG.
Given to. Then, the comparator 174 compares the magnitudes of the prediction errors given from the nine operation units 173 at the preceding stage, identifies a candidate point having the smallest prediction error as the search point 515 shown in FIG. calculate. This motion vector is stored in the vector storage device 166 shown in FIG. 9, and the vector storage device 166 stores the motion vector of each small block of the image and stores the motion vector information of each image frame.

As described in detail above, in the second embodiment, the carry / ripple method is used by using the input / carry controller 182 for difference calculation and the input / carry controller 185 for addition shown in FIG. , The prediction error calculation unit constituted by the difference calculation unit 183, the absolute value calculation unit 184, and the adder 186 is subordinately integrated. In particular, the transmission method of the carry is the ripple carry method. The present invention is not limited to this. For example, it is also possible to use a carry look ahead method that performs carry processing in advance for the purpose of high-speed calculation.

In the first and second embodiments described above, the search for the candidate point is performed in two stages when detecting the motion vector. However, the number of stages may be further increased. Further, in the above-described second embodiment, the arithmetic unit 173 is configured by four difference arithmetic units 183, but the present invention is not limited to this, and an appropriate number of arithmetic units may be selected according to the structure of the target image data. What is necessary is just to provide a difference arithmetic unit.

[0071]

As described above, according to the present invention,
The following effects can be obtained. That is, according to the first aspect of the present invention, first, a motion vector candidate group is detected using only upper bits of image data, and a more detailed prediction error calculation is performed on the motion vector candidate group. With this configuration, the amount of calculation for searching for a motion vector can be significantly reduced.

In addition, at the initial stage, only the upper bits of the image data are used, and the prediction error calculation process is performed using more bits as the motion vector candidate group is narrowed down. Even if the number of bits of the image data is reduced at the stage, there is almost no influence on the detection accuracy of the motion vector, and erroneous detection of the motion vector can be effectively prevented.

Further, according to the present invention, in the first search and the subsequent search stages, one prediction error calculation unit is commonly used and operated. Therefore, the hardware scale can be reduced without lowering the motion vector detection accuracy.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a motion vector detection device according to a first embodiment.

FIG. 2 is a configuration diagram of a first-stage motion vector detector included in the motion vector detection device according to the first embodiment.

FIG. 3 is a configuration diagram of an arithmetic unit configuring a first-stage motion vector detector of the motion vector detection device according to the first embodiment.

FIG. 4 is a configuration diagram of a second-stage motion vector detector included in the motion vector detection device according to the first embodiment.

FIG. 5 is a configuration diagram of an arithmetic unit configuring a second-stage motion vector detector of the motion vector detection device according to the first embodiment.

FIG. 6 is an explanatory diagram for explaining an operation of the motion vector detection device according to the first and second embodiments.

FIG. 7 is an explanatory diagram for explaining an operation of the motion vector detection device according to the first and second embodiments.

FIG. 8 is an explanatory diagram for explaining an operation of the motion vector detection device according to the first and second embodiments.

FIG. 9 is a configuration diagram of a motion vector detection device according to a second embodiment.

FIG. 10 is a configuration diagram of a multi-stage motion vector detector included in the motion vector detection device according to the second embodiment.

FIG. 11 is a configuration diagram of an arithmetic unit included in a motion vector detection device according to a second embodiment.

FIG. 12 is a configuration diagram of a group of adders forming an operation unit of the motion vector detection device according to the second embodiment.

FIG. 13A is a configuration diagram of a group of adders constituting an operation unit of the motion vector detection device according to the second embodiment. FIG. 2B is a diagram showing the circuit configuration shown in FIG.

FIGS. 14A to 14C are configuration diagrams of a bit slice control unit included in an arithmetic unit of the motion vector detection device according to the second embodiment.

FIGS. 15A to 15C are configuration diagrams of an integration unit configuring an arithmetic unit of the motion vector detection device according to the second embodiment.

FIGS. 16 (a) and (b) are explanatory diagrams of the operation of a difference calculation input / carry controller constituting an operation unit of the motion vector detection device according to the second embodiment.

FIGS. 17 (a) and (b) are explanatory diagrams of the operation of an adder input / carry controller constituting an operation unit of the motion vector detection device according to the second embodiment.

FIG. 18 is an explanatory diagram for explaining the concept of the block matching method.

FIG. 19 is an explanatory diagram for describing a method for detecting a motion vector by a simple search method.

[Explanation of symbols]

 100A Primary motion vector detection unit 100B Secondary motion vector detection unit 101 Reference frame first memory 102 Target frame first memory 103 First data control unit 104 First stage motion vector detector 105 Vector storage device 106 Reference frame second memory 107 Target frame second memory 108 Second data control unit 109 Second stage motion vector detector 161 Reference frame memory 162 Target frame memory 163 Data control unit 164 Multi-stage motion vector detector 165 Multi-stage motion vector detection controller 166 Vector storage apparatus

Claims (4)

[Claims] 1. A motion vector detecting apparatus for detecting a motion vector by using a block matching method, wherein a prediction error is calculated using upper bits of image data, and a motion vector candidate group is detected based on the calculation result. A first motion vector detecting unit that calculates a prediction error using the upper bits and lower bits of the image data corresponding to the motion vector candidate group, based on a result of the calculation. And a second motion vector detecting means for detecting a motion vector from the motion vector candidate group. The first and second motion vector detection means share a plurality of prediction error calculation means for inputting a bit sequence having a bit length of the number of upper bits of image data and calculating a prediction error. The plurality of prediction error calculation means function independently of each other to calculate a prediction error as first motion vector detection means, and the plurality of prediction error calculation means The motion vector detecting device according to claim 1, wherein the motion vector calculating device calculates a prediction error as a second motion vector detecting means. 3. The motion vector detecting device according to claim 2, wherein the carry is generated by a ripple carry method. 4. The motion vector detecting device according to claim 2, wherein the carry is generated by a carry look ahead method.