JPH03165375A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To enable the execution of most satisfactory error correction over a wide range as much as possible by using corrected sample data for the correction processing of error sample data and varying an upper limit value in the number of times for repeating the correction. CONSTITUTION:To the sample data and an error flag supplied to an input terminal 1, the error correction is executed concerning a horizontal direction by a one-dimensional error correcting circuit 2. Next, the respective sample data of lines are supplied to a two-dimensional error correcting circuit 3 corresponding to the current line, upper line, lower line and current line before one frame from the circuit 2 and line delay circuit 4-6. Then, the error correction is executed by a control signal, etc., from a ranking control circuit 7. A threshold value in the number of times for repeating the correction to be set to the ranking control circuit 7 can be set from an external part and made variable. Thus, since the number of times for repeating a repeated replacement processing using the sample data, to which the error correction is already executed, is controlled, the error correction can be executed corresponding to the kind of a picture, etc.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B1 Overview of the invention C0 Prior art 1 Problem to be solved by the invention E0 Means for solving the problem F2 Effect G. Example G-1. Basic configuration (Fig. 1) G -20 Configuration of the entire error correction device to which the present invention is applied (
(Figure 2) G-3, One-dimensional error correction circuit (Figures 3, 4) G-4, Two-dimensional error correction circuit (Figures 1, 5 to 11) B1 Effects of the invention A, INDUSTRIAL APPLICATION FIELD The present invention relates to a video signal processing circuit, and more particularly to a video signal processing circuit for correcting errors in a video signal.

B1 Summary of the Invention The present invention provides a counter that counts the number of times correction is repeated when corrected sample data is used for error correction in a video signal processing circuit that corrects errors in error sample data of sample data of a video signal. By providing a means to prevent corrections that would cause the count value from this counting means to exceed a predetermined upper limit value, and by making this upper limit count value variable, errors using already corrected data that are possible even at high error rates can be prevented. In addition to making corrections, the error correction format can be made variable by changing the upper limit of the number of times the correction is repeated, for example, depending on video and still images, fast-moving screens and slow-moving screens, or error rates. The system is designed to perform optimal error correction.

C9 Prior Art For example, error correction processing using an error correction code is performed for errors in sample data of a video signal reproduced from a VTR (video tape recorder). Furthermore, for the sample data that could not be corrected by these error correction processes, error correction (error 6M I am doing some sorting.

This error correction is performed in the video signal processing process, after error detection and error correction processing, but before outputting the videotape, and takes advantage of the inherent redundancy of video images to correct uncorrectable errors. A new value of the error sample data is created by interpolation, replacement, etc.

Here, the error correction method Mh for correcting incorrect sample data (error sample data) is interpolation (horizontal (I() direction) using sample data on both sides in the same line of error sample data. method of interpolation (interpolation in the vertical (V) direction) using sample pigs at the same position on the upper and lower lines J2 of the error sample data, neighboring sample data in the downward diagonal direction of the error sample data A method of interpolation using (D, direction interpolation), a method of capturing using neighboring sample data on the diagonal line downward to the left of the error sample data (D one-way interpolation), a previous frame with high temporal correlation. (or field) with error-free sample data fl
A method of replacing error sample data with neighboring sample data, etc. are known.

D1 Problem to be Solved by the Invention By the way, when the error rate of sample data reproduced from a VTR is extremely high, most of the sample data used for interpolation processing and replacement processing will be in an error state, and the normal interpolation processing and replacement processing described above will be in an error state. Processing may not be possible.

However, in actual error correction, it is desired to function over a wide range of uncorrectable error rates, for example, from virtually 0% during normal playback to approximately 100% during high-speed tape gloss. .

The present invention was made in view of the above-mentioned circumstances, and even when the error rate is very high, approximately 100%,
The objective is to facilitate a video signal processing process that provides the best possible error correction.

E3 Means for Solving Problem The video signal processing circuit according to the present invention is provided with sample data of a video signal, and when the sample data has an error, performs correction processing on the error sample data using other sample data. and a counting means for counting the number of times the correction is repeated when the already corrected sample data is used for the correction processing of the error sample data, and the count value from the counting means exceeds a predetermined upper limit value. Do not make any modifications that exceed the above.
The above problem is solved by making the limit count value variable.

By using F1 effect corrected video sample data,
Error correction is possible even at a high error rate, and the form of error correction is made variable by changing the upper limit of the number of repetitions of correction (that is, the number of recursive corrections).

G. Embodiment Hereinafter, an embodiment of a video signal processing circuit according to the present invention will be described with reference to the drawings.

G-1, Basic configuration (Figure 1) For example, for errors in sample data of a video signal reproduced from a VTR (video tape recorder), error correction processing is performed using an error correction code, etc. . Furthermore, for sample data that could not be corrected by these error correction processes (error sample data), interpolation processing and replacement processing using sample data without errors (error-free sample data), and further error correction have already been performed. Replacement processing using sample data is performed.

FIG. 2 shows a block circuit diagram of the entire error correction device that performs these interpolation processes and replacement processes. As shown in FIG. 2, the interpolation processing and replacement processing are performed using one-dimensional error correction (one-dimensional error correction circuit 2 ) and a two-dimensional error correction circuit (two-dimensional error correction circuit 3) that performs error correction using sample data around the error sample data to which error correction is applied.

A specific configuration of the two-dimensional error correction circuit 3 is shown in FIG. As shown in Figure 1, two-dimensional error correction is
A part that performs interpolation processing using error-free sample data around error sample data inputted through terminals 73 to 79 (optimum capture direction determination circuit 51, arbitrary interpolation direction determination circuit 54, error correction method selector 5) Day,
A section that performs replacement processing using error-free sample data around error sample data input manually via terminals 80 to 87 (composed of interpolation circuits 61 to 63 and selectors 64 and 66) (consisting of a replacement direction determining circuit 53, a nearest neighbor determining circuit 56, an error correction method selector 5, and selectors 65 and 66), and the error sample data of the previous frame inputted through the terminal 8B. Part that performs temporal replacement processing (high school 4th grade)
11 degree temporal replacement determination circuit 52, low integration temporal replacement determination circuit 55, error correction method selector 58, and selector 66), and a sample that has already been subjected to error correction manually input through terminals 80 to 87. A part that performs replacement processing using data (repetitive replacement determination circuit 5
7, a recursion count generation circuit 59, a recursion count memory 60, an error correction method selector 58, and selectors 65 and 66).

In the video signal processing circuit according to the present invention, correction processing (particularly replacement processing) is performed using sample data that has already been subjected to the above error correction in this two-dimensional error correction circuit.
I am trying to do this repeatedly and recursively.

G-24 Overall configuration of error correction device to which the present invention is applied (
FIG. 2) FIG. 2 shows the overall configuration of an error correction device to which the present invention is applied. In this FIG. 2, the input terminal 1 has, for example,
Sample data of a video signal after error correction processing and the like are applied to a reproduced video signal from a VTR (video tape recorder) and an error flag corresponding to the sample data are supplied.

Normally, this manual sample data includes error sample data that could not be completely corrected by the error correction process, and the error flag is used to identify these error sample data. These error flags are set in the error correction processing circuit when there is an error in the sample data.
''), and when there is no error in the sample data, it is in the recent state (Oj).

These sample data and error flags are supplied to a one-dimensional error correction circuit 2, where error correction (one-dimensional error correction) in the horizontal direction (line direction) is performed. The sample data subjected to one-dimensional error correction is supplied to a two-dimensional error correction circuit 3, a line delay circuit 4, and a ranking control circuit 7.

The two-dimensional error correction circuit 3 includes the one-dimensional error correction circuit 2.
Sample data from the line delay circuit 4 delayed by one line (lH-1 horizontal scanning period) with respect to the output of , sample data from the line delay circuit 5 delayed by two lines with respect to the output of the one-dimensional error correction circuit 2 Sample data from a frame delay circuit 6 delayed by one frame (IF=2 vertical scanning times) with respect to the output of the line delay circuit 4 is supplied. That is, based on the sample data from the line delay circuit 4, the one-dimensional error correction circuit 2
The sample data from the frame delay circuit 6 is delayed by lH, the sample data from the line delay circuit 5 is delayed by lH, and the sample data from the frame delay circuit 6 is delayed by IF. In other words, each sample data of the current line, the upper line, the lower line, and the line corresponding to the current line one frame before is supplied to the two-dimensional error correction circuit 3.

In this two-dimensional error correction circuit 3, the above four lines F
Optimal error correction is performed using the sample data. That is, this two-dimensional error correction circuit 3 performs, for example, interpolation processing in multiple directions, replacement processing for replacing error sample data using sample data at the same position in the previous frame, and replacement processing for error sample data using neighboring sample data. It has various error correction functions such as replacement processing, and in this two-dimensional error correction circuit 3, the control signal (ranking flag to be described later) from the ranking control circuit 7 is used to select the data that has the least change from neighboring sample data. In other words, the ranking control circuit 7 is supplied with sample data and each error flag from the one-dimensional error correction circuit 2 and the line delay circuit 4.5, and the ranking control circuit 7 In this step, the optimum two-dimensional error correction direction is determined based on each sample data and each error flag, and this result is supplied to the two-dimensional error correction circuit 3 as a control signal.

By the way, each of the above input sample data is, for example, 8-bit,
It consists of a node and takes values from [01) to "FE" in hexadecimal, and the above-mentioned error correction is performed by performing calculations and judgments on these 8 and node data. Note that the sample data after error correction is "00" in 16a.
” to “FF”. Also,
In the case of a color video signal, error flags corresponding to, for example, sample data of a luminance signal, sample data of a color difference signal, and each sample data of the luminance signal and color difference signal are supplied to a terminal l for one pixel. At this time, the sampling frequency of the luminance signal is twice the sampling frequency of the color difference signal, and the sample data of the luminance signal has a wider band and contains more detailed information than the sample data of the color difference signal. That is, the sample data and error flag of the luminance signal have good predictability for determining the direction of error correction for error correction of the luminance signal and color difference signal. Therefore, sample data of the luminance signal and error flags are typically used to determine the optimal error correction direction. Note that when the error flag of the luminance signal and the error flag of the color difference signal for one pixel are different, the error correction of the luminance signal and the error correction of the color difference signal are respectively performed in the optimal direction.

As described above, error correction is performed on the error sample data that could not be corrected in the previous error correction process.

(, -3, One-dimensional error correction circuit (FIGS. 3 and 4) Details of the one-dimensional error correction circuit 2 shown in FIG. 2 will be explained with reference to FIGS. 3 and 4.

As shown in FIG. 3, the one-dimensional error correction circuit is a variable length error correction circuit that performs error correction using the weighted average value of a plurality of sample data on both sides of the error sample data on the same line as the error sample data. It can be roughly divided into an interpolation processing section and a replacement processing section that replaces the error sample data using one of the sample data near the error sample data on the same line as the error sample data. The variable length interpolation processing unit is a variable length interpolation processing unit that calculates a weighted average value using a plurality of sample data on both sides of error sample data PO to which error correction is manually inputted via terminal 1 shown in FIG. The interpolation processing circuit 11 and the second
Sample number control that determines the error flag corresponding to each sample data inputted through the terminal l shown in the figure, and controls the number of sample data used for the ζ additive average and the coefficient of the weighted average based on the determination result. It consists of a circuit 13. The replacement processing unit also includes a replacement processing circuit 12 that replaces the error sample data using one of the sample data without errors among the sample data, and a replacement processing circuit 12 that determines the error flag and based on the determined result i. It consists of a permutation mode control circuit 14 that determines sample data to be used in the permutation process. Each error-corrected sample data from the variable length interpolation processing circuit 11 and the replacement processing circuit 12 is supplied to the selector 16, and when interpolation processing is possible, the sample data obtained by the interpolation processing is is taken out from terminal 18 and '4i
When the inter-lt processing is not possible, the sample data obtained by the replacement process is taken out from the terminal 18. Of course, if there is no error in the sample data, the sample data is taken out from the terminal 1.
taken out from the sun.

This output sample data is supplied to a two-dimensional error correction circuit 3 shown in FIG.

Next, the specific operation of this one-dimensional error correction circuit will be explained.

This one-dimensional error correction circuit 2 includes, for example, seven sample data P3, P2, PI%PO1M1, M2, M3 on the same line of the video signal, as shown in FIG. error flag FP3,
FP2, FPI, FPO, FMI, FM2, and FM3 are supplied. The above sample data PO is sample data to which error correction is applied, and sample data P1, P2
, P3 are three pieces of sample data in order from the one closest to the left of the sample data PO, and the sample data Ml, M
2 and M3 are three pieces of sample data in order from the closest one on the right side of the sample data PO.

These sample data P3, P2, Pl, Ml, M2
, M3 is a variable length interpolation processing circuit 11 and a replacement processing circuit 12
is supplied to On the other hand, error flag F P3, FP2, F
PI, FMI, FM2, and FM3 are supplied to a sample number control circuit 13 and a replacement mode control circuit 14. Also,
Sample data PO and error flag FPO are supplied to latch 15 and selector 16.

In the sample number control circuit 13, the state of the error flags of a plurality of sample data on both sides of the error sample data PO to be subjected to error correction is determined, and the sample data whose error flag is "l" (error present) is determined. A control signal is supplied to the variable length interpolation processing circuit 11 to perform weighted average processing while excluding . In the specific example shown in FIG. 3, six error flags FP3, FP2, FPI, FMI
, FM2, and FM3, and a control signal is supplied to the variable length interpolation processing circuit 11 to exclude sample data that is "l" (with error) and perform weighted average processing. Then, in the variable length interpolation processing circuit 11, the sample data P3, P2, PI.

The above error flag is "l" among Ml, M2, and M3
Weighted average processing is performed by excluding sample data (with errors). Here, a specific example shown in FIG. 4 will be explained. In addition, O shown in this figure indicates error-free sample data, × indicates error sample data, △ indicates that at least one of the left and right sample data pairs is error sample data, and the opening indicates that an error state is taken into consideration. Shows sample data that does not.

As shown in FIG. 4a, error flag data FP3, FP
2. FPI, FMI, FM2, and FM3 are all '0' (
6 sample data P3, P on both sides of the error sample data PO to which error correction is applied (no error).
2. Pl, Ml, M2, and M3 are all error-free (
(using 6 samples), the weighted average coefficient is set to K1. to 2
, K3, and the weighted average value P is P 41 x (Pi ten years old) ÷ 2X (P2 + M2)
+3X (P:bM3).

As shown in the box of FIG. 4, the error flags FP2, FPI,
FMI and FM2 are all “0” (no error),
At least one of error flags FP3 and FM3 is "l"
(There is an error), and the four sample data P2 on both sides of the error sample data PO to which error correction is applied
, PI, Ml, and M2 are in an error-free state (using 4 samples), the weighted average value P is set to P.IX(PI+old)+2X(P2+12).

As shown in Figure 4C, the error flags FPI and FMI
is “0” (no error), and the error flag FP2
, FM2 is 11° (with error), and two sample data Pi, , Ml on both sides of the error sample data PO to be subjected to error correction are in an error-free state (two samples are used), the weighted Let the average value P be 1 x (PL+M1).

Hereinafter, the weighted average value P obtained by the variable length interpolation processing circuit 11 as described in (g) is supplied to the selector 16. By the way, as the values of 1, K2, and K3 in the above coefficient group, the following values are used in consideration of ease of circuit configuration, number of component parts, etc.

When using 2 samples, Kl=I/2・0.5. Set K2= to 3.0.

When using 4 samples, 1・1/2+1/8+1/16・2・0.6875
-(1/2+1/4)/4・-0,1875,K3=0
shall be.

When using 6 samples, K1=1/2+1/4・0.75. K2・-(1/2
+ 1/8) /2・-0,3125 to 3・l/16・
It is set to 0.0625.

Next, the replacement processing section (replacement processing circuit 12, replacement mode control circuit 14) shown in the third section will be explained.

In cases other than the three error modes shown in a, b, . . . c of FIG.

In the replacement mode control circuit 14, the error flag FPI
, the state of the FMI is determined and the error flag Fl)1. F
When at least one MI is "1" (error present), sample data P1. The error sample data PO is replaced using the error free sample data of Ml.

When the error flags FPI and FMI are "IJ (error present)" and at least one of the error flags FP2 and FM2 is "0" (no error), error-free sample data of sample data P2 and M2 is used. The error sample data PO is replaced. Note that when both error flags FP2 and FM2 are "0" (no error), sample data P2 is used preferentially.

Error flags FP2, FPI, FMl, and FM2 are all "
l” (there is an error), and the error flag FP3,
At least one of FM3 is rQ.

(No error), error-free sample data of the sample data P3 and M3 is used to replace the error sample data PO.

Note that when both error flags FP3 and FM3 are "0" (no error), sample data P3 is used with priority.

Error 7 Lag FP3, FP2, FPI, FMI, FM2
, when all of FM3 is "l" (error exists),
The last error-free sample data is used to replace the error sample data PO. Here, the last error-free sample data means that the memory for one sample data provided in the latch 15 is sequentially updated with error-free sample data on the same line, and this stored sample data is say.

As described above, the sample data subjected to the replacement process is supplied to the selector 16. That is, the selector 16
is supplied with three sample data: sample data (weighted average value) obtained by the variable-length interpolation processing circuit 11, sample data obtained by the replacement processing circuit 12, and sample data (sample de')PO, and then performs the interpolation/replacement processing. One piece of sample data is selected based on the control signal from the control circuit 17 and the state of the error flag FPO, and is taken out from the terminal 18.

In other words, in the selector 16, the error flag FPO
is "0. (no error), the sample data PO
is extracted, the error flag FPO is "1" (error present), and the above interpolation process is possible, the above weighted average value P (sample pig subjected to interpolation process) from the variable length interpolation processing circuit 11 is extracted, and when interpolation processing cannot be performed, sample data obtained by the above replacement processing is extracted from the replacement processing circuit 12. This output sample data is supplied to the two-dimensional error correction circuit 3 shown in FIG. 2, etc.

(, -4, Two-dimensional error correction circuit (Fig. 1, Fig. 5 to Fig. 11) The sample data after one-dimensional error correction has been applied as described above has two-dimensional errors shown in Fig. 2. Two-dimensional error correction is performed in the correction circuit 3.The two-dimensional error correction circuit 3 processes sample data around the error sample data on the same line as the error sample data and on the lines above and below it, as well as the same sample data in the previous frame. For example, interpolation processing in multiple directions using sample data around the error sample data, sample data at the same position of the previous frame, etc. Replacement processing in which the error sample data is replaced using sample data, replacement processing in which the error sample data is replaced using neighboring sample data, and the like are performed.

A description will be given of the ranking control circuit 7 that predicts the (optimal) direction in which the results of these interpolation processing and replacement processing have the least change from the neighboring sample data, and determines the 1st place (ranking) ahead of 13 in these directions. do. Here, each sample data obtained from the one-dimensional error correction circuit 2, line delay circuit 4.5, and frame delay circuit 6 is shown in FIG. 5, and error flags corresponding to these sample data are shown in FIG. As shown in FIG. 5, the six sample data on both sides of the cough sample data PO on the same line (current line) as the sample data PO to which error correction is applied are P3, P2, PI, Ml, , M2. , M3, and each sample data of the upper line "-" is PP3, PP2, P
P ], PPO1PMI, PM2, PM3, and each sample data on the lower line is NF2, NF2, NP
I, NPOlNMl, NM2, NM3, and each sample data on the line corresponding to the current line one frame before is L P3, LP2, LPI LPO2LM
1, LM2.1M3. In addition, as shown in FIG. 6, error flags corresponding to each of the above sample data are set to FPOIF P3, PP2, l?, respectively. PI, F.M.
I, FM2, FM3, FPP3, FPP2, FPPl,
, FPPOlFPML, FPM2, FPM3, FNP3
,FNP2,FNPl,FNPOlFNMl,FNM2
, FNM3, FLP3, FLP2, FLPl, FLPO
Let them be lFLMI, Fl, M2, and FLM3.

FIG. 7 is a diagram showing a specific circuit configuration of the ranking control circuit 7. As shown in FIG. In FIG. 7, the H correction accuracy output circuit 41 is for measuring the accuracy of error correction in the H direction based on the correction error in the H direction in the vicinity of the error sample data. Calculate the corrected error J7ff using the samples 1-1 on the line A of the error sample data PO to be applied ((tl) using the error calculation circuit 41a and the sample data of H ([1) error calculation circuit 4 that calculates correction errors
1b, and the 1 ((U) output of the error calculation circuit 41a) i
(D) It is composed of a mean value/selector circuit 41c that calculates the average value with the output of the error calculation circuit 111b.

That is, the H(lt) error calculation circuit 41a receives, for example, sample data l'P1. ．． P, PO1PMl and error flags FPPI, FPPO, . In addition, the II (D) error/3i arithmetic circuit 41b includes, for example, sample data NPI and NPO of the line below the sample data PO to which error correction is applied.
lNMI and error flags FNr'l, FNPO, FN
MI is supplied, and a second correction F-NPO-(NPI 10N gates])/2 in the H direction is determined. These first and second corrected errors are supplied to an average value/selector circuit 41c. In this average value/cell, in the collector circuit 41c, the first and second
A calculation is performed to find the average value of the correction errors. That is, the correction error E(H) in 11 directions.

E (II) = (l F'PO- (PPl + P gate l) no 210 l NPO- (NPI ÷ NMI) / 2 +
)/2 is required. This +1 direction correction error E
()() are supplied to the ranking determination circuit 45. Note that the correction errors in the 11 directions mentioned above (in the old case, for example,
Using the weighted average calculation formula in dimensional error correction, E C)l)・0.5x (l PP0-(0,75x
(ppt÷P gate l)0.3125 X (PP2+P
M2> +0.0625 X (PP3+PM3))
+1IIPO-(0,75X(NP1+NMI)0.3
125 x (NP2÷NM2)÷〇, 0625X (
NP3+NM3)) l) may also be used. Also, for example, the first correction error i in the H direction is PP0-(PPl
+P gate 1)/2: When the error flag FPPl of the sample data PPI used for the calculation is "1" (error present), the correction error E (H) in the H direction is converted to E(II)・I NFO−( NPl+NM1)/2. Further, for example, the first correction error IPρ in the H direction
0-(PPl+PM1)/2 Error flag FPPI of sample data PPI used for calculation of 1 and the above H
Second correction error in direction i NPO−(NPl+NM1
)/21 when the error flag FNP 1 of the sample data NPI is [1J (error present), it is assumed that the correction error E (H) in the H direction cannot be calculated, and the H calculation possible signal in the H direction is The signal is sent to the two-dimensional error correction circuit 3 shown in FIG. 2 via the output terminal 46.

Further, the first and second correction errors in the H direction are compared with a predetermined threshold T. As a result of this comparison, if at least one correction error is greater than or equal to the predetermined threshold T, the H direction is not considered as the optimal direction for two-dimensional error correction. In other words, these 11 directions are excluded from the error correction directions, and error correction is performed in other directions. Note that the value of the threshold T is variable and can be set externally. By reducing this threshold T, it is possible to increase the accuracy of determining the direction of optimal two-dimensional error correction, but the direction of error correction cannot be determined at many positions. On the other hand, by increasing the threshold T, the accuracy of determining the direction of error correction becomes worse at many positions.

The ■ correction accuracy output circuit 42 is for predicting the accuracy of error correction in the ■ direction based on the correction error (correction error) in the ■ direction in the vicinity of the error sample data,
For example, error sample data PO to which error correction is applied
The sample data P1 on the left side and the sample data PI
V (L) error calculation circuit 42a that calculates a correction error using sample data PPI and NPI above and below, sample data M1 on the right side of sample data PO and sample data PMI above and below the sample data Ml,
V that calculates the correction error (correction error) using NMI
(R) Error/it calculation circuit 42b and these V (L)
Output of error calculation circuit 42a and V (R) error calculation circuit 4
2b and an average value/selector circuit 42c that calculates an average value with the output of 2b.

That is, V(L)Sv difference calculation circuit 42a, V (R)
In the error calculation circuit 42b and the average value/selector circuit 42C, for example, the first correction error Pl-(PP1
+NP1)/2 Second correction error gate 1- (PMl+N gate 1)/2 in ■ direction Correction error E (V) E(V)=(! Pi-(PI”1+NP1)/2 l
+ l Ml-(PP1+NP1)/2 l )/2
are required respectively. This V-direction correction error E (
V) is supplied to the ranking determination circuit 45.

Note that, similarly to when determining the correction error in the H direction, when the correction error cannot be calculated, a V calculation enable signal is outputted to the two-dimensional error correction circuit 3 shown in FIG. 2 via the output terminal 47. Further, it is determined whether the first and second correction errors are larger than a predetermined darkness value or not, and when they are larger than the threshold T, the V direction is not considered as the optimal direction for two-dimensional error correction. .

The correction accuracy output circuit 43 is for predicting the accuracy of error correction in the direction D based on the correction error in the direction near the error sample data. (L) Error calculation circuit 4
3a, the sample data Ml on the right side of the sample data PO and the sample data PP01N M2 on both sides of the diagonal line downward to the right of the sample data Ml are used to calculate a correction error, and (R) an error calculation circuit 43b;
Then, the average value (L) of the output of the error calculation circuit 43a and the average value of (R) the output of the error calculation circuit 43b is calculated.
It is composed of an i/selector circuit 43c.

That is, as described above, (1,) error calculation circuits 43a, D.

(R) Error calculation circuit 43b, average value/selector circuit 43
In c, for example, the first correction error in the D9 direction F-Pl-(T'P2+NPO)/2 D, the second correction error in the direction ■-(PPO+NM2)/2 D, the correction error in the direction E (D, ); E(D,)
=(l PI-(PP2+NPO)/2+ old-(PP
O+NM2)/2・)/2 are obtained, respectively. Additionally, the directional correction error E (D, ) is supplied to the ranking determination circuit 45 . Note that, similarly to when determining the correction error in the H direction, when the correction error cannot be determined by /jiX, a computation enable signal is outputted to the two-dimensional error correction circuit 3 shown in FIG. 2 via the output terminal 48. Further, it is determined whether the first and second correction errors are larger than a predetermined threshold T, and if they are larger than the threshold T, then the direction is 2.
It is made so that it is not considered as the optimal direction for dimensional error correction.

The D-correction accuracy output circuit 44 is for predicting the accuracy of error correction in one direction of D based on the correction error in one direction of D in the vicinity of error sample data. Sample data P1 on the left side of the error sample data PO and sample data PP01NP2 on both sides of the diagonal line downward to the left of the sample data PI.
D − (L) error ′f
D − (R) error/ji which calculates a correction error using the J arithmetic circuit 44a and the sample data M1 on the right side of the sample data PO and the sample data PM2 and NPO on both sides of the diagonal line downward to the left of the sample data Ml. It is composed of an arithmetic circuit 44b and an average value/selector circuit 44c that calculates the average value of the output of the D-(L) error arithmetic circuit 44a and the output of the D-(R) error arithmetic circuit 44b.

That is, the D-(L) error calculation circuit 44a, D(
R) Error calculation circuit 44b1 average (1!/selector circuit 4
4c, for example, the first correction error in one direction of D - PL-(PP2+NPO)/2 The second correction error in one direction of D Ml- (PM2 now! IPO) /2 The correction error in one direction of D E (D- ) ;E(D-)・
(:Pi-(r'PO+NP2)/2+ 1M1- (
PP2+NPO)/2! )/2 can be found respectively. Additionally, the direction correction error E (D-) is supplied to the ranking determination circuit 45. Note that, similarly to when calculating the correction error in the H direction, when the correction error cannot be calculated, the D-calculation possible signal is sent to the second
It is output to the two-dimensional error correction circuit 3 shown in the figure. Also,
It is determined whether the first and second correction errors are larger than a predetermined threshold T, and if they are larger than the threshold T, one direction is not considered as the optimal direction for two-dimensional error correction. .

Next, in the ranking determination circuit 45, the remaining correction errors E (H), E (V), which have not been excluded above,
E (D, ) and E (D-) are compared with each other, and a modification direction ranking (priority order) is determined in order of decreasing value. Note that when the correction error values in each direction are the same, priority is given in the order of the H direction, the {circle around (2)} direction, the D direction, and the D direction. The ranking flag (multiple bits) from the ranking control circuit 45 is supplied to the two-dimensional error correction circuit 3 shown in FIG.

The specific circuit configuration of this two-dimensional error correction circuit 3 is as shown in FIG. 1 described above. The input terminal 70 of the two-dimensional error correction circuit shown in FIG.
NPl, . The two-dimensional error correction circuit uses these ranking flags, computable signals in each direction, error flags, etc. to determine the error state around the error sample data PO to be subjected to error correction, and determines the optimal error correction method. Optimum interpolation direction determining circuit 51, high precision temporal replacement determining circuit 52, optimal replacement direction determining circuit 53, arbitrary interpolation direction determining circuit 54, low precision temporal replacement determining circuit 55, most recent replacement determining circuit 56 , repeated replacement determination circuit 57 and error correction method selector 3
■Interpolation circuit 6 that performs the actual interpolation processing device tQ processing based on the part consisting of B and the determined error correction method.
1, D, interpolation circuit 62, D-interpolation circuit 63, selector 6
4.65.66. Each of the above circuits will be explained in order below.

In FIG. 1, the optimum interpolation direction determining circuit 51 stores error flags FPP1 and FPPOS rp of sample data around error sample data 20 to which error correction is applied.
Mx, rpt; FMI, FNPl, BiNPO, FNM
I, the ranking flag and computable signals in each direction are supplied from the ranking control circuit 7, the states of these error flags, ranking flags, and computable signals are determined, and an appropriate interpolation direction is determined. Specifically, directions with an error flag of "1" (error present) are excluded, and the highest priority direction is determined based on the ranking flag. A control signal indicating this highest priority direction is supplied to the error correction method selector 5.

In other words, even if the ranking control circuit 7 determines that the correction error is the smallest, if the sample data used for interpolation processing in this direction is in an error state, this direction will not be selected and will be given the next priority. The direction where is higher is selected.

The high-precision temporal replacement determination circuit 52 includes six sample data P3, P2, r'l, Ml, M2, M3 on both sides of the error sample data PQ to which error correction is applied, and seven sample data on the corresponding line of the previous frame. sample data LP
3, LP2, LPI, LPOLMI, 1M2, LM3
, these sample data error flags FP3, FP
2, FPl, FMI, FM2, FM3, FLP3, FL
P2, FLPI, FLPO, FLMI, F l-M 2
, FLM3 are supplied, the error flag is judged, and it is determined whether or not temporal (on the time axis) replacement processing is possible. All of the above error flags are rQ.

(no error) and the difference between the corresponding sample data is less than or equal to a predetermined threshold HT, a control signal for replacing the error sample data PO with the sample data LPO of the previous frame is supplied to the error correction method selector 58. be done. Specifically, FP3・FP2:FP1=FM1
=I'M2=F gate 3・F[, P3:FLP2・l? LP
l=I'LPoENGFL,'ll・FLM22FLM3=
OLP3-P3'≦HT, l 1. Ml-phylum t
: <or.

LP2-P2・≦)IT, l 1M2-M2 +≦
IITLPI-Pi'≦11T, LM3-M31≦
When all the IIT conditions are satisfied, the error sample data PO is replaced with the sample data LPO.

That is, when the six sample data on both sides of the error sample data PO do not change much over time, replacement is performed on the assumption that the error sample data PO also does not change over time. Note that during the above period (f HT is assumed to be a small value).

The optimum replacement direction determining circuit 53 has an error flag FPP1.
．． ．． Fl'l, FMI.

FNPI, FNPO, FNMI, ranking flags from the ranking circuit 7, and computable signals in each direction are supplied, and the states of these error flags, ranking flags, and computable signals are determined, and the optimal replacement direction is determined. . Specifically, directions with error flags rl, (error if) are excluded, and the direction with the highest priority is determined based on the ranking flags of the remaining directions. A control signal indicating the farthest direction is supplied to the error correction method selector 5.

The error flag FPP is sent to the arbitrary interpolation direction determining circuit 54.
l, FPPO, FPMI, FPI, FMI.

FNP_I, FNPO_FNMI are provided and the state of these error flags is determined. In other words, the direction in which the error flag is "0" (no error) is selected,
A control signal that allows interpolation processing in this direction is supplied to the error correction method selector 58.

Note that when multiple directions are selected, 11 directions are selected, ■direction, and D. Priorities are set in the order of D direction and D direction.

(Low precision temporar device) The mulberry determination circuit 55 stores six sample data P3, P2, Pl, Ml, M2, both 1jljl of the error sample data PO to be subjected to error correction.
M3, seven sample data LP3.1 of the corresponding line of the previous frame. , P 2, LPI, LPO, LMI
, LM2.1M3 and these sample data error flags FP3, FP2, FPl, r”Ml, FM2, F
M3, FLP3, FLP2, FLPI, FLPO, Fl
, Ml, FLM2, and FLM3 are supplied. In this low-precision temporal replacement determination circuit 56, - the above error flag is determined, and the error flag FLPO is "0" (no error), and the error flag FLPO is "0" (no error), and the (one set is "0" (no error)), and the above 2
When the difference between each sample data set is less than or equal to a predetermined darkness value LT, a control signal is supplied to the error correction method selector 58 to replace the error sample data PO with the sample data LPO of the previous frame. That is, 1'LI'0・0°FP3=FLP3・O or FP2・FLP2・O or F
PI・FLPI・0F41・FLMI・0 or FM2・
FLM2/O or FM3/FL gate 3/0! , l'n-P
nl ≦LT, ! LMn+-Mm≦Lr
When the following conditions (n and m represent error-free numbers) are satisfied, the error sample data PO is replaced with the sample data LPO.

In other words, the high-precision temporal replacement circuit 52 is connected to the
In this case, the six sample data on both sides of the error sample data PO and the corresponding sample data of the previous frame must all be in an error-free state, and when the error rate is low, the high-precision temporal replacement is effective. , and low-integration temporal replacement is effective when the error rate is high. Note that the threshold value LT is a small value.

The nearest neighbor replacement determining circuit 56 includes four error flags F on both sides of the error sample data PO to be subjected to error correction.
P2, FPl, l"Ml, FM2, 3 error free PPIs on the upper line, FPPO1Fl"Ml and 3 error flags FNPI FNPOlFN on the lower line
Ml is supplied and the state of these error flags is determined. That is, the error sample data PO is replaced by using the closest (nearest neighbor) sample data among the sample data whose error flag is "O" (no error). A control signal for replacing the error sample data PO with this nearest neighbor sample data is supplied to the error correction method selector 58. Note that when multiple sample data are available, sample data P1, ML P2
, M2, PPO.

NPO, PPI Priorities are set in the order of PMI, NPI, and NMI.

The iterative replacement determination circuit 57 used in the video signal processing circuit according to the embodiment of the present invention includes an error flag (particularly an error flag FPO of a point to be corrected) and a recursion count from a recursion count memory 60. is supplied. Here, repeated replacement refers to replacing the error sample data PO when the error rate of the supplied sample data is extremely high and normal interpolation processing or replacement processing as described above cannot be performed. For example, the first generation is the sample data obtained by replacement processing using the sample data that has undergone error correction, and this ttU generation The sample data obtained by performing the replacement process again using the sample data is defined as the second generation. In addition, the states of these generations are expressed by recursion counts (recursion count days). In other words, for example, as shown in FIG.
), and the sample data P4, P3, P2, Pl, P
When all O are in error state u (X), sample data P4 is replaced with error-free sample data P5,
Sample data P3 is replaced with sample data P4 (P5
recursive replacement) and becomes the first generation. Sample data P2 is replaced with sample data P3 and recursive replacement 2
It is the second generation. Sample data P1 is sample data P
2 and becomes the third generation. The sample data PO is replaced with the sample data PI, resulting in the fourth generation of recursive replacement. Figure 9 also shows that the recursive permutation described above is 8
A specific example is shown in which the process is performed up to the third generation. As for the specific value of the above recursion coefficient, the success value is set according to each error correction method as shown in Table 1. U.I.
It is assumed that 2 is added to the value each time the above recursive replacement is performed.

Table 1 Note that default temporal replacement in Table 1 refers to replacing the error sample data PO using the sample data LPO of the previous frame when all of the above error correction methods cannot be used. This is a correction process performed on error samples whose error rate is so high that even the above-mentioned recursive replacement cannot be performed. If this is done continuously, the image will appear static.

Here, in the embodiment of the present invention, the L limit value of the recursion count is changed, and the upper limit value of the generation of the recursive repeated replacement is changed. For example, when an error sample for which the above recursive replacement is not performed is to be corrected by the default temporal replacement, the error sample point in the image that cannot be corrected by the normal correction method is This will change the proportion of corrections made using temporal replacement or the recursive replacement described above.

Specifically, it is possible to change the upper limit of the above recursion count depending on the content and type of the screen. In the case of an image with a high
As shown in the figure, the range 9 to be modified by the recursive replacement is reduced, and the range 1 to be modified by the default temporal replacement (i.e., the range in which the previous image is displayed) is
Widen 0. On the other hand, in the case of images with low temporal correlation, such as those in video or shuttle playback mode, the above upper limit value is made thicker (as shown in Figure 11, the image is corrected by the above recursive replacement). The range 9 is enlarged, and the range 10 corrected by the above default temporal replacement is narrowed.In these figures 10 and 11, the same sample data is used within the range 9 corrected by the above recursive replacement. Therefore, it is displayed with a single density and a single color like one pixel, and the above default temporal 1st value is set to 4g f (, within the range 10, the closest error in time for each sample position is However, if errors occur continuously, the old sample data will continue to be used and the image will appear stationary.As a result, for images with little movement, as shown in Figure 1O. The previous image data is used as it is in the 10th range to increase the resolution, and for images with rapid movement, the 11th range is used as is.
As shown in the figure, even at the expense of resolution, it displays a large amount of real-time data and prevents the negative effects of the previous image remaining.

By the way, as a concrete example of the above-mentioned determination of the content and type of the image, especially the magnitude of the movement, it may be performed based on, for example, the playback mode of the VTR. This is because when the VTR is in still image (still image) mode or slow playback mode, there is a high probability that images with little movement will be obtained, and when the tape running speed is fast, such as in so-called shuttle mode, there is a high probability that images with little movement will be obtained. This is done in consideration of the high probability of obtaining a sharp image. In other words, when in gloss mode, cue, review playback mode, etc., the upper limit of the number of times the recursive replacement is repeated increases the range in which recursive replacement processing is performed, and when in still image playback mode or slow playback mode. Sometimes, you can reduce the upper limit of the number of repetitions of recursive replacement to narrow the range in which recursive replacement is performed (
do. Specific numerical values of the above upper limit include, for example, a state where the maximum value of the recursion count is set to 7 and the generation of repeated replacement is limited to 4, and a state where the maximum value of the recursion count is set to 15 and the Iit generation of repeated replacement is limited to 8. It is possible to switch between the states.

In addition, for example, the upper limit of the number of repetitions of the recursive replacement may be changed depending on the error rate.
Furthermore, for example, in the shuttle playback mode, the range in which repeated replacement is performed (the upper value of the number of repeated replacements) may be made larger when the error rate is high and the speed is high.
Note that the recursion count is stored in a recursion count memory 60 shown in FIG. 1, and a recursion count is provided corresponding to all sample data.

In the iterative replacement determining circuit 57, the recursive counts at the positions of the sample data Pl, the sample data PPI, PPO, and PMI on the line above the sample data to which the error correction is applied are calculated as the recursive counts input through the terminal 90. The position is compared with the maximum value, for example 7, and the position with the smallest recursion count that is less than or equal to 7 is selected, and a control signal for performing this repeated substitution is supplied to the error correction method selector 58. Also,
The recursion count of the selected position is sent from the repeat permutation determination circuit 57 to the recursion count generator 59. This recursion count generator 59 is repeatedly set in the error correction method selector 5 (negative is selected).
When a signal indicating that the replacement has been performed is supplied and the iterative replacement method is selected, 2 is added to the recursion count of the selected position, and this added recursion count becomes the recursion count of the position where the replacement has been performed. It is newly stored in the recursion count memory 60 as a recursion count. Note that when the recursion coefficients at the positions of the sample data P1, PPI, PPO, I'Ml are the same value, the sample data 1'l, I'PO
, PPI, and PMI.

Here, a specific circuit configuration of the iterative replacement determining circuit 57 is shown in FIG. In this figure, the comparator 110 to compare! 5113 contains sample data PO to which error correction is applied via terminals +00 to 103, respectively.
Sample data near PI, PPO,, PPI, PM
An H direction recursion count of I, a direction recursion count of I, a direction recursion count of D, and a one-way recursion count of D are respectively supplied. In these comparators 110 to 113, a comparison is made with an upper limit value of the recursion count supplied via the terminal 90, for example, 7, and when the recursion count is less than 7 (NAND A repeatable replaceable signal from gate 114 that allows repeatable replacement is connected to terminal 105.
taken from.

The upper limit value of this recursion count is determined by the recursion count upper limit value switching circuit 91.
This recursive count upper limit value switching circuit 91 switches from the switching side? ffl is now available.

As the switching control signal from the terminal 92, specifically, for example, a signal indicating whether the reproduction mode of the VTR is the shuttle mode or not can be used. For example, 15 is output when this is the case, and 7 is output at other times, and is sent to the terminal 90 as the upper limit value of the recursion count. Further, the recursion count in the -F name direction is supplied to a permutation direction selection circuit 115, which selects the position with the minimum recursion count, and takes out a signal indicating this position from the terminal 106. These iteratively replaceable signals and signals indicating the position are supplied to the error correction method selector circuit 58 in FIG. 1 as recursive and iteratively replaced control signals.

As described above, the optimal interpolation direction determining circuit 51, the high-precision temporal replacement determining circuit 52, and the optimal replacement direction determining circuit 5
3. Control signals for performing various error corrections from the arbitrary interpolation direction determination circuit 54, the low-precision temporal replacement determination circuit 55, the nearest neighbor replacement determination circuit 56, and the iterative replacement determination circuit 57 are supplied to the error correction method selector 58. Ru. In this error correction method selector 58, the optimum error correction method is selected based on the priority order (from top to bottom) shown in Table 2.

Table 2 Repeated Replacement Maximum 98% The error rates in Table 2 indicate the applicable range of each error correction method, and it is important to note that multiple error correction methods can be applied to the same error rate. It shows. However, the error rate is not used to determine the error correction method; as mentioned above, the error correction method is determined by the state of the error flags (error pattern) around the sample data to which error correction is applied. be done. As described above, the error correction method is determined by the error correction method selector 58, and the error correction is performed according to the control signal from the error correction method selector 58. Each error correction method will be explained below.

When interpolation in the optimum interpolation direction is possible, a signal is sent from the error correction method selector 5 to control the selectors 64 and 66. This control 0 signal causes the selector 64 to select one of the interpolated number data (interpolated value 1). That is, the selector 64 is supplied with F (direction weighted average value (interpolated value) P) obtained by the one-dimensional error correction circuit 2 shown in FIG. 2 via the terminal 73. The circuit 61 has terminals 74.7
Sample data PPO and NPO above and below the sample data PO to be subjected to interpolation processing are respectively supplied through
In this V interpolation circuit 61, the interpolated value P ((
PPO+NI'O)/2) is obtained, and this interpolated value P in the {circle around (2)} direction is supplied to the selector 64.

Further, the interpolation circuit 62 is supplied with sample data PPI and NMl on the diagonal line downward to the right of the sample data P0 to be interpolated, respectively, through terminals 76 and 77. In the interpolation circuit 62, an interpolated value P ((PPl+~old)/2) in the direction D is determined, and the interpolated value P in the direction is supplied to the selector 64. The D-interpolation circuit 63 is supplied with sample data P, 'V41, and NPI on the diagonal line downward to the left of the sample data PO to be interpolated, respectively, through terminals 78 and 79.
In this D interpolation circuit 63, one-way D interpolation value P((
PMl+! JPI)/2) is determined, and this one-way interpolation value P of D is supplied to the selector 64. As described above, the interpolated values P in each direction are supplied to the selector 64, and the control signal from the error correction method selector 58 determines the direction determined by the optimum interpolation direction determining circuit 51 (the direction with the minimum correction error). Interpolated value P is selected and output to terminal 8 via selector 66.

When the high-precision temporal replacement is selected in the error correction method selector 58, the selector 66 is controlled;
The sample data LPO of the previous frame inputted through the terminal 88 is outputted to the terminal 8.

When the error correction method selector 58 selects replacement according to the optimal replacement direction, the selector 65.6G is controlled and the sample data l″P1, PPOlPMI, Pl input via the terminals 80 to 7-87, respectively.
.

When interpolation in an arbitrary interpolation direction is selected in the error correction method selector 5B, the selectors 64 and 66 are controlled, and one of the interpolation values P in each direction manually input to the selector 64 is selected by the arbitrary interpolation direction determining circuit 54. The interpolated value P in the determined direction is selected and output to the terminal 8 via the selector 66.

When low-precision temporal replacement is selected in the error correction method selector 5B, the selector 66 is controlled, and the number data 1 and PO of the previous frame input manually via the terminal 88 are output to the terminal 8.

In the error correction method selector 5th, the most recent replacement is M
When IJe is performed, selectors 65 and 66 are controlled,
The sample data PPi, PPO, PMl, Pl, Ml, NP, which are manually input through the terminal 10 and the terminal 87, respectively
l, , NPOlNMI to the most recent replacement determination circuit 56
The sample data determined in is selected, and the selector 66
It is output to terminal 8 via.

When repeat replacement is selected in the error correction method selector 58, the selectors 65 and 66 are controlled, and the repeat replacement determination circuit 57 determines the sample data PP1 and PPOlPMiPl input via the terminals 80 to 83, respectively. The selected sample data is selected and outputted to the terminal 8 via the selector 66.

Note that when the error correction method selector 58 determines that all of the above error correction methods cannot be used, default replacement is performed, and the selector 66 is controlled to replace the sample of the previous frame input via the terminal 88. It is output to data 8.

As is clear from the explanation below, when the error rate is very high and normal error correction cannot be performed, such as interception processing or replacement processing using error-free sample data, the error The error correction using the sample data that has been applied is repeated recursively, and the number of repetitions of this relocal correction is made variable.
The upper limit of the number of times the above recursive modification can be repeated depends on the JIN and content of the i-side, such as moving images and still images, fast-moving double-sided screens and slow-moving screens, and more specifically, depending on the VTR's forward mode, etc. By controlling the values, it is possible to perform optimal error correction according to the content and type of the screen.

H. Effects of the Invention According to the video signal processing circuit according to the present invention, when the error rate is so high that normal error correction such as interpolation processing using error-free sample data cannot be performed, the correction has already been performed. In addition to making corrections using the sample data that has been edited, by making the upper limit of the number of recursive repeated corrections of the correction sample data variable, it is possible to make the most suitable corrections depending on the type and content of the screen, for example. There is.

Specifically, the number of repetitions in the iterative replacement process using sample data that has already undergone error correction can be controlled depending on, for example, moving images and still images, fast-moving double-sided screens and slow-moving screens, or error rates. By speaking, it is possible to perform error correction suitable for the type of screen, etc.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of a two-dimensional error correction circuit to which an embodiment of the video signal processing circuit according to the present invention is applied, and FIG. 2 is a block circuit diagram of an error correction device to which the video signal processing circuit according to the present invention is applied. FIG. 3 is a block circuit diagram of the dimensional error correction circuit, and FIG. 4 is a block circuit diagram of the dimensional error correction circuit.
It is a diagram showing the error state of sample data for explaining the operating principle of the dimensional error 1'6 adjustment circuit, and FIG.
FIG. 6 is a diagram showing the arrangement of sample data used in dimensional error correction; FIG. 6 is a diagram showing the arrangement of error flags used in two-dimensional error correction; and FIG. i is a block circuit diagram of a circuit;
8 and 9 are diagrams showing specific examples of repeated replacement, FIGS. 10 and 11 are diagrams showing the range of repeated replacement processing, and FIG. 12 is a block circuit diagram of a repeated replacement determination circuit. be. 57...Repetitive replacement determination circuit 59...Recursion count generator 60... -Recursion count memory 90...Upper limit value input terminal

Claims (1)

[Claims] Error correction processing means for correcting the error sample data using other sample data when sample data of a video signal is supplied and the sample data is in error; and a counting means for counting the number of repetitions of modification when using already modified sample data for processing, and does not perform modification such that the count value from the counting means exceeds a predetermined upper limit value, and the above upper limit count value. A video signal processing circuit characterized in that the circuit is variable.