JPH0376416A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a through-current flowing when a level of an input terminal of a semiconductor circuit having MOS structure is an intermediate level by detecting the intermediate level and outputting a detection signal. CONSTITUTION:When a level of an input terminal 3 is an intermediate level, a through-current flows from a Vcc to GND via a resistor 7, a P-channel transistor (TR) 5 and an N-channel TR 6, a voltage drop is caused by the through- current and an input 10 of an inverter 10 is brought into an 'L' level. The level of the input 10 is selected not to turn off the P-channel TR 5 and a threshold voltage of the inverter 8 is selected to decide the said level to be an L input. Thus, the level of the output 9 goes to 'H' and a gate of a P-channel TR 11 and of an N-channel TR 12 goes to an 'H', the P-channel TR 11 is turned off and a through-current flowing from the Vcc to the P-channel TR 1 and the N-channel TR 2 to GND is blocked.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit having an MO5 structure.

[Conventional technology]

FIG. 2 shows an inverter circuit with a conventionally used CMO5 structure. In the figure, (1) is a P-channel transistor, (2) is an N-channel transistor, and this transistor (11 (2)) is constructed. (3) is the input of the inverter, and (4) is the output of the inverter.

Next, the operation will be explained. When a high level potential (hereinafter referred to as H) is input to input (3).

P-channel transistor (hereinafter referred to as Pch transistor) (1) is 0FFL, N-channel transistor (hereinafter referred to as Nch transistor) (2) is ON t,
A low level potential (hereinafter referred to as below) is output to the output (4).

When L is input to the input (3), the Nch transistor (2) is OFF.
) is turned on, and H is output to output (4).

When the intermediate potential is input to input (3), Nch
Both transistor (2) and Pch transistor (1) are in an ON state, a through current flows from Vcc to GND, and it is uncertain whether the output (4) becomes H or L.

[Problem to be solved by the invention]

The conventional semiconductor integrated circuit with the MO5 structure was configured as described above, so if the input voltage is at an intermediate potential, it is uncertain whether the output is L or H, so it is impossible to determine that it is at an intermediate potential. Moreover, in the case of an intermediate potential, there is a problem that power is consumed due to a through current.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor integrated circuit that determines that the voltage is at an intermediate potential.

[Means to solve the problem]

A semiconductor integrated circuit according to the present invention is capable of determining that the input terminal of a semiconductor circuit having a 1MO5 structure is at an intermediate potential.

[For production]

The determination circuit according to the present invention detects when the input terminal of the semiconductor circuit having the MO5 structure is at an intermediate potential and outputs a detection signal.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, a Pch transistor (1) and an Nch transistor (2) constitute an inverter circuit similar to the conventional one. (3) is the input of the inverter circuit, (4) is the inverter circuit output, OI) is the PCh transistor for blocking the through current of the inverter circuit,
This is an Nch h transistor for fixing the output (4) to L when the 0th input (3) is at an intermediate potential. Next, the input (3) of the conventional circuit is the gate input, (5) is the Pch transistor of the judgment circuit, and (6) is the Nch transistor of the judgment circuit.
) transistor, (7) is a pull-up resistor that controls the current flowing through the judgment circuit, (8) is an inverter that detects the voltage drop due to the current flowing through the judgment circuit, (9) is the output of the judgment circuit, (1G is the inverter This is the input of (8).

Next, the operation will be explained.

First, the case where the input (3) of the conventional circuit is at an intermediate potential will be described. Pch) transistor (5), Nch)
Both transistors (6) become ONL, and V
From cc to resistor (7), Pch transistor (5), Nc
h) A through current flows through the transistor (6) to GND, and this through current causes a voltage drop, and the input (101) of the inverter (8) is pulled to L. At this time, Pc
h) Transistor (51, Nch transistor (6)
The level of input 00 is determined by the on-resistance of and the resistance division of resistor (7).

This level is selected to a value that does not turn off the Pch transistor (5), and the threshold voltage of the inverter (8) is selected to a value that allows this level to be determined as an L input. With this circuit configuration, output (9) is obtained.

becomes H. By the output (9) becoming H, Pch
The gates of transistor θ1) and Nch transistor a frame become H, and Pch) transistor 00 becomes OFF L/
, Vcc to Pch) transistor (1), Nch
) Blocks the through current flowing to GND through the transistor (2), turns on the Nch transistor (02), fixes the output (4) to L, and connects the next stage logic to which the output (4) is connected. Input becomes stable. Next, input (3)
To explain the case where L is input to %Pch h transistor (5) is ONf, but Nch transistor (
6) is OFF L/, the input α0 of the inverter (8) is held at H, and the inverter (8)
The output (9) becomes L, and the Pch) transistor (10
is ON% Nch) transistor α is OFF,
The inverter circuit within the broken line is simply an inverter.

When input (3) is H, Nc is the same as when L is input.
The h transistor (6) is turned on, but the Pch transistor (5) is turned off, so the input α mark remains high and the output (9) of the inverter (8)
remains at L, and the inverter circuit within the broken line is simply an inverter.

〔Effect of the invention〕

As described above, according to the present invention, a through current can be prevented from flowing when the MOS semiconductor integrated circuit is at an intermediate potential, and the intermediate potential can be detected by observing the output of the 1 determination circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of an inverter circuit having a conventional CMOS structure. (11, (51 is P channel MOS) transistor, (2
1, (61 is an N-channel MOS transistor, (7) is a pull-up resistor that controls the through current, (8) is an inverter that detects the voltage drop by the through current, and αυ and a t transistors are shown. , Same symbols indicate the same or equivalent parts.

Claims (1)

[Claims] The output of an inverter whose gate inputs are the output from Vcc through a resistor and the output from GND through an N-channel MOS transistor and a P-channel MOS transistor is N.
A semiconductor integrated circuit characterized in that an intermediate potential is detected by changing only when the gate inputs of a channel MOS transistor and a P-channel MOS transistor reach an intermediate potential.