JPH0376401A - Microwave planer circuit board - Google Patents
Microwave planer circuit boardInfo
- Publication number
- JPH0376401A JPH0376401A JP1213571A JP21357189A JPH0376401A JP H0376401 A JPH0376401 A JP H0376401A JP 1213571 A JP1213571 A JP 1213571A JP 21357189 A JP21357189 A JP 21357189A JP H0376401 A JPH0376401 A JP H0376401A
- Authority
- JP
- Japan
- Prior art keywords
- board
- circuit board
- thin film
- gold
- kovar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010408 film Substances 0.000 claims abstract description 13
- 239000010409 thin film Substances 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 11
- 239000010931 gold Substances 0.000 abstract description 11
- 229910052737 gold Inorganic materials 0.000 abstract description 11
- 229910000833 kovar Inorganic materials 0.000 abstract description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 5
- 229910000679 solder Inorganic materials 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 238000005476 soldering Methods 0.000 abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052802 copper Inorganic materials 0.000 abstract description 3
- 239000010949 copper Substances 0.000 abstract description 3
- 230000006378 damage Effects 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 10
- 230000003139 buffering effect Effects 0.000 description 3
- 238000010304 firing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Waveguides (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はマイクロ波固体増幅器に関し、特に整合回路
基板の組立構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microwave solid-state amplifier, and more particularly to an assembly structure of a matching circuit board.
第2図は基板裏面が表面と同様に金薄膜が蒸着によって
メタライズされている従来の平面回路基板の斜視図を示
している。FIG. 2 shows a perspective view of a conventional flat circuit board in which the back surface of the board is metalized with a thin gold film by vapor deposition, as is the front surface.
図に分いて、(1)はアルミナ又は高誘電体基板、(2
)は表面の金メタライズ薄膜、(3)は裏面の金メタラ
イズ薄膜、(4)はAuSn又はAuGe半田で、マイ
クロ波平面回路基板はパッケージ(61上にM!衝用の
板(5)を挾み半田付けしである。In the figure, (1) is an alumina or high dielectric substrate, (2
) is a gold metallized thin film on the front surface, (3) is a gold metallized thin film on the back side, and (4) is AuSn or AuGe solder. It is soldered.
従来のGsAa FICTの整合回路基板では、基板裏
面の金メタライズ薄膜は誘電体基板と物理的に蒸着して
いるため、熱変化に弱く、半田付は及び、金ワイヤボン
ディングの際、金薄膜が破壊され基板はがれが起り易い
という欠点があった。In the conventional GsAa FICT matching circuit board, the gold metallized thin film on the back side of the board is physically vapor-deposited with the dielectric substrate, so it is susceptible to thermal changes, and the gold thin film is easily damaged during soldering and gold wire bonding. The disadvantage is that the substrate is likely to peel off.
従来のマイクロ波平面回路基板は以上のように構成され
ていたので、裏面は表面と同様金薄膜で蒸着メタライズ
しであるため、アルミナ、高誘電体基板との結合が弱く
、熱変化によって半田と接している裏面金薄膜が破壊さ
れ、基板がはがれるという問題点があった〇
この発明は上記のような問題点を解決するためになされ
たもので、裏面に金属厚膜を焼成法で形成し基板との結
合を強くして基板のはがれを少なくすることを目的とす
る。Conventional microwave flat circuit boards were constructed as described above, and because the back side is vapor-deposited metallized with a thin gold film like the front side, the bond with alumina and high dielectric substrates is weak, and thermal changes cause solder and metallization. There was a problem that the thin gold film on the back surface that was in contact was destroyed and the substrate was peeled off. This invention was made to solve the above problems, and a thick metal film was formed on the back surface by a firing method. The purpose is to strengthen the bond with the substrate and reduce peeling of the substrate.
この発明に係るマイクロ波平面回路基板は、裏面に焼成
法による金属厚膜NJを形成するようにしたものである
。The microwave planar circuit board according to the present invention has a thick metal film NJ formed on the back surface by a firing method.
この発明にかけるマイクロ波平面回路基板は、基板裏面
に基板との結合の強い金属厚膜が形成されているため、
半田付けpよび金ワイヤ−ボンディング時の熱変化によ
り゛C基板がはがれてしまうことはない。The microwave flat circuit board of the present invention has a thick metal film formed on the back surface of the board that has a strong bond with the board.
The C substrate will not peel off due to thermal changes during soldering and gold wire bonding.
以下、この発明の一実施例を図について説明する。第1
図にかいて、(1)はアルミナ又は高誘電体の回路基板
で、銅パッケージ(61上に緩衝用のコバール板(6)
を挾んで、Au5H又はAuGe半田(41で半田付け
しである。また、回路基板(IIの表面は金薄膜で蒸着
メタライズしてあシ、裏面は焼成法により金属厚膜層(
7)が形威しである。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is an alumina or high dielectric circuit board with a Kovar plate (6) for buffering on a copper package (61).
The circuit board (II) is sandwiched and soldered with Au5H or AuGe solder (41).The surface of the circuit board (II) is metalized with a thin gold film by evaporation, and the back surface is coated with a thick metal film layer (
7) is a formality.
なか、上記実施例では緩衝用コバール板(6)を使用し
た場合を示したが、コバール板は、なくてもよい0
〔発明の効果〕
以上のようにこの発明によれば、半田付けや金ワイヤポ
ンディング時の熱変化による裏面金膜の破壊がなく、基
板のはがれが少なくなり、素子の信頼性1歩留りを向上
させるのに効果がある0Among them, although the above embodiment shows the case where the Kovar board (6) for buffering is used, the Kovar board may not be used. There is no destruction of the backside gold film due to thermal changes during wire bonding, and there is less peeling of the substrate, which is effective in improving device reliability1 yield0
第1図はこの発明の一実施例であるマイクロ波平面回路
基板の斜視図、第2図は従来のマイクロ波平面回路基板
の斜視断面図である。
図にかいて、(1)はアルミナ又は高誘電体の回路基板
、(2)は表面の金メタライズ薄膜、(4)はAuSn
又はAuG5半田、(51は緩衝用のコバール板、(6
)は銅パッケージ、(7)は基板裏面に焼成法によって
形成された金属厚膜層を示す。
なり1図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a perspective view of a microwave planar circuit board according to an embodiment of the present invention, and FIG. 2 is a perspective cross-sectional view of a conventional microwave planar circuit board. In the figure, (1) is an alumina or high dielectric circuit board, (2) is a gold metallized thin film on the surface, and (4) is AuSn.
Or AuG5 solder, (51 is Kovar plate for buffering, (6
) shows a copper package, and (7) shows a metal thick film layer formed on the back surface of the substrate by a baking method. In the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
より形成し、他面を薄膜により形成したことを特徴とす
るマイクロ波平面回路基板。A microwave flat circuit board characterized in that one side is formed of a thick metal film and the other side is formed of a thin film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1213571A JPH0376401A (en) | 1989-08-18 | 1989-08-18 | Microwave planer circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1213571A JPH0376401A (en) | 1989-08-18 | 1989-08-18 | Microwave planer circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0376401A true JPH0376401A (en) | 1991-04-02 |
Family
ID=16641412
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1213571A Pending JPH0376401A (en) | 1989-08-18 | 1989-08-18 | Microwave planer circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0376401A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6972496B2 (en) | 2001-06-12 | 2005-12-06 | Hynix Semiconductor Inc. | Chip-scaled package having a sealed connection wire |
-
1989
- 1989-08-18 JP JP1213571A patent/JPH0376401A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6972496B2 (en) | 2001-06-12 | 2005-12-06 | Hynix Semiconductor Inc. | Chip-scaled package having a sealed connection wire |
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