JP3240830B2 - Surface mount component and method of manufacturing the same - Google Patents

Surface mount component and method of manufacturing the same

Info

Publication number
JP3240830B2
JP3240830B2 JP11871994A JP11871994A JP3240830B2 JP 3240830 B2 JP3240830 B2 JP 3240830B2 JP 11871994 A JP11871994 A JP 11871994A JP 11871994 A JP11871994 A JP 11871994A JP 3240830 B2 JP3240830 B2 JP 3240830B2
Authority
JP
Japan
Prior art keywords
substrate
electrode
wiring electrode
wiring
mount component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP11871994A
Other languages
Japanese (ja)
Other versions
JPH07326830A (en
Inventor
一昭 南
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP11871994A priority Critical patent/JP3240830B2/en
Publication of JPH07326830A publication Critical patent/JPH07326830A/en
Application granted granted Critical
Publication of JP3240830B2 publication Critical patent/JP3240830B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、表面実装部品に関し、
特に基板の端面電極と接続される配線電極に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount component,
In particular, the present invention relates to a wiring electrode connected to an end face electrode of a substrate.

【0002】[0002]

【従来の技術】従来の表面実装部品を、図5乃至図10
を用いて説明する。図5及び図6において、11は所望
の回路(図示せず)が形成された、例えば樹脂やセラミ
ック等からなる基板であり、基板11の表面に、回路か
ら基板11の縁部まで引き出された配線電極12が形成
され、基板11の端面から裏面の端部及び表面の配線電
極12の端部の表面にかけて端面電極13が形成され、
表面実装部品15が構成されている。
2. Description of the Related Art Conventional surface mount components are shown in FIGS.
This will be described with reference to FIG. 5 and 6, reference numeral 11 denotes a substrate made of, for example, resin or ceramic on which a desired circuit (not shown) is formed. The substrate 11 is drawn from the circuit to the edge of the substrate 11 on the surface of the substrate 11. A wiring electrode 12 is formed, and an end face electrode 13 is formed from the end surface of the substrate 11 to the end of the back surface and the surface of the end of the wiring electrode 12 on the front surface,
The surface mount component 15 is configured.

【0003】この表面実装部品15の製造方法は、図7
に示すように、基板11の表面積より大きい表面積を有
するマザー基板16の表面に、例えばAuやAg等から
なる配線電極12が、蒸着,スパッタリング又はメッキ
等により複数個分形成された後、配線電極12を通って
ダイサー等により切断線16aでマザー基板16が切断
され複数の基板11が得られる。このとき、基板11の
切断面には配線電極12の端部が露出される。その後、
基板11の端面から裏面の端部及び配線電極12の端部
の上面にかけて、例えばAg,Cu又はAgPd等の厚
膜材料により端面電極13が印刷、焼成され、表面実装
部品15が得られる。
A method of manufacturing the surface mount component 15 is shown in FIG.
As shown in FIG. 5, after a plurality of wiring electrodes 12 made of, for example, Au or Ag are formed on the surface of a mother substrate 16 having a surface area larger than the surface area of the substrate 11 by vapor deposition, sputtering, plating, or the like, the wiring electrodes 12 are formed. The mother substrate 16 is cut through a cutting line 16a by a dicer or the like through the substrate 12, and a plurality of substrates 11 are obtained. At this time, the end of the wiring electrode 12 is exposed on the cut surface of the substrate 11. afterwards,
From the end surface of the substrate 11 to the end of the back surface and the upper surface of the end of the wiring electrode 12, the end surface electrode 13 is printed and fired with a thick film material such as Ag, Cu or AgPd, and the surface mount component 15 is obtained.

【0004】しかし、基板11の切断面の配線電極12
の端部には、図8に示すように、基板11の切断時に上
方向にバリ状の鋭利な突起12aが発生し、この突起1
2aにより、その後配線電極12の端部に取り付けられ
た端面電極13に亀裂が生じ、配線電極12と端面電極
13の導通が得られないことがあった。
However, the wiring electrode 12 on the cut surface of the substrate 11
As shown in FIG. 8, when the substrate 11 is cut, a burr-like sharp projection 12a is generated at the end of the projection 11a.
Due to 2a, the end face electrode 13 attached to the end of the wiring electrode 12 may be cracked, and the conduction between the wiring electrode 12 and the end face electrode 13 may not be obtained.

【0005】このため、図9に示すように、基板11の
縁部及び配線電極12の突起12aをバレル研磨により
除去するか、又は、図10に示すように、マザー基板1
6にV溝17を形成し、V溝17から切断線16aでマ
ザー基板16を分割し、配線電極12の突起12aの発
生を防止する方法が用いられていた。
For this reason, as shown in FIG. 9, the edge of the substrate 11 and the projections 12a of the wiring electrodes 12 are removed by barrel polishing, or as shown in FIG.
6, a V-groove 17 is formed, the mother substrate 16 is divided from the V-groove 17 by a cutting line 16a, and a method of preventing the projection 12a of the wiring electrode 12 from being generated has been used.

【0006】[0006]

【発明が解決しようとする課題】ところが、上記従来の
表面実装部品15において、端面電極13は焼付け加工
されているため、基板11や配線電極12との密着強度
は高いものの、配線電極12は蒸着,スパッタリング又
はメッキ等により基板11に取り付けられているため、
基板11と配線電極12との密着強度は低くなってい
る。
However, in the above-mentioned conventional surface mount component 15, the end face electrode 13 is baked, so that the adhesion strength to the substrate 11 and the wiring electrode 12 is high, but the wiring electrode 12 is deposited. Because it is attached to the substrate 11 by sputtering or plating,
The adhesion strength between the substrate 11 and the wiring electrode 12 is low.

【0007】そのため、表面実装部品15に温度変化が
生じると、基板11,配線電極12及び端面電極13の
それぞれの熱膨脹係数の違いにより、表面実装部品15
の各部に熱ストレスが発生し、この熱ストレスにより、
基板11と端面電極13との接合面が、基板11の端面
に対して垂直方向(図6の矢印方向)に剥離しょうとし
た場合、密着強度の低い基板11と配線電極12の境界
Xから剥離するため、熱ストレスに対する端面電極13
の剥離強度が低くなっていた。
Therefore, when a temperature change occurs in the surface-mounted component 15, a difference in the thermal expansion coefficients of the substrate 11, the wiring electrode 12, and the end surface electrode 13 causes the surface-mounted component 15 to change.
Thermal stress occurs in each part of the
When the bonding surface between the substrate 11 and the end surface electrode 13 is to be separated in a direction perpendicular to the end surface of the substrate 11 (the direction of the arrow in FIG. 6), the separation surface is separated from the boundary X between the substrate 11 and the wiring electrode 12 having low adhesion strength. The end face electrode 13 against heat stress.
Peel strength was low.

【0008】また、製造方法において、基板11をバレ
ル研磨する方法では、バレル研磨する際に、基板11の
表面の回路及び配線電極12が除去されないように、回
路及び配線電極12の表面保護工程がさらに必要にな
る。また、V溝17を形成する方法では、基板11の表
裏両面に配線電極12を形成する場合において、V溝1
7をマザー基板16の表裏両面に同時に形成することが
できないため、どちらか一方の面にV溝17を形成した
後、マザー基板16を反転し他方の面に再度V溝17を
形成する必要があり、工程が複雑になっていた。さら
に、どちらの方法も加工工程が増加するという問題があ
った。
Further, in the method of barrel polishing the substrate 11 in the manufacturing method, the surface protection step of the circuit and the wiring electrode 12 is performed so that the circuit and the wiring electrode 12 on the surface of the substrate 11 are not removed during the barrel polishing. You need more. In the method of forming the V-groove 17, when the wiring electrodes 12 are formed on both the front and back surfaces of the substrate 11, the V-groove 1 is formed.
7 cannot be simultaneously formed on both the front and back surfaces of the mother substrate 16, it is necessary to form the V-groove 17 on one of the surfaces and then reverse the mother substrate 16 to form the V-groove 17 on the other surface again. Yes, the process was complicated. Further, both methods have a problem that the number of processing steps increases.

【0009】本発明は、このような問題を解消するため
になされたものであり、基板の縁部と配線電極の端部と
の間に基板露出部を設けて、基板切断時の配線電極の突
起の発生を防止することにより、配線電極と端面電極の
導通を確実にし、端面電極の剥離強度を高め、加工工程
を簡略化した表面実装部品及びその製造方法を提供する
ことを目的とするものである。
SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. A substrate exposure portion is provided between an edge portion of a substrate and an end portion of a wiring electrode so that the wiring electrode is cut when the substrate is cut. An object of the present invention is to provide a surface-mounted component in which continuity between a wiring electrode and an end surface electrode is ensured by preventing the occurrence of a projection, the peel strength of the end surface electrode is increased, and a processing step is simplified, and a method for manufacturing the same. It is.

【0010】[0010]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明においては、基板と、少なくとも前記基板
の表面又は裏面に蒸着、スパッタリングまたはメッキに
より形成された配線電極と、前記基板の端面及び配線電
極の端部を覆って厚膜材料で形成した端面電極とを有す
る表面実装部品において、前記基板の縁部と配線電極の
端部との間に基板露出部を設け、前記端面電極を前記基
板の端面から前記基板露出部を介して前記配線電極の端
部にかけて形成したものである。
In order to achieve the above object, according to the present invention, a substrate is formed by vapor deposition, sputtering or plating on at least the front or back surface of the substrate.
In a surface mount component having a wiring electrode formed from the above , and an end surface electrode formed of a thick film material covering the end surface of the substrate and the end portion of the wiring electrode, the edge portion of the substrate and the end portion of the wiring electrode An exposed portion of the substrate is provided therebetween, and the end surface electrode is formed from an end surface of the substrate to an end portion of the wiring electrode via the exposed portion of the substrate.

【0011】また、マザー基板に回路を形成する工程
と、前記マザー基板の少なくとも表面又は裏面に、前記
マザー基板を複数に切断するための切断線から前記マザ
ー基板の基板露出部を設けて、前記回路と接続する配線
電極を蒸着、スパッタリングまたはメッキにより形成す
る工程と、前記マザー基板の切断線で前記マザー基板を
複数の基板に切断する工程と、前記複数の基板の切断面
から前記基板露出部を介して前記配線電極の端部にかけ
て端面電極を厚膜材料で形成する工程とからなるもので
ある。
A step of forming a circuit on the mother substrate; and providing a substrate exposed portion of the mother substrate from a cutting line for cutting the mother substrate into a plurality at least on a front surface or a back surface of the mother substrate. A step of forming a wiring electrode connected to a circuit by vapor deposition, sputtering or plating ; a step of cutting the mother substrate into a plurality of substrates by a cutting line of the mother substrate; and a step of exposing the substrate from a cut surface of the plurality of substrates. Forming an end face electrode of a thick film material to the end of the wiring electrode through the step ( c ).

【0012】[0012]

【作用】上記の構成によれば、基板の縁部と配線電極の
端部との間に、基板露出部が設けられているため、端面
電極は基板の端面以外に基板の端部の基板露出部にも接
合される。また、マザー基板の切断線と、配線電極の端
部との間に基板露出部が設けられているため、マザー基
板の切断の際に配線電極が切断されず、配線電極の端部
に鋭利な突起が発生しない。そのため、配線電極の端部
と接続される端面電極に亀裂が生じない。
According to the above arrangement, since the substrate exposing portion is provided between the edge of the substrate and the end of the wiring electrode, the end surface electrode is exposed to the substrate at the end of the substrate in addition to the end surface of the substrate. It is also joined to the part. Further, since the substrate exposed portion is provided between the cutting line of the mother substrate and the end of the wiring electrode, the wiring electrode is not cut when the mother substrate is cut, and a sharp edge is formed on the end of the wiring electrode. No protrusion occurs. Therefore, no crack occurs in the end face electrode connected to the end of the wiring electrode.

【0013】[0013]

【実施例】以下、本発明による表面実装部品及びその製
造方法の実施例を図面を用いて説明する。図1及び図2
に、本発明の第1の実施例による表面実装部品の部分斜
視図及び断面図を示す。また、図3に、本発明の第2の
実施例による表面実装部品の断面図を示す。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a surface mount component and a method of manufacturing the same according to the present invention. 1 and 2
2 shows a partial perspective view and a sectional view of a surface mount component according to a first embodiment of the present invention. FIG. 3 is a sectional view of a surface mount component according to a second embodiment of the present invention.

【0014】図1及び図2において、1は所望の回路
(図示せず)が形成された、例えば樹脂やセラミック等
からなる基板であり、基板1の表面に、例えばAuやA
g等からなる配線電極2が、蒸着,スパッタリング又は
メッキにより、回路から基板1の縁部方向に引き出され
て形成され、基板1の縁部と配線電極2の端部との間
に、基板露出部1aが設けられている。そして、基板1
の端面から裏面の端部及び表面の基板露出部1aを介し
て配線電極2の端部の表面を覆って、例えばAg,Cu
又はAgPd等の厚膜材料により端面電極3が印刷、焼
成され、表面実装部品5が形成されている。
In FIGS. 1 and 2, reference numeral 1 denotes a substrate made of, for example, resin or ceramic on which a desired circuit (not shown) is formed.
wiring electrodes 2 made of g etc., evaporation, more sputtering or <br/> message key is formed is drawn from the circuit to an edge direction of the substrate 1, and the edge of the substrate 1 and the end portion of the wiring electrodes 2 The substrate exposure part 1a is provided between them. And the substrate 1
To cover the surface of the end of the wiring electrode 2 through the end of the back surface and the exposed portion 1a of the front surface, for example, Ag, Cu
Alternatively, the end face electrode 3 is printed and fired with a thick film material such as AgPd, and the surface mount component 5 is formed.

【0015】また、図3に示すように、基板1の表裏面
に配線電極2,2が形成されさたものにおいても、基板
1の縁部と配線電極2,2の端部との間に、基板露出部
1a,1aが設けられ、基板1の端面から表裏面の基板
露出部1a,1aを介して配線電極2,2の端部の表面
を覆って端面電極3が形成され、表面実装部品6が形成
されている。
Further, as shown in FIG. 3, even in the case where the wiring electrodes 2 and 2 are formed on the front and back surfaces of the substrate 1, between the edge of the substrate 1 and the ends of the wiring electrodes 2 and 2, And substrate exposed portions 1a, 1a are provided, and end surface electrodes 3 are formed to cover the surfaces of the ends of the wiring electrodes 2, 2 from the end surfaces of the substrate 1 via the substrate exposed portions 1a, 1a on the front and back surfaces, and surface mounting is performed. A part 6 is formed.

【0016】このように構成された表面実装部品5,6
は、端面電極3が基板1の端面以外に、基板1の端部の
基板露出部1aとも接合されるため、熱ストレスによる
端面電極3の剥離強度が向上する。
The surface mount components 5 and 6 configured as described above
Since the end face electrode 3 is bonded not only to the end face of the substrate 1 but also to the substrate exposed portion 1a at the end of the substrate 1, the peel strength of the end face electrode 3 due to thermal stress is improved.

【0017】次に、表面実装部品5の製造方法を図4に
示す。まず、基板1の表面積より大きい表面積を有する
マザー基板7が準備される。そして、マザー基板7上に
所望の回路(図示せず)が形成されるとともに、マザー
基板7を複数の基板1に切断するための切断線7aの両
側に基板露出部1aを設けて、マザー基板7の表面に、
例えばAuやAg等からなる配線電極2が、蒸着又はス
パッタリング又はメッキにより形成される。
Next, a method of manufacturing the surface mount component 5 is shown in FIG. First, a mother substrate 7 having a surface area larger than the surface area of the substrate 1 is prepared. Then, a desired circuit (not shown) is formed on the mother substrate 7, and a substrate exposing portion 1 a is provided on both sides of a cutting line 7 a for cutting the mother substrate 7 into a plurality of substrates 1. On the surface of 7,
For example wiring electrodes 2 made of Au or Ag or the like, is more formed on evaporation or sputtering or plating key.

【0018】回路及び配線電極2が形成されたマザー基
板7は、切断線7aで複数の基板1に切断される。その
後、基板1の切段面から裏面の端部及び表面の基板露出
部1aを介して配線電極2の端部の表面を覆って、例え
ばAg,Cu又はAgPd等の厚膜材料により端面電極
3が印刷、焼成され、表面実装部品5が形成される。
The mother substrate 7 on which the circuit and wiring electrodes 2 are formed is cut into a plurality of substrates 1 along cutting lines 7a. Thereafter, the end surface of the wiring electrode 2 is covered with a thick film material such as Ag, Cu, or AgPd to cover the end surface of the wiring electrode 2 from the stepped surface of the substrate 1 through the end of the back surface and the exposed portion 1a of the front surface. Are printed and fired to form the surface-mounted component 5.

【0019】また、基板1の表裏面に配線電極2,2が
形成された表面実装部品6においても、マザー基板7の
表裏面に、切断線7aの両側に基板露出部1aを設けて
配線電極2が形成され、切断線7aで複数の基板1に切
断された後、基板1の切段面から表裏面の基板露出部1
aを介して配線電極2,2の端部の表面を覆って端面電
極3が形成され、表面実装部品6が形成される。
Also, in the surface-mounted component 6 having the wiring electrodes 2 and 2 formed on the front and back surfaces of the substrate 1, the substrate exposed portions 1a are provided on both sides of the cutting line 7a on the front and back surfaces of the mother substrate 7, respectively. 2 are formed and cut into a plurality of substrates 1 along a cutting line 7a.
An end face electrode 3 is formed to cover the surfaces of the ends of the wiring electrodes 2 and 2 via a, and a surface mount component 6 is formed.

【0020】このように構成された表面実装部品5,6
の製造方法においては、マザー基板7の切断線と、配線
電極2の端部との間に基板露出部1aが設けられている
ため、マザー基板7の切断の際に配線電極2が切断され
ず、配線電極2の端部に鋭利な突起が発生しない。その
ため、基板1の端部に設けられ配線電極2の端部と接続
される端面電極3に亀裂が生じない。
The surface mounting components 5 and 6 thus configured
In the manufacturing method of (1), since the substrate exposed portion 1a is provided between the cutting line of the mother substrate 7 and the end of the wiring electrode 2, the wiring electrode 2 is not cut when the mother substrate 7 is cut. In addition, no sharp protrusion is generated at the end of the wiring electrode 2. Therefore, no crack occurs in the end face electrode 3 provided at the end of the substrate 1 and connected to the end of the wiring electrode 2.

【0021】[0021]

【発明の効果】以上説明したように、本発明にかかる表
面実装部品及びその製造方法によれば、基板の縁部と配
線電極端部との間に基板露出部が設けられ、端面電極が
基板の端面以外に基板の端部の基板露出部にも接合され
るため、端面電極の熱ストレスによる剥離強度が向上す
る。また、マザー基板の切断線と配線電極の端部との間
に基板露出部が設けられているため、マザー基板の切断
の際に配線電極が切断されず、配線電極の端部に鋭利な
突起が発生しない。そのため、基板の端部に設けられ配
線電極の端部と接続される端面電極に亀裂が発生せず、
配線電極と端面電極との導通を確実に行うことができ
る。
As described above, according to the surface-mounted component and the method of manufacturing the same according to the present invention, the substrate exposed portion is provided between the edge of the substrate and the end of the wiring electrode, and the end surface electrode is formed on the substrate. In addition to the end surface, the substrate is also joined to the exposed portion of the end of the substrate, so that the peel strength due to the thermal stress of the end surface electrode is improved. Further, since the substrate exposed portion is provided between the cutting line of the mother substrate and the end of the wiring electrode, the wiring electrode is not cut when the mother substrate is cut, and a sharp projection is formed on the end of the wiring electrode. Does not occur. Therefore, no crack occurs in the end face electrode provided at the end of the substrate and connected to the end of the wiring electrode,
Conduction between the wiring electrode and the end face electrode can be reliably performed.

【0022】さらに、回路及び配線電極の表面保護工程
及びバレル研磨工程が不要になるとともに、基板の表裏
面に配線電極が設けられる場合においても、表裏面を同
時に処理できるため、加工工程を簡略化することができ
る。
Furthermore, the step of protecting the surface of the circuit and the wiring electrode and the step of polishing the barrel become unnecessary, and the processing step can be simplified since the front and back surfaces can be processed simultaneously even when the wiring electrodes are provided on the front and back surfaces of the substrate. can do.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例による表面実装部品の部
分斜視図である。
FIG. 1 is a partial perspective view of a surface mount component according to a first embodiment of the present invention.

【図2】図1のA−A線断面図である。FIG. 2 is a sectional view taken along line AA of FIG.

【図3】本発明の第2の実施例による表面実装部品の部
分断面図である。
FIG. 3 is a partial cross-sectional view of a surface mount component according to a second embodiment of the present invention.

【図4】本発明の第1の実施例による表面実装部品の製
造方法を示す断面図である。
FIG. 4 is a cross-sectional view illustrating a method of manufacturing the surface mount component according to the first embodiment of the present invention.

【図5】従来の表面実装部品の部分斜視図である。FIG. 5 is a partial perspective view of a conventional surface mount component.

【図6】図5のB−B線断面図である。FIG. 6 is a sectional view taken along line BB of FIG. 5;

【図7】従来の表面実装部品のマザー基板の断面図であ
る。
FIG. 7 is a sectional view of a mother board of a conventional surface mount component.

【図8】従来の表面実装部品の配線電極の突起を示す断
面図である。
FIG. 8 is a cross-sectional view showing a projection of a wiring electrode of a conventional surface mount component.

【図9】従来の表面実装部品のバレル研磨後の断面図で
ある。
FIG. 9 is a sectional view of a conventional surface mount component after barrel polishing.

【図10】従来の表面実装部品の第2の製造方法を示
す、マザー基板の断面図である。
FIG. 10 is a cross-sectional view of a mother board, illustrating a second conventional method for manufacturing a surface mount component.

【符号の説明】[Explanation of symbols]

1 基板 1a 基板露出部 2 配線電極 3 端面電極 5,6 表面実装部品 7 マザー基板 7a 切断線 DESCRIPTION OF SYMBOLS 1 Substrate 1a Substrate exposed part 2 Wiring electrode 3 End surface electrode 5,6 Surface mount component 7 Mother substrate 7a Cutting line

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H05K 1/02 H01G 4/252 H05K 1/11 H05K 3/40 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H05K 1/02 H01G 4/252 H05K 1/11 H05K 3/40

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 基板と、少なくとも前記基板の表面又は
裏面に蒸着、スパッタリングまたはメッキにより形成さ
れた配線電極と、前記基板の端面及び配線電極の端部を
覆って厚膜材料で形成した端面電極とを有する表面実装
部品において、前記基板の縁部と配線電極の端部との間
に基板露出部を設け、前記端面電極を前記基板の端面か
ら前記基板露出部を介して前記配線電極の端部にかけて
形成したことを特徴とする表面実装部品。
1. A substrate, a wiring electrode formed by vapor deposition, sputtering or plating on at least the front or back surface of the substrate, and an end electrode formed of a thick film material covering an end surface of the substrate and an end of the wiring electrode. Wherein a substrate exposed portion is provided between an edge of the substrate and an end of a wiring electrode, and the end surface electrode is connected to an end of the wiring electrode from the end surface of the substrate via the substrate exposed portion. A surface mount component characterized by being formed over a part.
【請求項2】 マザー基板に回路を形成する工程と、前
記マザー基板の少なくとも表面又は裏面に、前記マザー
基板を複数に切断するための切断線から前記マザー基板
の基板露出部を設けて、前記回路と接続する配線電極を
蒸着、スパッタリングまたはメッキにより形成する工程
と、前記マザー基板の切断線で前記マザー基板を複数の
基板に切断する工程と、前記複数の基板の切断面から前
記基板露出部を介して前記配線電極の端部にかけて端面
電極を厚膜材料で形成する工程とからなることを特徴と
する表面実装部品の製造方法。
2. A step of forming a circuit on a mother substrate, and providing a substrate exposed portion of the mother substrate from a cutting line for cutting the mother substrate into a plurality of pieces on at least a front surface or a back surface of the mother substrate; Wiring electrodes connected to the circuit
A step of forming by vapor deposition, sputtering or plating, a step of cutting the mother substrate into a plurality of substrates with a cutting line of the mother substrate, and a step of cutting the plurality of substrates from the cut surface of the plurality of substrates through the substrate exposed portions of the wiring electrodes. Forming the end surface electrode from a thick film material to the end portion.
JP11871994A 1994-05-31 1994-05-31 Surface mount component and method of manufacturing the same Expired - Lifetime JP3240830B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11871994A JP3240830B2 (en) 1994-05-31 1994-05-31 Surface mount component and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11871994A JP3240830B2 (en) 1994-05-31 1994-05-31 Surface mount component and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH07326830A JPH07326830A (en) 1995-12-12
JP3240830B2 true JP3240830B2 (en) 2001-12-25

Family

ID=14743399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11871994A Expired - Lifetime JP3240830B2 (en) 1994-05-31 1994-05-31 Surface mount component and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP3240830B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4962193B2 (en) * 2007-08-01 2012-06-27 Tdk株式会社 Chip-type electronic component and manufacturing method thereof
KR102179672B1 (en) * 2019-05-29 2020-11-17 주식회사 테토스 Method of forming wiring on side surface of substrate

Also Published As

Publication number Publication date
JPH07326830A (en) 1995-12-12

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