JPH0375959B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to EEPROM (Electrically Erasable
and Programmable Read Only Memory), which can be updated, retain the contents even when the power is turned off, and limit the number of times the contents can be updated. It is something.

[Conventional technology]

In general, in control devices and data processing devices, semi-fixed data or variable data that is generated sequentially during operation is stored in RAM.
(Random Access Memory.) In order to ensure that the contents do not disappear even if the power is cut off, the RAM is maintained in an operating state by a backup power source such as a battery, but if the battery is replaced or Since it requires a switching circuit to a backup power source, EEPROM has recently been used.

[Problem that the invention seeks to solve]

However, current EEPROMs have a limit on the number of times their contents can be updated, and if you store data at a random address like general RAM and update the contents at the same address, it will take a short period of time. This creates a problem in which it is impossible to update the contents in between.

[Means for solving problems]

In order to solve the above-mentioned problem, the present invention is constructed by the following means.

In other words, in a method of storing contents in a memory such as an EEPROM, when storing data for the first time, the data is stored at the first address in the registration area of the memory, and an end mark is stored at the next address. Stores a valid mark indicating that the data is valid at an address other than the area, and when storing the next data, stores the data at the address where the end mark was stored, and stores the end mark at the next address. Thereafter, similar storage operations are repeated as necessary up to the final address of the registration area.

[Effect]

Therefore, data is first stored at the first address of the registration area, then the contents are updated to the address where the end mark is stored, and the next data is stored, and then sequentially until the last address of the registration area. , Since data is stored as needed, the number of contents updated at each address is equal.

〔Example〕

Hereinafter, details of the present invention will be explained with reference to figures showing examples.

FIG. 2 is a block diagram of a device using EEPROM, which includes a processor such as a microprocessor (hereinafter referred to as CPU) 1, fixed memory (hereinafter referred to as ROM) 2, variable memory (hereinafter referred to as RAM) 3,
EEPROMs 4 to 6 and interfaces (hereinafter referred to as I/Fs) 7 and 8 are arranged around the periphery, and these are connected by a bus bar. machine or keyboard,
A terminal device such as a cathode ray tube display device is connected, and a printer (hereinafter referred to as
PRT) 9 is connected.

Here, CPU 1 executes instructions in ROM 2, performs control operations according to input data via I/F 7, accesses necessary data to RAM 3, and also accesses EEPROMs 4 to 6. Then, edit the printout data using the patterns of characters, symbols, etc. stored in EEPROM 4 to 6, and then send it via I/F 8.
The data is sent to the PRT9, thereby causing predetermined data to be printed.

Please note that the patterns of characters, symbols, etc.
You will be given what you need via
It is used after being stored in EEPROM 4 to 6.

FIG. 1 is a diagram showing the storage status of data in EEPROMs 4 to 6. In this example, these are divided into a code area CE and a data area DE, and the data area DE has data DT indicating patterns of characters, symbols, etc. ₀ to DT _o are stored sequentially, and data DT ₀ to DT o are stored sequentially from the first address #0 to the last address #n+1 of the registration area RE in the code area CE.
Data codes DC ₀ to DC _o and end mark EN corresponding to DT _o are stored, and data codes CD ₀ to _{CD o} are valid at address #r other than the registered area RE in code area CE. A valid mark AM indicating that there is a valid mark is stored.

That is, when storing the first data, as shown in (A), the data code DC ₀ is stored in the first address #0, and the end mark EM is stored in the next address #1.
and stores valid mark AM at address #r, while storing data corresponding to data code DC ₀ .
DT ₀ is stored continuously over multiple addresses starting from the first address of data area DE.

Note that the * mark indicates that the data has been newly stored.

Next, as shown in (B), when storing the next data, update the contents to address #1 where end mark EM of registered area RE is stored, store data code DC ₁ , and store the next data. Address #
Store the end mark EM to 2 and save it to the data area.
In the DE, data DT ₁ is stored at each address following data DT ₀ , and thereafter, similar storage operations are repeated as necessary.

Then, as shown in (C), the final address #n+
Data code DC _o is stored at address #n immediately before 1, and an end mark is stored at the last address #n+1.
EM is stored, and data DT _o is stored at the final address in the data area DE.

Note that 2 bytes are used for the data codes DC ₀ to DC _o , and separate codes from the data codes DC ₀ to DC _o are used for the end mark EM and valid mark AM.
Since each of DT ₀ to DT _o is composed of 72 bytes, the number of addresses and storage capacity of each area CE, DE and space are determined according to the number of bytes.

Therefore, in code area CE, addresses #0 and #n+1 are used once each, and addresses #1 to #n
In this case, each address is stored twice, and in the data area DE, each address is stored once, so that the number of times of storage can be averaged.

Also, when reading the contents, first check the valid mark AM in the code area CE, and if this is normal, read from address #0 to end mark EM.
The data code up to the address immediately before the address where is normally stored is valid, and the data in the data area DE may be read and used according to the data code.

Therefore, by using the same procedure, the contents can be checked when the power is turned off and turned on again, and it can be determined whether the contents are valid or not.

In contrast to the above, when clearing the contents and storing them again, either invert each bit of the valid code AM at the same time as clearing, or clear each bit to make sure that all the contents have been cleared. Can be displayed.

Figure 3 is a flowchart of the storage operation by CPU1.
Is there AM? ”101, and if it is NO, store the data code DC ₀ to address #0 with “DC ₀ → # 0” 111, and store data DT ₀ in the data area DE with “DT ₀ → DE” 112. up,
“EM→#1” 113 stores the end mark EM at address #1, and the valid mark “AM→#1”
r''114, it is stored at address r.

Also, if step 101 is NO, “DCi→
The i-th data code DCi is stored at the address where the end mark EM is stored using the stored address of EM"121, and the i-th data DTi is stored as "DTi→
DE" 122, and then the end mark EM is stored at the next address in step 121 using the end mark "EM→EM stored address + 1" 123.

FIG. 4 is a flowchart showing a similar read operation.
If YES, it is determined that the contents from the address "#0 to the address immediately before EM are valid" 211, and a data area "reading of corresponding data from DE" 212 is performed.

On the other hand, when step 201 is NO,
“Content invalid” 221 is determined.

However, in Fig. 1, the data DT ₀ to DT _o
Since the number of bytes is large, a data area DE was provided separately from the code area CE, but data DT ₀ to
If the number of bytes in DT _o is small, the code area CE
and data code as DC ₀ ~ _{DC o}
DT ₀ to DT _o may be stored, and in the case of the configuration shown in Figure 1, data DT ₀ is stored in the data code DC ₀ to _{DC o.}
~ Add the storage address code of DT _o , or
CPU1 outputs data according to data code DC ₀ ~ _{DC o.}
Determine the storage address of DT ₀ to DT _o and set the code area
The storage addresses may be sequentially determined in the DE, and the configuration shown in FIG. 2 can be arbitrarily selected depending on the conditions, and various other modifications are possible.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, in a memory such as an EEPROM where the number of times of content update is limited, the content is updated an equal number of times for each address, and the number of content updates is not concentrated at a specific address. First, the overall lifespan of the memory is extended, and a remarkable effect can be obtained as a method of storing the contents of such a memory.

[Brief explanation of drawings]

The figures show an embodiment of the invention, FIG.
Diagram showing how data is stored in EEPROM,
Figure 2 is a block diagram of a device using EEPROM.
Figure 3 is a flowchart of the storage status by the CPU.
FIG. 4 is a flowchart showing a similar read situation. 1...CPU (processor), 4 to 6...
EEPROM (memory), CE……Code area, DE
...Data area, RE...Registration area, DC ₀ ~
DC _o ...Data code, EM...End mark,
AM...Valid mark, DT ₀ to DT _o ...Data.

Claims (1)

[Claims] 1. In a method of storing contents in a memory whose contents can be updated, retains the contents even when the power is turned off, and controls the number of times the contents are updated, Stores data at the first address in the registration area of the memory, stores an end mark at the next address, stores a valid mark indicating that the data is valid at an address other than the registration area, and stores the next data. Sometimes, data is stored at the address where the end mark is stored, and the end mark is stored at the next address, and the same storage operation is repeated as necessary until the final address of the registration area. Featured memory content storage method.