KR830000696B1 - Data processing systems - Google Patents

Abstract

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Description

Data processing systems

1 is a schematic diagram of a data processing system according to the present invention;

2 is a detailed view of the memory MEM of FIG.

FIG. 3 is an illustration of the development of the contents of register Y in FIG. 1 in the operation of the FIG.

The present invention relates to a data processing system, comprising: a memory having a plurality of blocks of a plurality of memory locations having at least one block containing a memory location storing an instruction having a first address information referring to second address information; And the address of the memory location that is earlier in this block, so that the second address information can be obtained with the help of the first address information stored in the memory location mentioned above. The invention relates to a data processing system comprising a computer with a processor that can address a memory location in any of the blocks mentioned above with the aid of means for indicating whether a address should be finally assigned.

Such data processing systems are well known in Belgian patent 823,300 (H. Janssens 1). This known system contains two memory blocks or banks in particular, and with the aid of the second address information the means of indicating which of them should be addressed last is called a so-called tank flip-flop. Teaches each of the two banks. During the execution of the above-mentioned command, for example in the above case, in order to melt this unique bank flip-flop in either of the two states at a suitable moment during the period of its so-called indirect cycle, It has a pair of auxiliary flip-flops, logic circuits, and a series of special control commands. Just before the above-mentioned command is addressed in memory, the computer executes the appropriate one of the above control commands to put the auxiliary flip-flops in the proper state, and during the subsequent execution of the command, the computer logic circuit banks according to the state of the auxiliary flip-flop. Place the flip-flop in either of two states.

In view of the foregoing, it can be assumed that the means for indicating the memory block to be last addressed is relatively complex and a relatively long time is required to control the bank flip-flop and the auxiliary flip-flop.

Belgian patent bank flip mentioned above in an article titled "The 8086 Microcomputer bridges the gap between 8-bit and 16-bit designs," published on February 16, 1978, in pages 94 through 104. Here is how memory capacity can be extended by using segment registers, which can be seen as an extension of a flop. This allows any memory location to be obtained by adding it to the address of the location in the memory segment consisting of the multiple segments mentioned above. This means that a stock price action is necessary to obtain the necessary address.

It is therefore an object of the present invention to provide a system which does not have drawbacks as the data processing system of the Belgian patent disclosed above. This purpose is to provide a means for the extended portion of one memory block to indicate which of the second memory locations and the blocks to which each of the blocks which have stored the second address information respectively have to be finally addressed. The present invention is achieved by having an electronic processor that obtains the second address information, which is obtained by addressing the second memory location, using the first part of the second address information and the first address information. .

Since the second address information can address any memory block by itself, no longer computer time is consumed than is required in a system containing one memory block. You only need a little more memory space to store the second address. In addition, according to this method, it is noted that the computer memory can be expanded up to several memory blocks without the modification of the computer instruction form. In fact, as mentioned above, the second address information is obtained by a simple indirect addressing process which is normally performed by any computer. In another aspect of the present invention, a data processing system as defined at the beginning of the present description is directed to that the red blocks of the memory blocks described above are divided into words of two different lengths and the memory locations within the memory block. It is characterized in that it stores shorter words that can be addressed, and longer words that can address memory locations in any other block. The advantage that such a system provides is that the existing set of instructions of a computer operating on a word of any length, such as a 16-bit word, is usually beyond the range normally defined by the above length. Even when it is stretched, it can be kept as it is. In addition, by having a word of increased length with a fractional value, such as an 18-bit word, in addition to the word of the original length, it has been proved that a memory configuration capable of providing great flexibility in programming in addition to the increase of the memory range has been proved. . The present data processing system according to the preferred embodiment includes a processor and a computer having memory divided into four memory blocks.

Each memory block has a storage capacity of 64K (K = 1024) words, an 18-bit 2K word and a 16-bit 62K word. This means that 2 ⁹ = K / 2 words out of 2K 18-bit words can be called by the 9-bit addresses contained in the 16-bit instruction word. It allows you to have four times as much memory as the maximum capacity of 2 ¹⁶ = 64K words. The remaining 3K / 2 18-bit words can be used for data with 62K 16-bit words.

Referring to FIG. 1, there is a data processing system including a computer having a memory (MEM), a processor (CPU) in which only an arithmetic unit (AU) and a controller (CU) are displayed. This treatment system is in the form of the Belgian patent mentioned above. The arithmetic unit AU is an 18-bit memory buffer register for storing words to be written to and read from the memory location of the memory MEM, and an 18-bit memory for storing into the memory location of the memory location of the memory MEM. Place register Y, an 18-bit accumulator register A, and an 18-bit instruction counter P for storing the address of the instruction to be made or performed. The memory buffer register M and the memory location register Y are associated with the memory MEM through the distribution bus DB, which is a gate circuit controlled by the control unit CU via the control line CW. The memory buffer register M, the memory location register Y, the accumulator A and the instruction counter P are connected to another gate circuit (GC), which (GC) connects these registers to each other to allow the exchange of information between them. These are controlled by the control unit CU via the control line CW. The gate circuit (GC) is of the type known, for example, from Belgian patent 776495 (S. Kobus et-al 26-3-2). The control unit CU has a conventional logic circuit LC having a 16-bit register F and an electric control line CW. The input of register F is connected to the output of the distribution bus (DB) and the output is connected to the logic circuit (LC). The output from the control line CW of the logic circuit LC is connected to the distribution bus DB and the gate circuit GC. The register F is for storing the word read from the memory MEM, while the logic circuit LC performs a control function well known in computer technology as in Belgian patent 823,300.

Referring to FIG. 2, the memory MEM has four memory blocks MB0 to MB3 (only NB0 and MB3 are drawn), and each block has 64K memory locations. The memory block MB0 contains a partial NEAO of the 62K 16-bit memory location but not with the fixed partial EAO locations of the 2K 18-bit memory locations. The extended partial EAO is divided into two zones EAO (S0) and EAO (S1) for memory locations of K / 2 and 3K / 2, respectively. The memory locations of EAO (S0) store 18 bits of valid Operand addresses, such as EOA, and the memory locations of EAO (S1) store 18-bit datawords, meaning all kinds of wordwords in addition to instruction words. Save it. The NEAO portion of MB0, which is not an extended portion, stores 16-bit instruction words and data words. Memory block MB3 is similar to MBO and stores similar information words.

With reference to FIGS. 1 to 3, the following will describe the operation of the above data processing system, all operations being controlled by the control unit CU of the processor CPU, in particular the logic circuit LC of the CU. do.

Instruction counter P and register Y initially store an 18-bit address (Figure 3). Since 18-bit address A is 2 ¹⁶ = 64K, 16 bits of the memory location within each block from memory blocks MB0 to MB3. Suppose we have 16 bits from 0 to 15 forming the partial address U, and two address bits 16 and 17 bits that designate one of these memory blocks. According to the address A stored in the register Y, the control unit CU has a memory MEM and in particular a partial address U in the memory block MB0 such as the additional bits 16 and 17 of address A, for example 00 in FIG. The memory location ML1 in the figure is addressed.

As a result, the 16-bit instruction word stored in ML1 of FIG. 2 is transferred from this memory location to the memory buffer register as well as register F. The instruction word is a 16-bit load-ad accumulator consisting of a 9-bit address V stored in ML1 0 through 8 bits and a 2-bit exponent K stored in 9 and 10 bits of ML1. Same as the A command. This K-index corresponds to bit 10 and bit 10 corresponds to area S0 (2) in the memory block such as area EAO (S0) to EA3 (S0) where the 9-bit address V is in the memory blocks MB0 to MB3. Indirectly addresses a word in ⁹ = K / 2 words) and indicates that it is an address for addressing a 5-bit operation code in bits 11 to 15 of ML1.

The operation code CLDA and the exponent K are analyzed in the logic circuit (LC) and as a result, the instruction is loaded on the accumulator A, and the operation loaded here is a memory location having an effective address obtained with the help of the partial address V in the instruction. It should be executed according to the word stored in it. As a result, the logic circuit (LC) first calculates the indirect address IA by putting address V of the LDA instruction in bits 0 to 8 of register Y and 0 in the remaining 9 to 15 bits. The indirect address IA is thus finally obtained from register Y. Since IA is 2 ⁹ = K / 2, the 9 bits of the memory location and the partial address V in each area S0 of blocks MB0 to MB3 are divided from 0 bits to 8 bits of IA. 9 to 9 bits and 0 to the additional bits 16 and 17 bits to indicate the memory block MB0.

Thus, the control unit CU addresses the memory MEM with the indirect address IA stored in the register Y, in particular with the address V in the area EAO (S0) of MB0.

As a result, the 18-bit word stored in ML2 constitutes the so-called valid Operaland address EAO and is transferred from MB0 to the memory buffer register and to the next register Y. As in FIG. 3, this includes additional bits 16, 17, such as 11, indicating memory block MB3, and the 16-bit partial address W of the memory location in block MB3.

By the address EAO stored in the register Y, the control unit CU addresses the memory location ML3 belonging to the memory MEM and in particular to the determined area EA3 (S1) of MB3.

Thus, the 16-bit dataword DW is passed to the memory buffer register M for further processing. However, this operation process is not indicated because it is not important in the present invention.

It is clear that the additional bits 16 and 17 bits of the effective Operland address EOA indicate the memory block that should be addressed last and as a result any of these blocks can be addressed. Obviously both extended and unextended portions of this block can be addressed so that not only 18 bits but also 16 bits of dataword can be obtained. For example, if a jump instruction is performed, an 18-bit return address obtained by increasing the contents of the instruction counter by 1 is stored in the extended portion of the memory block MBO.

In summary, the partial address V in the instruction word read from memory location ML1 in memory block MB0 allows memory location ML2 in extended region S0 of the same memory block MB0 to be addressed. In the memory block MB0, an extended address EOA is stored which enables a data word of 16 or 18 bits to be finally obtained from any of MB3. As shown in FIG. 2, each block from the memory blocks MB0 to MB3 has a fixed portion EA0 to EA3 and an unexpanded portion NEA0 to MEA. Indeed, since the use of a block of memory that has an unextended portion is more convenient than the use of a block of memory that has both an extended portion and an unextended portion, for this reason additional bits of the portion to be expanded of one or more independent memories Stored on the device. In this case, it may be pointed out that 2K × 2 additional bits of the memory portion to be expanded must be stored in the corresponding 2K × 2 bit memory device. Unfortunately, such a 2K × 2 bit memory device is currently unavailable, so a usable 4K × 1 bit memory device has been used. Additional bits of 2K × 2 bits are stored in a similar group of two 4K × 1 memory devices, respectively, in order to be able to simultaneously address 0 to 15 bits and an additional 16 and 17 bits of the unextended memory block. In general, at least q rows of additional memory devices are used to determine m rows of n × pbit memories each having q additional bits, where the additional memory devices in the similar row store q additional bits together. There are things.

While the principles of the invention have been described above in connection with specific devices, this description has been made by way of example only, and in no way implies a limitation on the scope of the invention.

Claims (1)

Address any memory location in an electrical block and a memory divided into blocks of multiple memory locations with at least one block containing a memory location that stores instructions containing the first address information referring to the second address information. The second address information can be obtained with the help of the first address information stored in the memory location, and the blocks described above with the help of means indicating which address information and which block of memory should be finally addressed twice. A computer with a processor that can address a memory location in any of the blocks, The extended portion (EAO) of the electric memory block (MB0) has a group [EAO (S0)] of the second memory location (ML2), each of which stores the second address information posted; The first part of the second address information is constituted by means for instructing to obtain the second address information posted by addressing a memory location, in which the posted blocks are finally addressed and the electric processor posts in the middle of the address information V posted by the electric processor. And a data processing system.

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