JPH0391046A - Data processor - Google Patents

Abstract

PURPOSE:To improve efficiency for allocating a real memory and to improve the performance of a whole system by executing the reallocation of the real memory while limiting the position only when a program uses a real address. CONSTITUTION:A real address comparator circuit 500 is provided in an address converting circuit 5 and an interruption signal 160 is generated according to whether or not the real address as the result of address conversion satisfies the allocation position of the real memory on an address conversion table 302 when a page is fixed. According to this interruption, an interruption processing routine 303 is operated by an interruption processing routine activating circuit 600 as one kind of program interruption in a conventional data processor. Thus, the interruption processing routine is operated only when an instruction is issued to obtain the real address and further, the interruption is generated only when the real address is not suitable. Then, it is enough for an operating system to adjust the position of the real memory with the interruption as a chance, and the unnecessary allocation to a low-order real memory address area is eliminated. Thus, the efficient allocation of the real memory is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a virtual memory computer system, and particularly to a data processing device suitable for real memory allocation in a computer system having multiple addressing widths.

[Conventional technology]

The conventional method uses the rt, oc=3 parameters of the G-bit TMALN macro to determine the virtual memory location and the virtual The actual storage location is determined when the storage is page-fixed. What is page pinning?
The real memory location allocated to a virtual page is fixed,
This is a state that is not subject to paging. Therefore, if a page is not fixed, the corresponding real memory location becomes undefined due to paging processing, so access from the program to the page at the real address does not need to be guaranteed, and only when the page is fixed as described above. The method used was to specify the location of the real memory using a new parameter (LOG=) of the GHTMAIN macro when the virtual memory was secured. In addition, conventional programs without the parameter specified are page-fixed to a lower area of real memory.

Furthermore, page fixing is often used in programs where responsiveness is important to eliminate paging overhead and improve performance, and in this case it is rare for a program to directly access real addresses.

[1] Problems to be Solved by the Invention] [In the above-mentioned conventional technology, the location of real memory is determined when a page is fixed, regardless of whether access is made using a real address. The page is fixed,
There is a problem in that even if the high-level area of the real memory is empty, the allocation is concentrated in the low-level area of the real memory, which in turn causes a negative effect on system performance due to a decrease in the utilization efficiency of the entire real memory.6.Objective of the present invention The object of the present invention is to provide a data processing device that realizes efficient real memory allocation by reallocating real memory only when a program actually operates on real memory.

[Means to solve the problem]

Provided with a real address comparison circuit that checks whether or not the real address that is the processing result of the instruction matches a predetermined real memory location when the page is fixed, when processing an instruction to obtain a specific real memory address, Only in the case of non-compliance, the comparison circuit generates an interrupt, and the operating system uses the interrupt as a trigger to reallocate real memory that matches the real memory location at the time of page fixation.

[Effect]

When a program actually manipulates a real address, the real address comparison circuit, for example, uses an instruction to obtain a real address (L
RA: Load HeaIAddress) is issued, and furthermore, an interrupt is generated only in the case of a real address mismatch, and the operating system uses the interrupt as a trigger to adjust the location of real memory (reallocate real memory). If this is done, unnecessary allocation to the lower real storage address area as described above can be eliminated.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the present invention. FIG. 1 shows a configuration diagram of this embodiment. In FIG. 1, 3 is a processing device, 10 is an instruction word register that holds instructions to be processed, 4 is an instruction analysis circuit that analyzes instructions, and 5 is an instruction An address conversion circuit that converts a virtual address specified by an operand into a real address, 500 a real address comparison circuit that checks the position of a real address, and 600 an interrupt process that operates when an interrupt signal 160 is generated by the real address comparison circuit. A routine starting circuit, 300 a main memory, and 302 an address conversion table.

303 is an interrupt processing routine of the operating system.

In this embodiment, the address conversion circuit 5 includes a real address comparison circuit 5.
00 is set, and an interrupt signal 160 is generated depending on whether the real address that is the address conversion result satisfies the real memory allocation position when the page is fixed on the address conversion table 302, and the interrupt processing routine is started by the interrupt. The feature is that one circuit 600 operates an interrupt processing routine 303 as a kind of program interrupt of a conventional data processing device.

The operation of one embodiment of the present invention will be explained below.

There are two types of addressing in computer systems: 24 bits and 31 bits, and an instruction (LRA: LoadHeal A) to obtain a real address corresponding to a virtual address is used.
The processing of ddress (hereinafter referred to as LRA) will be explained as an example.

In FIG. 1, an LRA instruction is fetched into the instruction word register 10, and when the instruction analysis circuit 4 analyzes that it is an LRA instruction, the next First, the address translation circuit operates to obtain an address. The simulated operation of the address translation circuit is shown in FIG. 2. In FIG.
0 is the instruction word register, 50 is the virtual address specified by the LRA instruction, 80 is the segment table, 100 is the page table, 110 is the real address obtained by executing the LRA instruction, and 120 is the PSW (
102 is a flag indicating the real memory allocation position condition on the page table entry 101, and 500 is a real address comparison circuit that compares the flag 102 with the above real address 10. Address conversion circuit of this embodiment. is the real address comparison circuit 5
The feature is that 00 is provided, and the operation other than this circuit is the same as before. The execution process of the LRA instruction will be described below, and then the operation of the real address comparison circuit 500 will be explained.

The LRA command is rLRA Rt, Us (Xz, Bz)J
is coded as instruction word register 10 inside the computer.
As shown in Rtl 1. Xzl 2. Bzl 3゜D
214 fields, converts the virtual address specified by the second operand (Dz (Xz, Bz)), and stores the obtained real address in register R.
z11. This is an instruction to set it to O. The command is, first,
Register X specified by fields XxL2 and Bzl3
z20. Hz30 and field Dz14%
40 L, and the resulting virtual address 50 is obtained.

At this time, in the addition 40, according to the addressing mode 121 of 1'511120, the register Xs 20 t H
Determine the effective length of x30. The address conversion of the virtual address 50 is performed in the same manner as before, and the 1st to 11th bits of the virtual address 50 are multiplied by 4 (segment table entry length) by shift 60, and added to control register l by 7.
0 and the segment entry 81 on the segment table 80 is found. Next, the first real address of the page table on the entry 81 and the first virtual address 50 are
Bits 2 to 19 are added (4 times by shift 90, ie, multiplied by the page table entry length) #91 to obtain the page table entry 101. The real page address 103 on the entry is set to bit 1 of register RIIIO.
~19 and set bits 20-31 to virtual address 5.
Execution of the conventional LRA instruction ends by setting the lower 12 bits of 0.6 In the present invention, the register RzllO
The above real addresses are compared by the real address comparison circuit 500. In the circuit 500, first, in the selector 530, one of the bit patterns 510 and 520 is selected by the M selected bit pattern ( 510 or 520) and bits 1 to 7 of the real address on the register RzllO are ANDed.
540 and becomes a signal 150. Next, the decoder 550 converts the instruction code into 0. Alternatively, a signal 155 of 1 is generated, and the AND signal 150 and 155 are generated by AND560.
is taken, resulting in a second interrupt signal 160.

In this embodiment, as described in the conventional technology section, Gl<TMAI
The real memory location when the page is fixed is 1, which is determined by the parameter (LOG = specification or default value) when issuing the N macro.
If it is less than 6M, the value of the flag 102 indicating the real memory allocation position condition is O. Otherwise, it is set to 1. If the flag 102 is O, the bit pattern 520 is selected by the selector 530, and the bit pattern of the real address is set to 1. If 1 to 7 are not all zeros and the instruction code is an LRA instruction, the interrupt signal 160 is turned on.
When the A instruction is executed and the interrupt signal 160 is on, the interrupt processing routine starting circuit 600 shown in FIG. 1 further operates.

Next, according to FIG. 3, the interrupt processing routine starting circuit 600
In third countries, this interrupt processing is a conventional page fault (a type of program interrupt that occurs when the virtual area you want to use does not exist on real memory, and this triggers the operating system's real memory allocation However, in addition to the case of a page fault, the real address at the time of interrupt occurrence (register RIIIO) is saved in the save area 2 in the interrupt control information area 301 in the main memory 300.
The difference is that it is saved in 01. The outline of the processing when the interrupt signal is turned on will now be explained with reference to FIG.

As described above, it operates when the interrupt signal 160 is on, and sends psvtzo pointing to the instruction address of the LRA instruction 10 to I! The APSW store circuit 170 stores the code representing the LRA interrupt in the save area 171 on the main memory 300, and stores the code representing the LRA interrupt. , 11 path 180 saves the LRA interrupt generation virtual address in the save area 181, and stores the LRA interrupt generation virtual address in the LRA interrupt generation virtual address store circuit 1.
The LRA interrupt occurrence real address is saved in the save area 191 in step 90 , and the LRA interrupt occurrence real address is saved in the save area 201 in the LRA interrupt occurrence real address storage path 200 . After saving 0 or more information used by the interrupt processing routine 303 of the operating system shown in FIG. 4, the PSW for the program interrupt processing routine 303 is activated from the area 211. The interrupt processing routine 303 of the operating system shown in FIG. 1 is activated by loading the interrupt processing routine 303 into the PSV 120 by the circuit 210. Next, the processing of the interrupt processing routine 303 will be described with reference to FIG. FIG. 4 shows a schematic flowchart of the interrupt processing routine 303. In FIG.
0 is the conventional processing unit 0 As shown in the figure, first, processing 4
At step 10, it is determined whether the interrupt is an LRA instruction interrupt or not. This is determined based on the interrupt code saved in the save area 181 in the process shown in FIG. If the interrupt is not an LRA instruction, the conventional processing unit 460 analyzes other interrupt factors and performs corresponding processing. If it is an LRA instruction interrupt, processing 420 prepares the real storage area specified at the time of virtual memory reservation, that is, one real page with a real address of less than 16MB (megabytes), and processing 430
The real page (address is saved in the save area 201 in the process shown in FIG. 3) that caused the LRA instruction interrupt to the real page.
It is also possible to directly refer to the real page address 103 on the page table entry 101 in the figure, and the present invention is not dependent on saving the real address itself.) Next, the address image conversion table ( In order to modify the real page address 103 on the page table entry 1oi) in FIG.
The address of the newly prepared real page is set in the page table entry 101.

Finally, in process 450, the real page that caused the L length A instruction interruption (the page at real page address 103 before process 440 was executed), which is no longer needed, is brought into an unused state and made available for reprint.

With the method described above, it is only necessary to limit the real memory location only when it is minimally necessary to guarantee the operation of the program triggered by the execution of the LRA instruction, and in other cases, any real memory area can be used. According to this embodiment, the processing overhead of the operating system can be reduced, and furthermore, the frequency of use of real memory with a small capacity of less than 16MB can be reduced, and allocation conflicts of real memory less than 16M13 will not occur. This has the effect of improving system performance.

〔Effect of the invention〕

In the present invention, a real address comparison circuit is provided, and real memory location-limited reallocation is performed only when a program actually uses a real address. Therefore, the frequency of real memory location-limited reallocation is reduced, and the operating system This has the effect of reducing processing overhead, reducing the frequency of allocation conflicts, improving the efficiency of real memory allocation, and improving the performance of the entire system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the present invention, and FIG. 2 is a real address comparison circuit (500) exemplifying an LRA instruction according to an embodiment of the present invention.
FIG. 3 is an explanatory diagram of the operation of the interrupt processing routine starting circuit (600) according to the present embodiment, and FIG. 4 is a schematic flowchart of the interrupt processing routine of the operating system that operates in response to an interrupt generated by the LRA instruction. figure. 3...Processing device, 4...Instruction analysis channel, 5...Address conversion circuit, 10...Instruction word register, 80...
・Segment table, 100...page table,
120... psw (program status word'), 121
... Addressing mode, 160 ... Interrupt signal, 303 ... Interrupt processing routine, 400 ...
Real memory position key! ! (Transfer #) Processing unit, 500... Real address comparison circuit, 600... Interrupt processing routine starting circuit. Figure 1 Figure 2 Figure 3 Figure 4 303 1st [! l

Claims (1)

[Claims] 1. In a computer system that uses a virtual memory method and has multiple addressing widths, check whether the real address obtained as a result of instruction processing matches the predetermined real memory location when the page is fixed. The present invention is characterized by being provided with a real address checking circuit which generates an interrupt in the case of non-conformity and requests the operating system to reallocate real memory that conforms to the real memory location specified at the time of page fixation. Data processing equipment.