JPH0373632A - Communication equipment - Google Patents

Abstract

PURPOSE:To eliminate the need for a PLL circuit and to attain efficient data transfer by generating a correction clock synchronously with a received data from a reference clock as soon as a specific logic level detection means detects the reception data and fetching the received data. CONSTITUTION:An inverse of Q output of a flip-flop 1 and a reference clock 6 are NANDed by a NAND gate 4 and the result is inputted to a flip-flop 2. The inverse of Q output of the flip-flop 2 and an output 8 of the NAND gate 4 are NANDed by a NAND gate 5 and the result is inputted to a flip-flop 3. A Q output 10 of the flip-flop 3 is synchronized with the leading of the reference clock 6 as a correction clock synchronously with the received data whose frequency is a half the frequency of the reference clock. The correction clock is used to allow a data latch section to latch the reception data and it is sent to a next stage code conversion section.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication device that immediately synchronizes asynchronous data and performs reception, code conversion, and transmission.

[Conventional technology]

In the conventional example, as in Japanese Patent Application Laid-Open No. 61-129936, the Kugata signal is sampled using a sampling clock,
It is based on a PLL circuit that uses a phase shift circuit to adjust the phase. Furthermore, most of the communication transceivers on the market use the first half method.

[Problem to be solved by the invention]

A transceiver device in a conventional communication system receives a data transmission confirmation signal from the data generation controller side, supplies a data transfer clock to the controller side, receives data synchronized with that clock, and transmits it to the line side. do.

In addition, for the 1st line side, a preamble signal (for PLL synchronization) set in the first few dozen bits of received data is received, and after the PLL circuit completes synchronization, the data is code-converted and sent to the controller side. are doing.

An object of the present invention is to simplify the communication operation described above, by making it possible to immediately sense and receive asynchronous data, so that the controller side does not need to be supplied with a clock for data transfer.
On the line side, an attempt was made to eliminate the PLL circuit and improve the efficiency of data transfer by eliminating the need for a preamble signal.

[Means to solve the problem]

In order to achieve the above purpose, a specific logic level such as logic 10' is always placed at the beginning of the transmitted/received data, and a specific logic level detecting means for detecting this is provided, and the transfer rate is at least twice as high as the transfer rate. The frequency of the reference clock is divided by at least 2 from the first rising edge half a clock period after the timing at which the specific logic level is detected by the specific level detection device. By obtaining the frequency-divided output as the correction clock, it is possible to latch the received data in the next stage.

[Effect]

At the same time as the specific logic level detection means detects the received data, a correction clock synchronized with the received data is generated from the reference clock, and the received data can be captured and processed using the correction clock.

〔Example〕

Below-1 Regarding one embodiment of the present invention, Fig. 1, Fig. 2,
This will be explained using FIGS. 3 and 4.

FIG. 1 is a block diagram of a communication transceiver device showing an embodiment of the present invention. 1 is a transceiver device, 2 is a data generation controller, 3 is a line, 4 is a correction clock generation circuit, 5 is a data latch circuit, 6 is a line transmission/reception circuit, 7 is a code converter, 8 is a received data level converter,
9 is a code conversion section, and 6 to 9 use conventional circuits.

The basic operation of the present invention consists of 4 and 5 circuit sections. 2nd to 4th
Details will be explained with reference to figures.

In Figure 2, 1, 2.3 are D type positive edge trigger flip props (preset PR
, with clear CR), and 4.5 are clock generation sources with twice the frequency of the received data.

FIG. 3 shows transmitted and received data with a specific logic level ``O''.

FIG. 4 is a timing chart of signals of each part in FIG. 2 when the data in FIG. 3 is received. First, C
), flip-flop with R signal.

Initial settings are performed in 2.3. Next, when the received data is input to the flip-flop, its Q output (Q of 1) is held at 1H. However, it is assumed that %Ot is always input to the beginning S of the received data. The flip-flop 1 detects this and sets its output Q to 1H'.

Next, the Q output of the free flop 1 and the reference clock 20
When the NAND is performed with the NAND gate 4 and the resulting output 8 is input to the flip-flop 2,
In synchronization with the first rising edge of output 8, the output Q of flip-flop 2 changes.

% Hj. When the Q output of the flip-flop 2 and the output 8 of the NAND gate 4 are NANDed at the NAND gate 5, and the output 9 is inputted to the flip-flop 3, the Q output 1o of the flip-flop 3 is obtained.
In synchronization with the rising edge of the output 9 and therefore the reference clock 6,
Furthermore, an output obtained by dividing the frequency of the reference clock by two is obtained as a correction clock synchronized with the received data. Using the corrected clock, the data latch section latches the received data and sends the data to the next stage code conversion section.

[Effects of the Invention] According to the present invention, data transmission and reception can be performed efficiently (data deletion for PLL synchronization), and synchronization can be performed using simple TTL logic instead of a PLL circuit. The circuit can be simplified.

[Brief explanation of drawings]

Fig. 2 is a block diagram of a communication transceiver according to an embodiment of the present invention, Fig. 2 is a correction clock generation circuit diagram showing the basic operation of the invention, Fig. 3 is an explanatory diagram of received data specifications,
FIG. 4 is a timing chart. DESCRIPTION OF SYMBOLS 1... Transceiver device, 2... Controller for data generation, 3... Line, 4... Correction clock generation circuit. 7.9...Code conversion section. Estimated diagram 3 Figure [Experimental discharge rate i+

Claims (1)

[Claims] 1. In a communication system that transmits and receives data using circuits and dedicated lines, the beginning of the transmitted and received data is sent to the transceiver device that receives data, converts codes, and transmits data between the data generation controller and the circuit. a specific logic level detection means for detecting a specific logic level that is always located at a reference clock; A communication device characterized in that a synchronized correction clock is generated from a reference clock, and the correction clock is used to capture and process received data.