JPH0373024U - - Google Patents
Info
- Publication number
- JPH0373024U JPH0373024U JP13445489U JP13445489U JPH0373024U JP H0373024 U JPH0373024 U JP H0373024U JP 13445489 U JP13445489 U JP 13445489U JP 13445489 U JP13445489 U JP 13445489U JP H0373024 U JPH0373024 U JP H0373024U
- Authority
- JP
- Japan
- Prior art keywords
- output
- data
- subtracter
- storage means
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims 1
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000001514 detection method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Description
第１図はこの考案の一実施例の構成を示すブロ
ツク図。第２図はこの考案の一実施例の作用の説
明を供する積分出力波形図。第３図は従来例の構
成を示すブロツク図。
１……バンドパスフイルタ、２……Ａ／Ｄ変換
器、３……ＦＩＦＯ、４……デジタルマルチプラ
イヤ、５……デジタルフイルタ、６……Ｄ／Ａ変
換器、１１……リミツタ、１２……積分器、１３
……減算器。
FIG. 1 is a block diagram showing the configuration of an embodiment of this invention. FIG. 2 is an integral output waveform diagram illustrating the operation of an embodiment of this invention. FIG. 3 is a block diagram showing the configuration of a conventional example. 1...Band pass filter, 2...A/D converter, 3...FIFO, 4...Digital multiplier, 5...Digital filter, 6...D/A converter, 11...Limiter, 12... ...integrator, 13
...Subtractor.
Claims (1)
とするリミツタと、リミツタからの出力を積分す
る積分器と、積分器の出力をデジタル変換するＡ
／Ｄ変換器と、Ａ／Ｄ変換器により変換されたデ
ータの隣接データの差を演算する減算器と、減算
器の出力データを一時記憶して所定時間遅らせて
出力する記憶手段と、減算器からの出力データと
記憶手段によつて遅らされたデータとを乗算する
乗算手段と、乗算手段の出力をＤ／Ａ変換するＤ
／Ａ変換手段とを備えたことを特徴とするデジタ
ルクオドラチユア検波回路。 A limiter that limits the amplitude of a frequency modulated signal to maintain a constant amplitude, an integrator that integrates the output from the limiter, and A that converts the output of the integrator into digital.
A/D converter, a subtracter that calculates the difference between adjacent data of data converted by the A/D converter, storage means that temporarily stores the output data of the subtracter and outputs it after a predetermined time delay, and the subtracter. a multiplication means for multiplying the output data from the storage means by the data delayed by the storage means; and D for D/A converting the output of the multiplication means.
1. A digital quadrature detection circuit comprising: /A conversion means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13445489U JPH0373024U (en) | 1989-11-21 | 1989-11-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13445489U JPH0373024U (en) | 1989-11-21 | 1989-11-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0373024U true JPH0373024U (en) | 1991-07-23 |
Family
ID=31681793
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13445489U Pending JPH0373024U (en) | 1989-11-21 | 1989-11-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0373024U (en) |
-
1989
- 1989-11-21 JP JP13445489U patent/JPH0373024U/ja active Pending
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