JPH0372693A - Interconnecting member and forming method therefor - Google Patents

Abstract

PURPOSE:To improve electric reliability of upper layer interconnection in an interconnecting member having a multilayer interconnection structure by forming a coated type second insulating film only on a recess except a protrusion formed of lower layer interconnection of a deposited type first insulating film. CONSTITUTION:An insulating film 4B of an intermediate layer of interlayer insulating film 4 is formed on a whole board surface on an insulating film 4A. The film 4B is formed of a silicon oxide film coated by a SOG method. This silicon oxide film is made of organic material mixed with methyl group. The silicon oxide film coated by the SOG method is formed in a small thickness of about 100[nm] on the protrusion on first layer interconnection 3, and formed in a large thickness of about 30[nm] in the recess between first layer interconnections 3. Then, the whole board is etched to remove the film 4B on the protrusion of the interconnection 3.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to wiring technology, and is particularly applicable to multilayer wiring technology that uses a coated insulating film as an interlayer insulating film between lower layer wiring and upper layer wiring. It is related to effective technology.

[Conventional technology]

Semiconductor integrated circuit devices are constructed with a so-called multilayer wiring structure in which multiple layers of wiring are stacked on a semiconductor substrate in order to prevent a decrease in the degree of integration due to wiring routing.

Each of the multiple layers of wiring is usually formed of aluminum alloy wiring, and these wirings mainly electrically connect semiconductor elements formed on the main surface of the semiconductor substrate.

Connection between the lower layer wiring and the upper layer wiring among the multiple layers is performed through a connection hole formed in an interlayer insulating film between them.

-4- The surface of the interlayer insulating film is planarized for the purpose of improving the step coverage of the upper layer wiring, as described in, for example, Japanese Patent Laid-Open No. 196555/1983. This interlayer insulating film is formed of a silicon oxide film having a three-layer structure. The silicon oxide film below the interlayer insulating film is deposited by plasma CVD. The silicon oxide film of the intermediate layer is 5OG (Spin On Glass).
s) applied by method.

After coating, the silicon oxide film coated by this SOG method is subjected to beta treatment to be inorganicized. Since the silicon oxide film coated by the SOG method has fluidity, it is coated with a thicker film thickness on the eye portions between the lower layer wirings than on the convex portions on the lower layer wirings, thereby reducing the step shape of the underlying layer.

The silicon oxide film coated by this SOG method is etched over the entire surface to remove the convex portions on the lower wiring. This removal involves removing SO
This is done to prevent the silicon oxide film coated by the G method from being exposed. The silicon oxide film on the upper layer of the interlayer insulating film is made of plasma C.
Deposited by VD method.

The surface of the interlayer insulating film having the three-layer structure configured in this way can be flattened by the silicon oxide film applied by the SOG method as the intermediate layer, so that the step coverage of the upper layer wiring can be improved. In addition, the glabella insulating film is S
Since the silicon oxide film coated by the OG method does not exist (it is not exposed in the contact hole), no side etching portion is generated in the contact hole. In other words, it is possible to reduce the step shape caused by the side etched portion in the connection hole and improve the step coverage of the upper layer wiring.

Etching the entire surface of the silicon oxide film coated by the SOG method, which is the intermediate layer of the interlayer insulating film, is described in, for example, Japanese Patent Laid-Open No. 61-28.
This is done by reactive ion etching (RIE) as described in Japanese Patent No. 5737.

Reactive ion etching uses an etching gas containing halogenated methane as a main component, such as a mixed etching gas of CHF3 and CF4. In addition, the entire surface etching is
For example, as described in Japanese Patent Publication No. 58-6306, sputter etching is used. Sputter etching is performed in an argon (Ar) gas and oxygen (02) gas atmosphere.

[The naked problem that the invention attempts to solve]

(1) A silicon oxide film coated by the SOG method is used as the intermediate layer of the interlayer insulating film used in the multilayer wiring structure of the semiconductor integrated circuit device described above. This silicon oxide film is made inorganic (vitrified) by the baking process after coating, and has a large internal stress, so it is easily broken (cracks are likely to occur). For this reason, it is not possible to increase the thickness of the silicon oxide film applied by the SOG method, and it is not possible to reduce the step shape of the concave portion between the lower layer wirings and to achieve sufficient planarization. This results in a problem of reduced coverage.

In addition, in order to sufficiently reduce the step shape of the concave portion between the lower wirings, it is necessary to apply the silicon oxide film multiple times using the SOG method and perform a baking process after each application to increase the total film thickness. Therefore, the number of steps for forming the interlayer insulating film increases, resulting in a problem that the manufacturing process of the semiconductor integrated circuit device becomes longer.

(2) The thickness of the silicon oxide film applied by the SOG method, which is the intermediate layer of the interlayer insulating film, depends on the shape of the underlying step, for example, the wiring width of the lower layer wiring. In other words, the silicon oxide film is applied to a thin film thickness on a flat portion on the lower wiring in a region where the wiring width is small. Further, the silicon oxide film is coated with a large thickness on a flat portion on the lower layer wiring in a region where the wiring width is large. The silicon oxide film coated by this SOG method is subjected to etching treatment over the entire surface, but during this treatment, etching remains in areas where the film is thick. Furthermore, in a region where the silicon oxide film is thin, a large amount of the silicon oxide film buried in the recessed portions between the lower wirings is removed due to overetching, resulting in deterioration in flatness. As described above, variations in the thickness of the silicon oxide film applied by the SOG method may cause variations in the processing of connection holes formed in the interlayer insulating film, resulting in poor conduction or damage to the underlying interlayer insulating film. A problem arises in that the step coverage of the upper layer wiring is reduced due to the deterioration of the flatness of the wiring.

(3) The entire surface of the silicon oxide film coated by the SOG method, which is the intermediate layer of the interlayer insulating film, is etched by reactive ion etching. Reactive ion etching is
Since an etching gas containing halogenated methane as a main component is used, carbon-based contaminants adhere to the surface of the silicon oxide film deposited by the SOG method. This carbon-based pollutant is SOG
A problem arises in that the quality of the silicon oxide film coated by the method deteriorates.

Further, this carbon-based contaminant causes a problem in that it tends to peel off between the silicon oxide film applied by the SOG method and the silicon oxide film deposited by the plasma CVD method.

In addition, since the carbon-based pollutants need to be removed,
A problem arises in that the manufacturing process of the semiconductor integrated circuit device becomes longer due to the step of removing this carbon-based contaminant.

Furthermore, when exposed to 02 plasma for the purpose of removing carbon-based contaminants, organic substances mixed with methyl groups can be formed as a silicon oxide film coated by the SOG method. When this organic silicon oxide film is used, the organic silicon oxide film becomes inorganic. Since these two phenomena occur simultaneously, a problem arises in that they cannot be controlled independently.

(4) When etching the entire surface of the silicon oxide film coated by the SOG method, which is the intermediate layer of the interlayer insulating film, no consideration is given to the etching conditions for the underlying silicon oxide film deposited by the plasma CVD method. For this reason, variations occur in the thickness of the interlayer insulating film on the lower wiring, and if the etching rate of the silicon oxide film applied by the SOG method is slower than that of the underlying silicon oxide film, the connection hole may not be conductive. A problem arises.

In addition, if the etching rate of the silicon oxide film coated with the SOG film is faster than that of the underlying silicon oxide film, the film thickness in the concave portion between the lower layer wirings becomes thinner and the surface flatness of the interlayer insulating film deteriorates. . This deterioration of flatness causes a problem of lowering the step coverage of the upper layer wiring.

(5) It is known that organic substances mixed with methyl groups are used as the silicon oxide film coated by the SOG method, which is the intermediate layer of the interlayer insulating film, as described in, for example, Japanese Patent Application Laid-open No. 164342/1983. It is being

In other words, since this silicon oxide film is not vitrified, it is difficult to break, and can be formed with a large thickness and planarized. After the coating and baking treatments are completed, this organic silicon oxide film is made inorganic by oxygen gas plasma treatment.

Therefore, the use of an organic silicon oxide film coated by the SOG method causes a problem in that the manufacturing process of the semiconductor integrated circuit device becomes longer due to the inorganic treatment.

An object of the present invention is to provide a technique that can improve the electrical reliability of upper layer wiring in a wiring member having a multilayer wiring structure.

Another object of the present invention is to provide a technique capable of planarizing the surface of the interlayer insulating film and improving the step coverage of upper layer wiring within the connection hole formed in the interlayer insulating film. There is a particular thing.

Another object of the present invention is to provide a technique that can reduce the number of manufacturing steps for the interlayer insulating film and shorten the manufacturing process for wiring members.

Another object of the present invention is to reduce the dependence of the film thickness of the silicon oxide film applied by the SOG method on the underlying step shape of the interlayer insulating film, prevent poor conduction between the lower layer wiring and the upper layer wiring, and thereby The object of the present invention is to provide a technique capable of improving the surface reliability of the glabellar insulating film as well as the flatness of the surface of the glabellar insulating film.

Another object of the present invention is to reduce carbon-based contaminants adhering to the surface of a wiring member having a multilayer wiring structure when etching the entire surface of a silicon oxide film coated by the SOG method for an insulating film between the eyebrows. An object of the present invention is to provide a technique capable of improving the film quality of a silicon film and preventing peeling of an interlayer insulating film.

Another object of the present invention is to reduce the number of manufacturing steps for improving the film quality of the silicon oxide film coated by the SOG method in the wiring member having the multilayer wiring structure, and to shorten the manufacturing process. The goal is to provide technology.

Another object of the present invention is to reduce variations in film thickness 11 2 when etching the entire surface of a silicon oxide film coated by the SOG method for an interlayer insulating film in a wiring member having a multilayer wiring structure. It is an object of the present invention to provide a technique that can improve electrical reliability by preventing poor conduction with upper layer wiring, and can also improve the flatness of the surface of the glabella insulating film.

Another object of the present invention is to reduce the number of manufacturing steps corresponding to mineralization treatment of an organic silicon oxide film coated by the SOG method of an interlayer insulating film in a wiring member having a multilayer wiring structure, and to reduce the manufacturing process of the wiring member. The goal is to provide technology that can shorten the time.

Another object of the present invention is to provide a technique that can improve the processing margin of connection holes that connect lower layer wiring and upper layer wiring, respectively, in a wiring member having a multilayer wiring structure.

Another object of the present invention is to provide a technique that can improve manufacturing yield in a wiring member having a multilayer wiring structure.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) Each of the lower layer wiring and the upper layer wiring is formed in an interlayer insulating film in which a deposited first insulating film, a coated second insulating film, and a deposited third insulating film are sequentially laminated. In the wiring member that is electrically connected through the coating type second
An insulating film is formed of an organic material, and this coating-type second insulating film is formed only on the recessed portions other than the white portion formed by the lower wiring on the deposited-type first insulating film. Each of the deposited first insulating film and the deposited third insulating film is a silicon oxide film deposited by plasma CVD, and the coating second insulating film is a silicon oxide film deposited by SOG.

(2) The wiring width of the lower layer wiring connected to the upper layer wiring through the connection hole in (1) above is formed to be 10 times or less the film thickness of the lower layer wiring.

(3) The second insulating film of the coating type of the interlayer insulating film of (1) or (2) is formed with a carbon content of 5 to 20 [wt%].

(4) Among the lower layer wirings to which the upper layer wirings are connected through the contact holes of (1) to (3) above, a dummy pedestal is formed under the lower layer wirings formed at a lower position than other lower layer wirings.

(5) Removal of the interlayer insulating film in (1) to (4) above on the lower wiring of the coated second insulating film is performed by sputter etching, and in this sputter etching, the coated second insulating film: the deposited type second insulating film is removed. The etching selectivity of the first insulating film is 1.4 to 2.0.
Do it with

(6) Removal of the underlying wiring of the second insulating film of the coating type interlayer insulating film in (1) to (5) above is carried out by reactive ion etching or sputter etching using an etching gas containing halogenated methane as a main component. Perform each section in turn.

(7) In the sputter etching described in (5) or (6) above, the mixing ratio of oxygen gas:argon gas is set to 0 to 1.

(8) The coated second insulating film of the interlayer insulating film of (5) to (7) is subjected to oxygen plasma treatment after the sputter etching.

(9) The second insulating film of the coating type of the interlayer insulating film in (5) to (8) above is subjected to vacuum vector treatment before sputter etching.

(10) After sputter etching the coated second insulating film of the interlayer insulating film of (1) to (9) above, a deposited third insulating film is formed on the surface of the coated second insulating film in the same vacuum system. Deposit an insulating film.

[For production]

According to the above-mentioned means (1), the coated second insulating film of the interlayer insulating film is not vitrified, internal stress can be reduced, and the thickness of the coated second insulating film can be reduced. Since the interlayer insulating film can be formed thickly without causing any damage, it is possible to planarize the surface of the interlayer insulating film and reduce the occurrence of disconnection and migration of the upper layer wiring. Since the second insulating film is not exposed, it is possible to prevent outgassing from the coated second insulating film and side etching of the coated second insulating film, and prevent the step of forming the upper layer wiring in the connection hole. Crab 5 16 You can improve your balance. As a result, the electrical reliability of the upper layer wiring of the wiring member can be improved.

According to the above-mentioned means (2), it is possible to reduce the dependence of the film thickness of the coated second insulating film of the interlayer insulating film on the underlying wiring pattern. The film thickness on the lower wiring can be made uniform. As a result, the coating-type second insulating film is reliably removed on the underlying wiring, the remaining coating-type second insulating film is reduced, and there is no etching residue), and the connection hole formed in the interlayer insulating film is removed. Since the coated type second insulating film is not exposed inside the coated type second insulating film, the coated type second insulating film is not exposed.
It is possible to prevent the occurrence of outgassing from the insulating film and side etching of the coated second insulating film, and further improve the step coverage of the upper layer wiring within the connection hole.

According to the above-mentioned means (3), it is possible to reduce cracks that occur in the coated second insulating film of the interlayer insulating film, and improve the controllability of the etching rate of the coated second insulating film. can do.

According to the above-mentioned means (4), the film thickness of the coated second insulating film of the interlayer insulating film on the lower layer wiring is made thinner than the film thickness of the other flat portion, and on which lower layer wiring. can also be made uniform.

As a result, it is possible to reliably remove the coated second insulating film on the underlying wiring, reduce the amount of the coated second insulating film remaining, and remove the coated second insulating film from the contact hole formed in the interlayer insulating film. Since the second insulating film is not exposed, degassing from the coated second insulating film and side etching of the coated second insulating film are prevented, and step coverage of the upper layer wiring within the connection hole is prevented. can be further improved.

According to the above-mentioned means (5), since the controllability of the total film thickness of the deposited first insulating film and the coating-type second insulating film can be improved (reduced variations), the interlayer It is possible to reliably process the contact hole formed in the insulating film, reduce conduction defects within the contact hole, and improve electrical reliability. Since the amount of etching of the recessed portion between the lower layer wirings can be reduced and the surface of the interlayer insulating film can be planarized, occurrence of disconnection and migration of the upper layer wiring can be reduced.

According to the above-mentioned means (6), carbon-based contaminants attached to the surface of the coating-type second insulating film by the reactive ion etching can be removed by sputter etching. The film quality of the insulating film can be improved.

According to the above-mentioned means (7), while sputter etching the second insulating film of the coating type, the second insulating film of the coating type is sputter etched.
The insulating film can be mineralized. As a result, the coating-type second layer is formed in the contact hole formed in the interlayer insulating film.
Even if the insulating film remains and is exposed, there is no generation of moisture or outgassing, so corrosion of the upper layer wiring can be prevented or step coverage within the connection hole of the upper layer wiring can be improved. .

Furthermore, since the mineralization treatment is performed by the sputter etching, the manufacturing process of the wiring member can be shortened by the amount equivalent to the mineralization treatment.

According to the above-mentioned means (8), the second II! of the coating mold!
After sputter etching the fourth edge film, this coated second insulating film can be mineralized by oxygen plasma treatment. As a result, even if the coated second insulating film remains and is exposed in the connection hole formed in the interlayer insulating film, no moisture or outgassing occurs, thereby preventing corrosion of the upper layer wiring. Alternatively, the step coverage of upper layer wiring can be improved.

According to the above-mentioned means (9), moisture can be removed from the coated second insulating film by vacuum baling before sputter etching, thereby improving the control of the amount of etching in sputter etching. . As a result, it is possible to reliably remove the underlying wiring of the second coating type insulating film of the interlayer M edge film.

According to the above-mentioned means (10), the deposition type third insulating film can be deposited before moisture or gas is adsorbed on the surface newly exposed by the sputter etching of the coating type second insulating film. Therefore, deterioration of the film quality of the second insulating film of the coating 90- type can be prevented.

The structure of the present invention will be described below along with an example in which the present invention is applied to a multilayer wiring structure of a semiconductor integrated circuit device (gate array) described in Japanese Patent Application No. 1-63037 previously filed by the applicant. explain.

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

(Example I) A method for manufacturing a multilayer wiring structure of a semiconductor integrated circuit device, which is Example I of the present invention, will be explained using FIGS. 1 to 8 (cross-sectional views of main parts shown for each manufacturing process). .

The multilayer wiring structure of a semiconductor integrated circuit device is formed as follows.

First, a base insulating film 2 is formed on the main surface of a semiconductor substrate 1,
As shown in FIG. 1, a first layer wiring (lower layer wiring) 3 is formed on this base insulating film 2.

Although the semiconductor integrated circuit device of this embodiment is not limited to this, it is constructed of a logic LSI that employs a gate array method. The basic cells forming the logic circuit of this semiconductor integrated circuit device are mainly composed of bipolar transistors. This semiconductor integrated circuit device can obtain various logical functions by changing the wiring pattern connecting semiconductor elements in the basic cells and the wiring pattern connecting basic cells (between logic circuits). The specific structure of the semiconductor integrated circuit device used in this embodiment is described in Japanese Patent Application No. 1-63037, as mentioned above, and therefore the description thereof will be omitted here.

The semiconductor substrate 1 is made of single crystal silicon, and a semiconductor element such as a bipolar transistor constituting the basic cell is formed on the main surface of the active region of the semiconductor substrate 1. The base insulating film 2 electrically isolates the semiconductor element and the first layer wiring 3, and is formed mainly of, for example, a silicon oxide film.

The first layer wiring 3 is mainly used as a connection between semiconductor devices in a basic cell and a connection between basic cells. The first layer wiring 3 is formed of aluminum or aluminum alloy deposited by sputtering, for example. Aluminum alloys are formed by adding Cu or Cu and Si to aluminum. Cu has the effect of increasing migration resistance. Si has the effect of increasing alloy spike resistance strength. The first layer wiring 3 has a different size depending on whether it is a signal wiring or a power supply wiring, but for example, in the case of a signal wiring connecting between basic cells, a film thickness of 0.8 to 1.2 [μm] and a thickness of 2.0 μm are used. It is formed with a wiring width of 0 to 4.0 [μm].

Next, as shown in FIG. 2, a lower insulating film 4A of the interlayer insulating film (4) is formed over the entire surface of the substrate including on the first layer wiring 3. This insulating film 4A is formed of a silicon oxide film deposited by a plasma CVD method, and has a thickness of, for example, about 600 [nm].

Next, as shown in FIG. 3, an insulating film 4B, which is an intermediate layer of the glabellar insulating film (4), is formed on the entire surface of the substrate on the insulating film 4A. This insulating film 4B is formed of a silicon oxide film coated by the SOG method. This silicon oxide film is an organic material mixed with methyl groups.

This silicon oxide film coated by the SOG method has a thickness of about 100 [n
It is formed with a thin film thickness of about 300 [nm] in the concave portions (flat portions) between the first layer wirings 3. The thickness of the insulating film 4B is controlled by adjusting the rotational speed and coating chemicals during coating of the silicon oxide film.

Next, as shown in FIG. 4, an etching process (etchback process) is performed on the entire surface of the substrate to remove the insulating film 4B from the convex portions on the first layer wiring 3. Then, as shown in FIG.

The insulating film 4B is removed, for example, by sputter etching using a single-wafer type magnetron etching device. This sputter etching is carried out using, for example, Ar gas: 70 [sc
cm, pressure H3Q [mtorr], magnetic field: 80 [G
s], RF power: 350 [W (13,56
[MHz]). Sputter etching performed under these conditions increases the etching rate of the insulating film 4B by 8
The etching rate of the edge film 4A can be set to 50 nm/m/min. That is, in the sputter etching, the insulating film 4B:
The etching selectivity of the insulating film 4A can be controlled to about 1.7. Since this sputter etching is over-etching, not only the insulating film 4B is removed, but also the underlying insulating film 4A is slightly etched away. Same 4th
As shown in the figure, the entire surface etching by sputter etching removes the insulating film 4B in the convex portions on the first layer wiring 3, and leaves the insulating film 4B in the concave portions between the first layer wirings 3. The surface can be made flat.

Next, as shown in FIG. 5, an interlayer insulating film (4
) is formed as an upper layer of an insulating film 4c. The insulating film 4C is
Like the lower insulating film 4A, it is formed of a silicon oxide film deposited by the plasma CVD method, and has a thickness of, for example, about 600 [nm]. By this step of forming the insulating film 4C, the insulating films 4A, 4B, and 4C are sequentially laminated.
The glabella insulating film 4 having a layered structure is completed. The surface of this interlayer insulating film 4 is flattened because an insulating film 4B is formed as an intermediate layer by applying the SOG method and etching the entire surface by sputter etching.

Next, as shown in FIG. 6, on the surface of the interlayer insulating film 4,
An etching mask 5 having an opening above the first layer wiring 3 is formed. This etching mask 5 is formed, for example, from a photoresist film formed by photolithography technology.

Next, using the etching mask 5, the interlayer insulating film 4 exposed through the opening of the etching mask 5 is removed,
As shown in FIG. 7, connection holes 6 are formed in this glabellar insulating film 4. As shown in FIG. For example, the connection hole 6 is formed by wet-etching mainly the upper insulating film 4C of the interlayer insulating film 4 using hydrochloric acid to form a negative part. The purpose of this wet etching is to reduce the level difference in the connection hole 6. After this, CHF3+02 or C
Reactive ion etching (RIE) using Freon gas of F4+CHF3 is performed to remove the remaining portion of the connection hole 6. The purpose of this reactive ion etching is to reduce the opening area of the connection hole 6.

In the formation region of this contact hole 6, an interlayer insulating film 4 is formed of a lower insulating film 4A and an upper insulating film 4C, and the inner wall of the contact hole 6 has an interlayer #! ! The insulating film 4B, which is the intermediate layer of the edge film 4, is not exposed. In other words, the insulating film 4 which is the intermediate layer of the interlayer insulating film 4
Insulating film 4B at the time of generation of degassing from B and formation of connection hole 6
The occurrence of side etching can be prevented. As a result, the selection range of etching conditions when forming the connection hole 6 is expanded, so that the connection hole 6 can be easily processed. Also,
The selection range of etching conditions when forming the connection hole 6 is expanded, and the etching mask 5 is used to remove deposits that adhere to the inner wall of the connection hole 6 when the surface of the first layer wiring 3 is sputter etched by over-etching. Can be removed at times. Further, since the insulating film 4B is not exposed on the inner wall of the connection hole 6, alteration and deterioration of the film quality of the insulating film 4B during removal (peeling) of the etching mask 5 can be prevented.

Next, the etching mask 5 is removed. Then, so as to connect to the first layer wiring 3 through the connection hole 6,
A second layer wiring 7 is formed on the interlayer insulating film 4. The second layer wiring 7 is formed of, for example, aluminum or an aluminum alloy, similarly to the first layer wiring 3. The first layer wiring 3 is formed as a signal wiring, a power main line, etc. that connects the basic cells (logic circuits).

Since the surface of the interlayer insulating film 4 in the second layer wiring 7 is flattened, the step coverage can be improved. Further, in the second layer wiring 7, the insulating film 4B, which is the intermediate layer of the interlayer insulating film 4, is not exposed on the inner wall of the connection hole 6, and the insulating film 4B is not exposed on the inner wall of the connection hole 6.
Since there is no moisture or outgassing from the etching process or side etching of the insulating film 4B, step coverage can be improved.

In this way, (1) each of the first layer wiring 3 and the second layer wiring 7 is formed by sequentially laminating the deposited insulating film 4A, the coated insulating film 4B, and the deposited insulating film 4C. In a semiconductor integrated circuit device that is electrically connected through a connection hole 6 formed in an interlayer insulating film 4, the coating type insulating film 4B is formed of an organic material, and the coating type insulating film 4B is It is formed only in the concave portions other than the convex portions formed by the first layer wiring 3 on the deposited insulating film 4A. With this configuration, the interlayer insulating film 4
The coating-type insulating film 4B is not vitrified and can reduce internal stress, and the coating-type insulating film 4B can be formed thickly without causing cracks. Planarization can be achieved, step coverage of the second layer wiring 7 can be improved, occurrence of disconnection and migration of the second layer wiring 7 can be reduced, and connection holes 6 formed in the interlayer insulating film 4 can be Because the coated insulating film 4B is not exposed on the inner wall of the.

It is possible to prevent the occurrence of outgassing from the coated insulating film 4B and side etching of the coated insulating film 4B, and to improve the step coverage of the second layer wiring 7 on the inner wall of the connection hole 6. can. As a result, the electrical reliability of the second layer wiring 7 of the semiconductor integrated circuit device can be improved.

(Example ■) The present Example ■ is a method of the present invention in which the controllability of the film thickness of the insulating film 4B, which is the intermediate layer of the interlayer insulating film, is improved in the multilayer wiring structure of the semiconductor integrated circuit device of the above-mentioned Example I. This is a second example.

In the process shown in FIG. 3 of the above-described embodiment (2), the thickness of the insulating film 4B, which is the intermediate layer of the interlayer insulating film 4, changes depending on the wiring width of the first layer wiring 3. As a result of the examination, it became clear. FIG. 9 shows a cross section of a multilayer wiring structure of a test semiconductor integrated circuit device in which the wiring width of the first layer wiring 3 is changed. Further, FIG. 10 shows the correlation between the wiring width of the first layer wiring 3 and the film thickness of the insulating film 4B.

As shown in FIG. 9, when the surface of the insulating film 4B is coated using the SOG method so that the surface is smooth, the wiring width increases from the first layer wiring 3A, which has a small wiring width, to the first layer wiring 3F, which has a large wiring width. , the insulating film 4B on the first layer wiring 3 is gradually coated thickly. The film thickness of the insulating film 4B at the convex portions on each of the first layer wirings 3A to 3F is normalized by the film thickness of the concave portions between the first layer wirings 3 of the insulating film 4B. As shown in the figure,
A correlation occurs with the shape of the underlying step (thickness of the first layer wiring 3). In FIG. 10, each of t1 to t3 represents the film thickness of the first layer wiring 3, and tl is 0.5 [p m ]
, t2 is 1.0 [μm1. ta is 2.0 [μm].

When performing the step shown in FIG. 4 of Example I, that is, etching the entire surface of the insulating film 4B, in order to avoid leaving the insulating film 4B on the convex portion on the first layer wiring 3 in the region where the connection hole 6 is formed. For this purpose, it is effective to perform etching on the entire surface of the insulating film 4B to a thickness corresponding to the film thickness applied to the recessed portions between the first layer wirings 3, or to control the film thickness of the insulating film 4B. In the former case, the amount of etching on the entire surface of the insulating film 4B is large, and the first
The step shape of the layer wiring 3 becomes larger. Therefore, the latter method of controlling the thickness of the insulating film 4B is effective, and as shown in FIG. can do. For example, the film thickness of the first layer wiring 3 is l.

In the case of O [μm], the wiring width of the first layer wiring 3 is set to 10 [μm] or less, which is about 10 times or less. Similarly, if the film thickness of the first layer wiring 3 is 0.5 [μm], the first layer wiring 3
When the thickness of the first layer wiring 3 is 2.0 [μm], the wiring width of the first layer wiring 3 is set to 20 [μm] or less, which is 10 times or less. μm] or less. In other words, by setting the wiring width of the first layer wiring 3 to 10 times or less the film thickness, a region where the film thickness of the insulating film 4B hardly depends on the underlying level difference is used, as shown in FIG. Therefore, the controllability of the amount of etching of the insulating film 4B can be improved, and the insulating film 4B on the first layer wiring 3 can be reliably removed.

In this way, (2) the wiring width of the first layer wiring 3 connected to the second layer wiring 7 through the connection hole 6 is formed to be 10 times or less the film thickness of the first layer wiring 3; With this configuration, the first thickness of the coated insulating film 4B of the interlayer insulating film 4 is
Since the pattern dependence of the layer wiring 3 can be reduced, the film thickness of the coating type insulating film 4B on the first layer wiring 3 can be made uniform. As a result, the coating-type insulating film 4B is reliably removed on the first layer wiring 3 (31-2), the remaining coating-type insulating film 4B is reduced, and there is no etching residue), and the interlayer insulating film 4 is removed. Since the coated insulating film 4B is no longer exposed on the inner wall of the connection hole 6 formed in the contact hole 6, degassing from the coated insulating film 4B and side etching of the coated insulating film 4B are prevented. The step coverage of the second layer wiring 7 on the inner wall of the connection hole 6 can be further improved.

(Example ■) This Example (■) is a book that improves the etching controllability of the entire surface etching process of the insulating film 4B, which is the intermediate layer of the interlayer insulating film, in the multilayer wiring structure of the semiconductor integrated circuit device of the above-mentioned Example I. This is a third embodiment of the invention.

In the step shown in FIG. 4 of Example I, when etching the entire surface of the insulating film 4B, which is the intermediate layer of the interlayer insulating film 4, due to variations in the etching selectivity of the insulating film 4B and the underlying insulating film 4A. As a result of studies conducted by the present inventors, it has become clear that the variation in the film thickness of the interlayer insulating film 4 changes significantly.

FIG. 11 shows an enlarged cross section of a main part of a multilayer wiring structure of a semiconductor integrated circuit device. Further, Table 1 listed at the end of the specification shows the degree of variation in the film thickness of the interlayer insulating film 4 based on the etching selectivity.

As shown in FIG. 11 and Table 1, first, the interlayer insulating film 4
The film thickness of the lower layer insulating film 4A is set to 600±60 [nm], and the film thickness of the convex portion on the first layer wiring 3 of the intermediate layer insulating film 4B is set to 100±30 [nm]. In this case, the total thickness of the insulating films 4A and 4B of the interlayer insulating film 4 is 700±
67 [nm] (600+100±v'Tma+30). As shown in FIG. 4 of Embodiment I, the entire surface of the insulating film 4B is etched (sputter etching) to ensure that the convex portions of the insulating film 4B on the first layer wiring 3 are removed. Since it is necessary to over-etch by ±30 [nm], it is sufficient to set the entire surface etching process with an etching amount of 150±15 [nm]. In other words,
Since the thickness of the insulating film 4B is 130 [nm] at maximum,
The entire surface etching process may be performed with a minimum etching amount of 135 [nm], taking into account the amount of overetching.

In the entire surface etching process at this time, the insulating films 4A, 4
By appropriately setting the etching selectivity of each of B, the thickness of the insulating film 4A after the entire surface of the insulating film 4B is etched can be controlled.

In the above example, in order to simplify the calculation, the insulating film 4A
The film thickness was 600 [nml], and the total etching amount was 150 [nml].
Fixed at nml. The total thickness of the insulating films 4A and 4B is calculated as shown in Table 1. That is, when the etching selectivity ratio of the insulating film 4B:insulating film 4A is set to 1.0, the total film thickness is 550±30 nm (film thickness variation ±5.5%). Etching selection ratio
1.4, the total film thickness is 564.5±21.5
[nm (amount of variation in film thickness ±3.8%)].

When the etching selection ratio is 1.8, the total film thickness is 5
72.5±16.5 [nml (film thickness variation ±2.
9 [%ko]. That is, as the etching selectivity is increased (the etching speed difference is increased), the amount of etching of the insulating film 4A during the entire surface etching process of the insulating film 4B is reduced, and the amount of variation in the total film thickness of the insulating films 4A and 4B is reduced. becomes smaller. In other words, this reduction in the amount of variation can improve the processing margin when forming the connection hole 6 in the interlayer insulating film 4.

On the other hand, if the etching selectivity mentioned above is increased too much, the amount of etching of the insulating film 4B becomes large, so that the first layer wiring 3
In the concave portion between the two, the thickness of the insulating film 4B becomes thinner, and the flatness of the surface of the interlayer insulating film 4 deteriorates. In particular, when aluminum or aluminum alloy is used as the second layer wiring 7 and patterning is performed by photolithography, the concave portions on the surface of the interlayer insulating film 4 (between the first layer wiring 3)
The etching mask becomes thinner due to the diffraction phenomenon, and the wiring width of the second layer wiring 7 becomes thinner partially. When the wiring width of the second layer wiring 7 becomes narrower, electromigration is more likely to occur and there is a higher possibility of disconnection, so the etching selection ratio mentioned above is set to be appropriately high.

FIG. 12 shows the relationship between the etching selection ratio and the failure rate. As shown in FIG. 12, when the etching selectivity ratio of the insulating film 4B:insulating film 4A of the interlayer insulating film 4 is less than 1.4 (region A), there is a large variation in the total thickness of the insulating films 4A and 4B. In particular, since the insulating film 4B cannot be removed reliably in the concave portion above the first layer wiring 3, the incidence of defects such as poor penetration of the connection hole 6 formed in the interlayer insulating film 4 increases.

Furthermore, when the etching selection ratio of the insulation film 4B:insulation film 4A of the glabella insulation film 4 exceeds 2.0 (region B), the insulation film 4
Since the amount of B etched increases and the surface flatness of the interlayer insulating film 4 deteriorates, the incidence of defects such as electromigration and disconnection of the second layer wiring 7 increases. That is, the etching selection ratio is 1.4 or more and 2.
If it is set to 0 or less, the above-mentioned defects will hardly occur.

In this way, (5) the coating-type insulating film 4B of the interlayer insulating film 4 on the first layer wiring 3 is removed by sputter etching, and the coating-type insulating film 4B of the sputter etching:
The etching selectivity of the deposited insulating film 4A is 1.4 or more 2
．． Perform within the range of 0 or less.

With this configuration, it is possible to improve controllability (reduce variations) in the total thickness of the deposited insulating film 4A and the coated insulating film 4B.
It is possible to reliably process the connection hole 6 formed in the
It is possible to reduce conduction defects in the connection hole 6 and improve electrical reliability, and also to
Since it is possible to reduce the amount of etching of the recessed portions between the layer wirings 3 and to planarize the surface of the interlayer insulating film 4, occurrence of disconnection and migration of the second layer wirings 7 can be reduced.

(Example ■) This example (■) is an example of the present invention in which the etching rate of the insulating film 4B, which is the intermediate layer of the interlayer insulating film 4, is stabilized in the multilayer wiring structure of the semiconductor integrated circuit device of the above-mentioned Example I. This is a fourth example.

In the step shown in FIG. 4 of Example I, the etching rate of the insulating film 4B, which is the intermediate layer of the interlayer insulating film 4, is greatly changed depending on the surface condition of the insulating film 4B. This was clarified as a result of a review by 8 people.

Figure 14 shows two types of processing methods in block diagrams.
FIG. 3 shows the etching rate of the insulating film 4B obtained by each of the above processing methods.

Processing method B shown in FIG. 14 involves applying an insulating film 4B on the surface of a semiconductor integrated circuit device (semiconductor wafer) by the SOG method, performing a baking process, and then etching the entire surface of the insulating film 4B. This is method <3>. The insulating film 4B is made of an organic material as in Example I. The baking process is performed, for example, by N2 annealing at 450 [° C.]. The semiconductor integrated circuit device that has been subjected to the baking process <1> is cooled in N2 gas, and then left in a storage room that has been purged with N2. In other words, the insulating film 4B is blocked from absorbing moisture as much as possible.

In the processing method A shown in FIG. 14, an insulating film 4B is applied on the surface of the semiconductor integrated circuit device by the SOG method, and after performing a baking process 1> and a vacuum baking process 2>, the insulating film 4B is This is method <3> in which the entire surface of the film 4B is etched. Vacuum baking treatment <2> is, for example, 400 [℃], 10
0 [mtorr] for 5 minutes. At this time, the process can be accelerated by flowing about 1O[5CCIIl of N2 gas, and the process time can be shortened. This treatment method A includes at least vacuum baking treatment <2
> to the entire surface etching treatment <3> are processed without breaking the vacuum (in the same vacuum system without exposure to the atmosphere).

In the processing method B, as shown in FIG.
In the entire surface etching process, the etching speed differs between the early stage and the latter stage, and the transition time of the etching speed also differs.

On the other hand, processing method A can reduce phenomena such as changes in etching rate that occur in processing method B, as shown in FIG. 13, by performing the vacuum baking process <2>. In other words, processing method A can improve the controllability of the etching amount in the entire surface etching process compared to processing method B.

According to the results of mass spectrometry of the degassed gas during the vacuum baking process <2> conducted by the present inventor, most of it was water, and when examining the change in the mass 9-0 of the semiconductor wafer before and after the vacuum baking process, e.g. It has been revealed that in the case of a diameter of 5 [1 nch], the amount reaches approximately 7 [mg/wafer].

That is, the insulating film 4B, which is the intermediate layer of the interlayer insulating film 4, is
After the coating/baking process <1>, vacuum baking process <2> is performed, and the entire surface etching process <3> is applied to the insulating film 4B in the same vacuum system. Controllability can be improved.

In this way, (9) before the entire surface etching (sputter etching) process <3>, the coated insulating film 4B of the interlayer insulating film 4 is subjected to the vacuum baking process <2>. With this configuration, moisture can be removed from the coating-type insulating film 4B by vacuum baking process 2> before sputter etching, and the controllability of the etching amount in sputter etching can be improved.

As a result, the coating-type insulating film 4B of the interlayer insulating film 4 on the first layer wiring 3 can be reliably removed.

Further, in the entire surface etching process <3> of the processing method A described above, an insulating film 4C is deposited on the insulating film 4B in the same vacuum system to complete the interlayer insulating film 4.

In other words, the insulating film 4 subjected to the vacuum baking process <2>
B is a state in which moisture has been removed, and the insulating film 4 in this state is
Even if a new surface of the insulating film 4B is exposed by performing etching process <1> on the entire surface of B, the new surface of the insulating film 4B can be covered with the insulating film 4C without adsorbing moisture or gas.

In this way, after (10) etching the entire surface of the coated insulating film 4B of the interlayer insulating film 4 (3), a deposited insulating film 4C is etched on the surface of the coated insulating film 4B in the same vacuum system. Deposit. With this configuration, the deposition type insulating film 4C can be deposited before moisture or gas is adsorbed on the surface newly exposed by sputter etching of the applied type insulating film 4B. Deterioration of the film quality of 4B can be prevented.

(Example ■) This example (■) is a book that improves the yield in the entire surface etching process of the insulating film 4B, which is the intermediate layer of the interlayer insulating film 4, in the multilayer wiring structure of the semiconductor integrated circuit device of Example I. This is a fifth embodiment of the invention.

In the step shown in FIG. 4 of the above embodiment (2), an etching gas containing halogenated methane as a main component, for example, C
Reactive ion etching using HF, +CF, and other gases is used. This reactive ion etching can deposit a carbon-based polymer (carbon-based contaminant) on the surface of the insulating film 4B, and can control the etching rate of the insulating film 4B.

The carbon-based polymer may cause cracks in the insulating film 4C deposited on the upper layer of the insulating film 4B, deteriorating the crack withstand voltage of the interlayer insulating film 4, or cause the insulating film 4B to crack when forming the connection hole 6.
Bleeding occurs at the interface between the film and the insulating film 4C, and defects such as side etching occur at this interface during wet etching.

Normally, the carbon-based polymer is removed by 02 plasma associative treatment after the reactive ion etching is completed, but this treatment mineralizes the insulating film 4B formed of organic matter, and this mineralization causes the volume of the insulating film 4B to shrink. , cracks occur in the insulating film 4B.

Further, when the carbon-based polymer is removed by various chemical solutions such as a photoresist film stripping solution or by washing with water, the chemical solution and moisture are adsorbed onto the surface of the insulating film 4B, which is an organic substance, and the upper insulating film 4B
Defects such as film radiation fogging and cracks occur during or after the formation of C.

According to the results of basic research conducted by the present inventors, by cleaning the surface of the insulating film 4B by thin sputter etching, the carbon-based polymer can be easily removed without causing the above-mentioned defects. The conditions for this sputter etching may be substantially the same as those for the sputter etching used in the step shown in FIG. 4 of the first embodiment described above.

In this way, (6) the coating-type insulating film 4B of the interlayer insulating film 4 is removed on the first layer wiring 3 by reactive ion etching or sputter etching using an etching gas containing halogenated methane as a main component. Perform each one in sequence.

With this configuration, the carbon-based polymer attached to the surface of the coating-type insulating film 4B by the reactive ion etching can be removed by etching the insulating film 4B.
The film quality of B can be improved. In addition, since sputter etching can be performed in the same chamber as reactive ion etching, there is no need for a new step to remove the carbon-based polymer, resulting in a shortened manufacturing process.

(Example ■) The present Example ■ reduces the crack occurrence rate of the insulating film 4B, which is the intermediate layer of the interlayer insulating film, in the multilayer wiring structure of the semiconductor integrated circuit device of the above-mentioned Example I. This is a sixth embodiment of the present invention in which flattening is achieved.

In the semiconductor integrated circuit device of Example I described above, the quality of the insulating film 4B, which is the intermediate layer of the interlayer insulating film 4, changes depending on the carbon content. FIG. 15 shows the relationship between the carbon content [wt%] in the insulating film 4B and the failure rate. As a result of failure analysis conducted by the present inventor, the carbon content in the insulating film 4B was found to be 5[
% by weight) (region C), cracks occur frequently at the step portion of the base.

If cracks occur in the insulating film 4B, the flatness of the insulating film 4B after the entire surface etching is extremely deteriorated, and in particular, the step coverage of the second layer wiring 7 and the processing accuracy are reduced.

Furthermore, if the carbon content in the insulating film 4B exceeds 20 [wt%] (region D), it becomes difficult to control the etching selectivity when etching the entire surface of the insulating film 4B. It is not possible to level out the situation.

In other words, the carbon content in the insulating film 4B of the interlayer insulating film 4 is 5
The optimum range was obtained to be 20% by weight.

In this way, (3) the coating type insulating film 4B of the interlayer insulating film 4 is formed with a carbon content of 5 to 20 [wt%]. With this configuration, the coating type insulating film 4B of the interlayer insulating film 4
In addition, it is possible to reduce cracks occurring in the etching process, improve the controllability of the etching rate of the coating type insulating film 4B, and make the interlayer insulating film 4 planar.

(Example ■) The present Example ■ improves etching controllability during the entire surface etching process of the insulating film 4B, which is the intermediate layer of the interlayer insulating film 4, in the multilayer wiring structure of the semiconductor integrated circuit device of the above-mentioned Example I. This is a seventh embodiment of the present invention in which the step coverage of the second layer wiring 7 in the contact hole 6 formed in the interlayer insulating film 4 is improved.

As a result of the basic research conducted by the present inventor, it has been found that when increasing the amount of 02 gas added based on Ar gas during sputter etching during the entire surface etching process of the insulating film 4B, which is the intermediate layer of the interlayer insulating film 4, Since the etching speed becomes faster, the etching selectivity ratio of insulating film 4B=insulating film 4A can be improved. In other words, the etching selection ratio of the entire surface etching process of Example 2 can be easily controlled.

Furthermore, when the amount of 02 gas added during sputter etching of the insulating film 4B is increased, the surface portion of the insulating film 4B can be made inorganic. In other words, even if the convex portion of the insulating film 4B on the first layer wiring 3 is not completely removed by the entire surface etching process and the insulating film 4B is exposed on the inner wall of the connection hole 6 formed in the interlayer insulating film 4, Since the insulating film 4B is inorganic, outgassing and the like are eliminated. However, if the mixing ratio of 02 gas:Ar gas in sputter etching becomes 1 or more, mineralization progresses unnecessarily, so that the volumetric shrinkage of the insulating film 4B becomes large and cracks occur frequently in the insulating film 4B. Therefore, the mixing ratio of the sputter etching is set to 0-1 or less.

Furthermore, in order to inorganicize the surface portion of the insulating film 4B, the same effect as described above can be obtained by controlling the etching of the entire surface of the insulating film 4B and performing a short-time 02 sputter etching treatment or 02 plasma treatment (non-bias). can play. The above-mentioned short time varies depending on the device and various conditions, but
In the single-wafer type magnetron sputter etching apparatus used by the present inventor, for example, 02 gas: 30 [
sccm], pressure crab 30 [mtorr], magnetic field: 70
In the case of the respective conditions of [Gsco] and RF small power of 250 [W], the time is about 10 seconds to 3 minutes. Further, in the case of plasma treatment, the short time varies depending on the plasma density and distribution, and is approximately 1 to 10 minutes.

7 48- Thus, (7) sputter etching at the etching rate of the entire surface of the insulating film 4B is carried out at a mixing ratio of 02 gas:Ar gas of 0 to 0. With this configuration, the coating-type insulating film 4B can be mineralized while sputter etching the coating-type insulating film 4B. As a result, even if the coated insulating film 4B remains and is exposed on the inner wall of the contact hole 6 formed in the interlayer insulating film 4, no moisture or outgassing occurs, so the second layer wiring 7 can be prevented from corrosion, or the connection hole 6 of the second layer wiring 7 can be prevented.
Step coverage within the range can be improved.

Furthermore, since the mineralization process can be performed by sputter etching of the entire surface etching process, the manufacturing process of the semiconductor integrated circuit device can be shortened by the amount equivalent to the mineralization process.

(8) The coated insulating film 4B of the interlayer insulating film 4 is subjected to oxygen plasma treatment after the sputter etching. With this configuration, after the sputter etching of the coating type insulating film 4B, the coating type insulating film 4B is etched.
B can be made inorganic by oxygen plasma treatment. As a result, the same effects as described above can be achieved.

(Example 2) Example 2 is an eighth example of the present invention in which the present invention is applied to a multilayer wiring structure having three or more layer wiring structures.

A multilayer wiring structure of a semiconductor integrated circuit device according to Embodiment 2 of the present invention is shown in FIG. 16 (cross-sectional view of main parts).

As shown in FIG. 16, although not shown, an interlayer insulating film 8 is provided on the second layer wiring 7 to isolate it from the third layer wiring. The interlayer insulating film 8 has a structure similar to that of the interlayer insulating film 4 described in each of the above-mentioned Examples I to (2). In other words, the interlayer insulating film 8 has a three-layer structure in which an insulating film 8A deposited by plasma CVD, an insulating film 8B coated by SOG, and an insulating film not shown deposited by plasma CVD are sequentially laminated. be done.

Since the second layer wiring 7 shown in FIG. 16 is arranged on the recessed portion between the first layer wiring 3, the surface of the interlayer insulating film 4 underlying the second layer wiring 7 is located above the recessed portion. However, in this embodiment, a dummy pedestal (DP) 3 is arranged, and the surface of the interlayer insulating film 4 underlying the second layer wiring 7 is flattened. The dummy pedestal 3 is formed in the recessed portion between the first layer interconnects 3 using the same conductive layer as the first layer interconnects 3. This pedestal 3 is placed in the white portion on the second layer wiring 7 for the purpose of thinning the thickness of the insulating film 8B, which is the intermediate layer of the interlayer insulating film 4. If the dummy pedestal 3 is not disposed, the insulating film 8B is coated with a thicker film thickness than other areas, which may cause etching residue in the entire surface etching process, or may cause contact holes to be formed in the interlayer insulating film 8 to be processed. becomes difficult.

Note that the dummy pedestal 3 is not limited to the same conductive layer as the first layer wiring 3, but as described in Japanese Patent Application No. 1-63037 previously filed by the applicant of the present application, It may be formed of an insulating film.

In this way, (4) among the second layer interconnects 7 to which the 3Mth interconnect is connected through the connection hole, other second layer interconnects 7
A dummy pedestal 3 is formed below the second layer wiring 7, which is formed at a lower position than the second layer wiring 7.

With this configuration, the coating type insulating film 8 of the interlayer insulating film 8
The film thickness on the second layer wiring 7 of B can be made thinner than the film thickness on the other flat portions, and can be made uniform over any second layer wiring 7.

As a result, it is possible to reliably remove the coated insulating film 8B on the second layer wiring 7, to reduce the amount of the coated insulating film 8B remaining, and to remove the coated insulating film 8B from the contact hole formed in the interlayer insulating film 8. Since the coated insulating film 8B is not exposed, outgassing from the coated insulating film 8B and #! ! Side etching of the edge film 8B can be prevented, and the step coverage of the third layer wiring within the connection hole can be further improved.

(Example ■) This Example ■ is the ninth example of the present invention in which the present invention is applied to a multilayer wiring structure in which a transition metal film is selectively embedded in contact holes formed in an interlayer insulating film. .

A multilayer wiring structure of a semiconductor integrated circuit device according to Embodiment 2 of the present invention is shown in FIG. 17 (a cross-sectional view of main parts).

1-52 As shown in FIG. be included. This transition metal film 9
is a tungsten film deposited by selective CVD using, for example, SiH4 or a mixed gas of H2 gas and WF6 gas as a source gas.

This tungsten film is selectively deposited only on the upper part of the first layer wiring 3 inside the contact hole 6 formed in the interlayer insulating film 4. In this transition metal film 9, since the insulating film 4B is not exposed on the inner wall of the connection hole 6, poor selectivity due to degassing from the insulating film 4B can be prevented.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the present invention is not limited to multilayer wiring structures of semiconductor integrated circuit devices, but can be applied to multilayer wiring structures of wiring members such as printed wiring boards.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a wiring member having a multilayer wiring structure, electrical reliability of upper layer wiring can be improved.

In the wiring member having the multilayer wiring structure, it is possible to planarize the surface of the interlayer insulating film and improve step coverage of the upper layer wiring within the connection hole formed in the interlayer insulating film.

In the wiring member having the multilayer wiring structure, the number of manufacturing steps of the interlayer insulating film can be reduced, and the manufacturing process of the wiring member can be shortened.

In the wiring member having the multilayer wiring structure, the dependence of the thickness of the silicon oxide film applied by the SOG method on the interlayer insulating film on the shape of the underlying step is reduced, and poor conduction between the lower layer wiring and the upper layer wiring is prevented. It is possible to improve the electrical reliability and the flatness of the surface of the interlayer insulating film.

In the wiring member having the multilayer wiring structure, when the silicon oxide film coated by the SOG method of the interlayer insulation film is etched over the entire surface, carbon-based polymer adhering to the surface is reduced and peeling of the interlayer insulation film is prevented, The film quality of the silicon oxide film can be improved.

In the wiring member having the multilayer wiring structure, the SO
The number of manufacturing steps for improving the film quality of the silicon oxide film coated by the G method can be reduced, and the manufacturing process can be shortened.

In the wiring member having the multilayer wiring structure, it is possible to reduce the variation in the film thickness during the entire surface etching treatment of the silicon oxide film applied by the SOG method of the interlayer insulating film, and to prevent poor conduction between the lower layer wiring and the upper layer wiring. It is possible to improve the electrical reliability and the flatness of the surface of the interlayer insulating film.

In the wiring member having the multilayer wiring structure, the number of manufacturing steps corresponding to the inorganic treatment of the organic silicon oxide film coated by the SOG method of the interlayer insulating film can be reduced, and the manufacturing process of the wiring member can be shortened.

In the wiring member having the multilayer wiring structure, it is possible to improve the processing margin of the connection hole connecting each of the lower layer wiring and the upper layer wiring.

In the wiring member having the multilayer wiring structure, manufacturing yield can be improved.

[Table 1 1

[Brief explanation of drawings]

1 to 8 are cross-sectional views of essential parts showing each manufacturing process of a multilayer wiring structure of a semiconductor integrated circuit device which is Embodiment I of the present invention, and FIG. 9 is Embodiment II of the present invention. FIG. 10 is a cross-sectional view of a main part of a multilayer wiring structure of a semiconductor integrated circuit device, and FIG. 10 is a correlation diagram between wiring width and film thickness of the multilayer wiring structure. FIG. 12 is an enlarged cross-sectional view of a main part of a multilayer wiring structure of an integrated circuit device, and FIG. FIG. 14 is a block diagram showing the etching method for the multilayer wiring structure of a semiconductor integrated circuit device according to Example 2. FIG. 15 is an example of the present invention. 16 is a diagram showing the relationship between the carbon content in the interlayer insulating film and the defective rate in the multilayer wiring structure of a semiconductor integrated circuit device according to (1). FIG. FIG. 17 is a cross-sectional view of a main part of a multilayer wiring structure of a semiconductor integrated circuit device according to embodiment (2) of the present invention. In the figure, 1... Semiconductor substrate, 3... First layer wiring, 4゜8... Interlayer insulating film, 4A, 4C, 8A... Deposited type insulating film, 4B, 8B... Coated type Insulating film, 6... connection hole,
7. Second layer wiring.

Claims (11)

[Claims] 1. Each of the lower layer wiring and the upper layer wiring is electrically connected through a connection hole formed in an interlayer insulating film formed by sequentially laminating a deposited first insulating film, a coated second insulating film, and a deposited third insulating film. In the wiring member connected to the coating type second
The insulating film is formed of an organic material, and the coating type second insulating film is formed only on the concave portions other than the convex portions formed by the lower wiring on the deposited first insulating film. wiring member. 2. Each of the deposited first insulating film and the deposited third insulating film is a silicon oxide film deposited by a plasma CVD method,
2. The wiring member according to claim 1, wherein the coated second insulating film is a silicon oxide film coated by an SOG method. 3. 3. The wiring member according to claim 1, wherein the wiring width of the lower layer wiring connected to the upper layer wiring through the connection hole is 10 times or less the film thickness of the lower layer wiring. 4. The coating type second insulating film of the interlayer insulating film has a thickness of 5 to 2
The wiring member according to claim 2 or 3, characterized in that it is formed with a carbon content of 0 [wt%]. 5. A dummy pedestal is formed below the lower layer wiring that is formed at a lower position than other lower layer wirings among the lower layer wirings to which the upper layer wirings are connected through the connection holes. 4. Each wiring member described in 4. 6. The coating-type second insulating film of the interlayer insulating film is removed on the lower wiring by sputter etching, and the etching selectivity of the coated-type second insulating film:deposited-type first insulating film during the sputter etching is set to 1. 6. The method of forming each wiring member according to claim 2, wherein the method is performed at a temperature of .4 to 2.0. 7. Removal of the coated second insulating film of the interlayer insulating film on the underlying wiring is performed by sequentially performing reactive ion etching using an etching gas containing halogenated methane as a main component and sputter etching. The method of forming each wiring member according to claim 2 to claim 6. 8. 7. The sputter etching for removing the coating-type second insulating film of the interlayer insulating film on the lower interconnection layer is performed at a mixing ratio of oxygen gas:argon gas of 0 to 1. A method for forming a wiring member according to. 9. 9. The method of forming each wiring member according to claim 6, wherein the coated second insulating film of the interlayer insulating film is subjected to oxygen plasma treatment after the sputter etching. . 10. 10. Formation of a wiring member according to claim 6, wherein the coated second insulating film of the interlayer insulating film is subjected to a vacuum baking process in the same vacuum system as the second insulating film before sputter etching. Method. 11. A claim characterized in that, after the sputter etching of the coated second insulating film of the interlayer insulating film, a deposition type third insulating film is deposited on the surface of the coated second insulating film in the same vacuum system. A method of forming each wiring member according to claim 1 to claim 10.