JPH0372637A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce the leakage current of a gate electrode so as to increase the breakdown strength of the gate electrode by providing the third semiconductor layer having an electron affinity which is smaller than that of the first semiconductor layer between the gate electrode and first semiconductor layer only at the section under the gate electrode. CONSTITUTION:The first semiconductor layer (channel layer) 1 and second semiconductor layer 2 are respectively constituted of undoped GaAs and n- GaAlAs, with the thickness and n-type impurity concentration of the layers 1 and 2 being made similar to those of conventional ones. An AlGaAs barrier layer 3 which is used as a barrier to electrons is provided between a gate electrode 6 and the channel layer 1 only at the section under a gate electrode section where a leakage current becomes an issue. Since no effect can be expected when the layer 3 is too thin in thickness and the distance between the electrode 6 and channel becomes longer and such element characteristics as transmission conductance, etc., deteriorate when the layer 3 is too thick, it is preferable to set the thickness of the layer 3 at about several tens of nm.

Description

[Detailed description of the invention] [Summary] Inverted HEMT (formerly gh ElectroMobi
With regard to semiconductor device configurations that utilize heterojunctions such as LityTraasistorl, the first semiconductor layer that becomes the channel layer is intended to improve device performance by reducing leakage current of the gate electrode and increasing gate breakdown voltage. (1> and has a smaller electron affinity on the substrate side than the first semiconductor layer,
In a semiconductor device including a transistor using a heterojunction made of an n-type doped second semiconductor layer (2), a semiconductor layer is formed between the electrode and the first semiconductor layer only under the gate electrode (6). A third semiconductor layer (3) having a smaller electron affinity than the first semiconductor layer (1>) is provided.

[Industrial Field of Application] The present invention relates to a semiconductor device having a heterojunction transistor such as an inverted HEMT, and a method for manufacturing the same.

HEMTs and various compound semiconductor devices are attracting attention as ultra-high-speed devices, but in order to maximize the performance of these devices, improvements in the characteristics of ohmic electrodes, gate electrodes, etc. are required.

[Prior Art] Figure 4 shows a cross-sectional structure of a conventional inverted HEMT, in which 11 is a semi-insulating GaAs substrate, 12 is an undoped GaAs substrate, and 12 is an undoped GaAs substrate.
As layer (buffer layer), 13 is undoped A#GaAs
layer (spacer layer), 2 is N-AJGaAs (electron supply layer), and 14 is attached to increase electron mobility.In the conventional inverted HEMT structure, the entire portion from the ohmic electrode to the channel is formed of GaAg. A on the way to be there
A better ohmic contact can be obtained compared to a normal HEMT in which a #GaAs electron supply layer exists.

[Problem to be solved by the invention] By the way, in the conventional inverted HEMT, the area under the gate electrode is n.
Since it is made of -GaAs contact layer 4, there is nothing to act as an electron barrier other than the Schottky barrier formed on the surface, and the gate breakdown voltage is determined only by the Schottky breakdown voltage of n-GaAs contact layer 4. Here, the contact layer 4 is n-type and is usually doped to about 1 x 1018 cm"-3, so the surface depletion layer accompanying the Schottky barrier is as thin as about 30 nm, and the gate breakdown voltage is low, making it difficult to form an integrated circuit. This is a major barrier to stable operation of the device.

The present invention is directed to a semiconductor device and an undoped semiconductor device for the purpose of overcoming the problem of low gate breakdown voltage, which is a problem of inverted HEMTs, and improving device performance.
GaAs layer (spacer layer), l is undoped GaAs layer (channel layer), 4 is n-GaAs layer (contact layer)
5 is a source electrode, 6 is a gate electrode, and 7 is a drain electrode.

Figure 5 shows the energy band structure diagram of Figure 3, where EC is the conduction band and EF is the Fermi level, formed on the GaAs layer (channel layer) 1 side of the two-dimensional electron gas (2DEC) or hetero interface. The illustration shows what will happen.

As is well known, its operating principle is based on the N-A#GaAs layer 2
Electrons supplied from the donor inside move to the GaAs layer 1 and generate a two-dimensional electron gas on the GaAs layer 1 side of the hetero interface, and the flow of the 2DEG is controlled by the gate voltage to perform transistor operation. It is.

Moreover, FIG. 6 shows the band structure of the lower part of the source electrode of a conventional normal HEMT, where 1 is a GaAs layer (channel layer), 2 is an N-AJ GaAs layer (electron supply layer), and 4 is an N-
The GaAs layer (contact layer) 6 is a source electrode.

A manufacturing method is provided.

[Means for Solving the Problems] The gist of the present invention is to provide a third semiconductor layer that serves as a barrier to electrons only under the gate electrode, between the channel and the contact layer.

That is, in the semiconductor device according to the present invention, a first semiconductor layer serving as a channel layer and a second semiconductor layer which has an electron affinity smaller than that of the first semiconductor layer and which is doped to be n-type are formed closer to the substrate than the first semiconductor layer.
In a semiconductor device including a transistor using a heterojunction made of semiconductor layers, a third semiconductor layer having a lower electron affinity than the first semiconductor layer is provided between the electrode and the first semiconductor layer only under the gate electrode. It is characterized by having the following.

Further, the method according to the present invention includes growing a second semiconductor layer and a first semiconductor layer on a semiconductor substrate, and then growing a third semiconductor layer having a smaller electron affinity than the first semiconductor layer, The third semiconductor layer is removed so that the third semiconductor layer remains only in the portion below the gate electrode, and a contact layer is formed on the surfaces of the remaining third semiconductor layer and the first semiconductor layer. , characterized in that the contact layer is provided with an electrode.

FIG. 1 shows an example of a device structure to satisfy the configuration described above, in which the first semiconductor layer (channel layer) 1 is made of undoped GaAs, and the first semiconductor layer (channel layer) 1 is made of undoped GaAs, and The semiconductor layer 2 of No. 2 is made of a-GaA or As and has the same thickness and the same 0 type impurity concentration as the conventional one.

A barrier layer 3 made of ^#GaAs, which serves as a barrier to electrons, is provided between the gate electrode 6 and the channel layer l only under the gate electrode portion where leakage current is a problem.

If the barrier layer 3 is too thin, it will not be effective, while if it is too thick, the distance between the gate electrode and the channel will become long and device characteristics such as transfer conductance will deteriorate, so the thickness is preferably several tens of nanometers.

[Function] FIG. 2 shows the band structure (a) under the gate electrode and the band structure under the source electrode of the device shown in FIG. 1. Figure 2 is the first
The energy band structure diagram in the figure is shown as (a) of the gate electrode,
(b) below the source electrode. As is clear from a comparison between FIG. 2a and FIG. 5, the presence of an AJGaAs barrier layer under the gate can reduce the gate leakage current of the device since it forms a barrier against electrons. In other words, the breakdown voltage of the gate electrode can be increased. Further, the contact layer does not have a barrier layer, and a good ohmic contact can be formed.

Next, to explain the method of forming the barrier layer 3 (AIGaAs layer) which is the third semiconductor layer only under the gate electrode according to the present invention, as a crystal growth method, for example, molecular beam crystal growth (MBE) method is used. A buffer layer (GaAs layer) 12 with a thickness of 0.2 μm and an undoped AJGa layer is formed on the substrate 11 used.
The As layer (spacer layer) 13 is 0.21. t, m, Si-doped N-AJGaAs layer (electron supply layer impurity concentration 1×1
018cm-3)2 to 15nm, undoped AJGaA
S layer (spacer layer) 14 is 2 nm, undoped GaAs
(b) shows a layer (channel layer) 1 with a thickness of 15 nm.The band structure under the source electrode is similar to that of a conventional inverted HEMT, and the two-dimensional electron gas forming the channel and the contact layer There is no barrier to electrons between the channels and a good ohmic contact can be formed.On the other hand, since an AlGaAs barrier layer 3 is inserted between the channel and the contact under the gate electrode, it acts as a barrier to electrons and prevents them from flowing from the channel. Flow to the gate electrode or vice versa can be blocked.

Therefore, gate leakage current is reduced and gate breakdown voltage is increased. As a result, the performance of the device also improves.

[Examples] Hereinafter, the present invention will be described in detail by way of examples with reference to the drawings. FIG. 1 is a sectional view of an inverted HEMT according to the present invention. 11 is a semi-insulating GaAs substrate, 12 is a buffer layer, 13 is a spacer, 2 is an electron supply layer, 14 is a spacer layer, 1 is a channel layer, 3 is a barrier layer, 4 is a contact layer, 5 is a source electrode, 6 is a Gate electrode, 7 is the drain electrode and undoped A#GaAs (barrier layer) 3 is 2
0 nm and an undoped GaAs layer 15 of 10 nm are epitaxially grown (FIG. 3(a)).

Ga ions (17) are implanted into the epitaxially grown wafer using a focused ion beam (FIB) device only in the portion that will become the gate of the device (see Figure 3).
b)〉. The implantation conditions are an accelerating voltage of 50 keV and a dose of about 5×10 12 cm 2 , and the implantation amount is small. When this wafer is etched in a halogen-based gas while being irradiated with light, the etching rate is slow only in the implanted area, and the other areas are etched quickly. The etching rate ratio of GaAs is about 1:3 to 1:5 between the implanted part and other parts, so in a situation where the GaAs cap layer 15 in the implanted part that will become the gate is almost etched, the other parts including the contact layer are etched. The AlGaAs barrier layer 3 is etched and removed (
Figure 3 (C〉〉).

Note that the barrier layer can also be selectively etched without providing the GaAs cap layer 15.

On the wafer processed in this way, Si-doped n-G
AAs (contact layer) 4 is regrown to a thickness of 30 nm. It is desirable that the process up to this point be carried out consistently in a high vacuum in order to suppress the generation of interface states at the regrown interface.

Thereafter, element isolation is performed by mesa etching, and as shown in FIG. 1, a source electrode 5 and a drain electrode 7 are formed, and finally a gate electrode 6 is formed.

This device uses a high gate voltage (conventional structure inverted H
The relative increase with respect to EMT is 0.3 V in the forward direction and about IV in the reverse direction), and a good ohmic contact cannot be formed and the contact resistivity is 1 x 10-6.
Ωcm or less>, excellent device characteristics can be obtained.

[Effects of the Invention] As is clear from the description of the embodiments above, according to the present invention, a high gate voltage can be applied because a barrier layer is provided between the channel layer and the gate electrode layer under the gate electrode. can get. Furthermore, since there is no barrier layer under the ohmic electrode, a good contact with low contact resistance can be formed, and a device with improved performance can therefore be obtained.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an inverted HEMT according to the present invention, FIG. 2 is a band diagram under the gate electrode (a), a band diagram under the source electrode (b), and FIG. 3 (a>, (b
), (c) are methods for forming the barrier layer below the gate, Figure 4 is a cross-sectional view of a conventional GaAs layer N-A#GaAs inverted type HEMT, Figure 5 is its energy band diagram, and Figure 6 is a conventional FIG. 2 is an energy band diagram of a type of HEMT. 1-Undoped GaAs layer (channel layer, first semiconductor layer), 2-N-A! GaAs (electron supply layer, second
semiconductor layer>, 3-third semiconductor layer <barrier layer>, 4
- n-GaAs layer (contact layer), 5 - source electrode 1 electrode, 6 - gate electrode, 7 - drain electrode, 11 semi-insulating GaAs substrate, 12 - undoped GaAs layer (buffer layer), 13 - undoped A# GaAs layer (spacer layer)
, 14-undoped^#GaAs layer (spacer layer), E
C-conduction band, EF-Fermi level, 2DEG two-dimensional electron gas 2

Claims (1)

[Claims] 1. A first semiconductor layer (1) serving as a channel layer, and a second semiconductor layer (1) which has a lower electron affinity than the first semiconductor layer and is doped to be n-type on the substrate side. In a semiconductor device including a transistor using a heterojunction made of a semiconductor layer (2), the electrode and the first electrode are formed only under the gate electrode (6).
A semiconductor device comprising a third semiconductor layer (3) having a lower electron affinity than the first semiconductor layer (1) between the semiconductor layer and the first semiconductor layer (1). 2. From the first semiconductor layer (1), which becomes a channel layer, and the second semiconductor layer (2), which has a smaller electron affinity than the first semiconductor layer and is doped to the n-type, closer to the substrate than the first semiconductor layer (1). In a method for manufacturing a semiconductor device including a transistor using a heterojunction, a second semiconductor layer (2) and a first semiconductor layer (1) are grown on a semiconductor substrate, and then,
A third semiconductor layer (3) having a lower electron affinity than the first semiconductor layer is grown, and the third semiconductor layer (3) is grown so that the third semiconductor layer (3) remains only in the portion below the gate electrode.
and forming a contact layer (4) on the surfaces of the remaining third semiconductor layer (3) and the first semiconductor layer (1),
A method for manufacturing a semiconductor device, comprising providing electrodes (5, 6, 7) on the contact layer (4).