JPH0371660A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0371660A
JPH0371660A JP1209307A JP20930789A JPH0371660A JP H0371660 A JPH0371660 A JP H0371660A JP 1209307 A JP1209307 A JP 1209307A JP 20930789 A JP20930789 A JP 20930789A JP H0371660 A JPH0371660 A JP H0371660A
Authority
JP
Japan
Prior art keywords
bonding wire
pad
lead
semiconductor device
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1209307A
Other languages
Japanese (ja)
Inventor
Kenji Toyosawa
健司 豊沢
Fushinobu Wakamoto
若本　節信
Takamichi Maeda
前田　崇道
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP1209307A priority Critical patent/JPH0371660A/en
Publication of JPH0371660A publication Critical patent/JPH0371660A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent a bonding wire from deforming due to pressure at the time of injecting sealing resin even if it is a semiconductor device of multi-pin structure by a method wherein at least a connection part between a pad and the bonding wire is reinforced with reinforcing resin, and then parts other than an outer lead are sealed up. CONSTITUTION:A semiconductor chip 10 is wire-bonded to a die pad 32, and a bonding wire 20 such as a gold wire or the like is connected between the pad 11 of the semiconductor chip 10 and an inner lead 312 of a lead section 31. Then, reinforcing resin 50 is made to drip on the whole face of the semiconductor chip 10 to cover the connection part of the bonding wire 20 with the pad 11 to reinforce. Then, a part other than an outer lead 311 or the semiconductor chip 10, the bonding wire 20, and the inner lead 312 are sealed up with a sealing resin 40. By this setup, even if it is a semiconductor device of multi-pin structure, the deformation of the bonding wire due to pressure at the time of injecting the sealing resin is prevented in parts covered with reinforcing resin.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、半導体チップとリードフレームとがボンディ
ングワイヤで接続された半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor device in which a semiconductor chip and a lead frame are connected by bonding wires.

〈従来の技術〉 従来のこの種の半導体装置について第４図及び第５図を
参照しつつ説明する。<Prior Art> A conventional semiconductor device of this type will be described with reference to FIGS. 4 and 5.

この種の半導体装置は、半導体チップ１０と、リードフ
レーム３０と、半導体チップＩＯのパッド１１とリード
フレーム３０のインナリード３１２　とを接続するボン
ディングワイヤ２０と、リードフレーム３０のアウタリ
ード３１１以外の部分、すなわち半導体チップ１０、ボ
ンディングワイヤ２０及びインナリード３１２を封止す
る封止用樹脂４０とから構成されている。This type of semiconductor device includes a semiconductor chip 10, a lead frame 30, a bonding wire 20 connecting the pad 11 of the semiconductor chip IO and an inner lead 312 of the lead frame 30, a portion of the lead frame 30 other than the outer lead 311, That is, it is composed of the semiconductor chip 10, the bonding wires 20, and the sealing resin 40 that seals the inner leads 312.

リードフレーム３０は、半導体チップ１０がダイボンデ
ィングされるダイパッド３２と、リード部３１とからな
り、リード部３１の先端は図示しない基板の配線パター
ンに接続されるアウタリード３１１、後端はインナリー
ド３１２となっている。このようなリードフレーム３０
は、エツチング加工によって形成される。The lead frame 30 consists of a die pad 32 to which the semiconductor chip 10 is die-bonded, and a lead part 31. The leading end of the lead part 31 is an outer lead 311 connected to a wiring pattern of a substrate (not shown), and the rear end is an inner lead 312. It has become. Such a lead frame 30
is formed by etching.

半導体チップ１０は、前記ダイパッド３２にダイボンデ
ィングされ、半導体チップ１０のパッド１１とインナリ
ード３１２とがボンディングワイヤ２０によって接続さ
れる。そして、アウタリード３１１以外の部分が封止用
樹脂４０によって封止されて半導体装置が形成される。The semiconductor chip 10 is die-bonded to the die pad 32, and the pad 11 of the semiconductor chip 10 and the inner lead 312 are connected by the bonding wire 20. Then, parts other than the outer leads 311 are sealed with the sealing resin 40 to form a semiconductor device.

〈発明が解決しようとする課題〉 しかしながら、上述した従来の半導体装置には以下のよ
うな問題点がある。<Problems to be Solved by the Invention> However, the conventional semiconductor device described above has the following problems.

すなわち、リード部３１の数が多いいわゆる多ビン構造
の半導体装置では、リードフレーム３０のインナリード
３１２とダイパッド３２との間の距離を短く設定するこ
とが困難になっている。これは、エツチング加工技術の
限界に起因している。That is, in a semiconductor device having a so-called multi-bin structure having a large number of lead portions 31, it is difficult to set the distance between the inner lead 312 of the lead frame 30 and the die pad 32 short. This is due to the limitations of etching technology.

例えば、１００ビン以上の半導体装置では、パッド１１
とインナリード３１２との距離が３．５１１Ｉｎ以上に
なるので、ボンディングワイヤ２０はリード部３１の数
が少ない半導体装置より長いものを使用しなければなら
ない。かかるボンディングワイヤ２０は、封止用樹脂４
０の封止時に流れ込む封止用樹脂４０の圧力のため、ワ
イヤ流れ（封止用樹脂４０の注入時の圧力によるボンデ
ィングワイヤ２０の変形をいう）が発生しやすい。かか
るワイヤ流れは、第５図に示す半導体チップ１０−ボン
ディングワイヤ２０（第５図のＡ部参照）、ボンディン
グワイヤ２０ボンデイングワイヤ２０（第５図のＢ部参
照）、インナリード３１２−ボンディングワイヤ２０　
（第５図のＣ部参照）の如き短絡不良の発生原因となる
。For example, in a semiconductor device with 100 bins or more, pad 11
Since the distance between the lead portion 312 and the inner lead 312 is 3.511 In or more, the bonding wire 20 must be longer than that of a semiconductor device having fewer lead portions 31. The bonding wire 20 is bonded to the sealing resin 4.
Due to the pressure of the sealing resin 40 flowing during the sealing process, wire flow (referring to deformation of the bonding wire 20 due to the pressure when the sealing resin 40 is injected) is likely to occur. Such wire flow is as shown in FIG. 5: semiconductor chip 10 - bonding wire 20 (see section A in FIG. 5), bonding wire 20 - bonding wire 20 (see section B in FIG. 5), inner lead 312 - bonding wire 20
(See section C in FIG. 5).

本発明は上記事情に鑑みて創案されたもので、多ビン構
造の半導体装置であってもボンディングワイヤのワイヤ
流れが発生しない半導体装置を提供することを目的とし
ている。The present invention was devised in view of the above circumstances, and an object of the present invention is to provide a semiconductor device in which bonding wire does not flow even in a semiconductor device having a multi-bin structure.

〈課題を解決するための手段〉 本発明に係る半導体装置は、リードフレームのダイパッ
ドにダイボンディングされた半導体チップのパッドと、
リードフレームのリード部のインナリードとがボンディ
ングワイヤで接続され、リード部のアウタリード以外の
部分が封止樹脂で刺止されてなる半導体装置であって、
少なくとも前記パッドとボンディングワイヤとの接続部
分が補強用樹脂で覆われている。<Means for Solving the Problems> A semiconductor device according to the present invention includes a pad of a semiconductor chip die-bonded to a die pad of a lead frame;
A semiconductor device in which an inner lead of a lead part of a lead frame is connected with a bonding wire, and a part of the lead part other than the outer lead is sealed with a sealing resin,
At least the connection portion between the pad and the bonding wire is covered with reinforcing resin.

く作用〉 補強用樹脂で少なくともボンディングワイヤとパッドと
の接続部分を覆う。補強用樹脂で覆われた部分は、ワイ
ヤ流れが発生しない。Effect> Cover at least the connection portion between the bonding wire and the pad with reinforcing resin. Wire drift does not occur in the portion covered with reinforcing resin.

〈実施例〉 以下、図面を参照して本発明に係る一実施例を説明する
。<Example> Hereinafter, an example according to the present invention will be described with reference to the drawings.

第１図は本発明の一実施例に係る半導体装置の概略的断
面図、第２図及び第３図は他の実施例に係る半導体装置
の概略的断面図である。なお、従来のものと略同−の部
品等には同一の符号を付して説明を行う。FIG. 1 is a schematic cross-sectional view of a semiconductor device according to one embodiment of the present invention, and FIGS. 2 and 3 are schematic cross-sectional views of semiconductor devices according to other embodiments. Note that parts and the like that are substantially the same as those of the conventional one will be described with the same reference numerals.

本実施例に係る半導体装置は、リードフレーム３０のダ
イパッド３２にダイボンディングされた半導体チップ１
０のバッド１１と、リードフレーム３０のリード部３１
のインナリード３１２とがボンディングワイヤ２０で接
続され、リード部３１のアウタリード３１１以外の部分
が封止用樹脂４０で封止されている。The semiconductor device according to this embodiment includes a semiconductor chip 1 die-bonded to a die pad 32 of a lead frame 30.
0's pad 11 and the lead part 31 of the lead frame 30
are connected to the inner leads 312 by the bonding wires 20, and the portions of the lead portions 31 other than the outer leads 311 are sealed with a sealing resin 40.

まず、第１図を参照しつつ本発明の一実施例に係る半導
体装置の製造工程について説明する。First, a manufacturing process of a semiconductor device according to an embodiment of the present invention will be described with reference to FIG.

まず、半導体チップＩＯをグイバッド３２にダイボンデ
ィングし、当該半導体チップ１０のバッド１１とリード
部３１のインナリード３１２との間を金線等のボンディ
ングワイヤ２０で接続する。First, the semiconductor chip IO is die-bonded to the guide pad 32, and the pad 11 of the semiconductor chip 10 and the inner lead 312 of the lead portion 31 are connected using bonding wires 20 such as gold wires.

次に、補強用樹脂５０を半導体チップ１０の上全面に滴
下して、ボンディングワイヤ２０とパッドＨとの接続部
分を覆って補強する。前記補強用樹脂５０は、エポキシ
系樹脂を加熱して液状にしたものであって、滴下後に熱
硬化させる。また、固形の補強用樹脂５０を少なくとも
ボンディングワイヤ２０とバッド１１との接続部分に載
せ、熱溶解、熱硬化させることによって両者を覆っても
よい。Next, a reinforcing resin 50 is dropped onto the entire surface of the semiconductor chip 10 to cover and reinforce the connecting portion between the bonding wire 20 and the pad H. The reinforcing resin 50 is made of an epoxy resin heated to a liquid state, and is thermally cured after being dropped. Alternatively, the solid reinforcing resin 50 may be placed on at least the connection portion between the bonding wire 20 and the pad 11, and may be thermally melted and thermally cured to cover both.

この後に、アウタリード３１１以外の部分、すなわち半
導体チップ１０、ボンディングワイヤ２０及びインナリ
ード３１２を封止用樹脂４０でもって封止する。この封
止用樹脂４０は、例えばエポキシ系樹脂であって、封止
された半導体チップ１０等を外部の雰囲気から保護する
役割を果たす。After this, parts other than the outer leads 311, that is, the semiconductor chip 10, the bonding wires 20, and the inner leads 312 are sealed with the sealing resin 40. This sealing resin 40 is, for example, an epoxy resin, and serves to protect the sealed semiconductor chip 10 and the like from the external atmosphere.

第２図に示す実施例では、補強用樹脂５０が半導体チッ
プ１０の上全面のみならず、ダイパッド３２にも滴下さ
れている。In the embodiment shown in FIG. 2, the reinforcing resin 50 is dripped not only on the entire upper surface of the semiconductor chip 10 but also on the die pad 32.

次に、ボンディングワイヤ２０の全体が補強用樹脂５０
で覆われた半導体装置について第３図を参照しつつ説明
する。Next, the entire bonding wire 20 is covered with reinforcing resin 50.
A semiconductor device covered with a wafer will be described with reference to FIG.

かかる半導体装置では、リード部３１とダイパッド３２
との間の隙間から補強用樹脂５０が流れ落ちないように
、リード部３１とダイパッド３２との間の隙間に例えば
ポリイミド等からなるフィルム６０を貼付しておく。In such a semiconductor device, the lead portion 31 and the die pad 32
A film 60 made of, for example, polyimide is attached to the gap between the lead part 31 and the die pad 32 to prevent the reinforcing resin 50 from flowing down from the gap between the leads 31 and the die pad 32.

なお、半導体チップＩＯのダイパッド３２へのダイボン
ディング、ボンディングワイヤ２０によるパッド１１と
インナリード３１２との接続或いは封止用樹脂４０によ
る封止は上述した実施例と同様なので説明は省略する。Note that the die bonding of the semiconductor chip IO to the die pad 32, the connection between the pad 11 and the inner lead 312 using the bonding wire 20, and the sealing with the sealing resin 40 are the same as those in the above-mentioned embodiment, so the explanation will be omitted.

なお、第１図及び第２図に示した実施例においては、補
強用樹脂５０は半導体チップ１０或いはダイパッド３２
から流れ落ちない適宜量だけ滴下するものとする。Note that in the embodiment shown in FIGS. 1 and 2, the reinforcing resin 50 is applied to the semiconductor chip 10 or the die pad 32.
The appropriate amount should be dripped so that it does not run off.

〈発明の効果〉 本発明に係る半導体装置は、補強用樹脂で少なくともパ
ッドとボンディングワイヤとの接続部分が補強された後
に、アウタリード以外の部分を封止用樹脂で封止して構
成されているので、封止用樹脂を注入する際の圧力によ
るワイヤ流れは発生しない、従って、多ピン構造の半導
体装置であっても短絡不良がない信頼性の高い半導体装
置とすることができる。具体的には２００ピン以上の半
導体装置であっても短絡不良が発生しない。<Effects of the Invention> The semiconductor device according to the present invention is constructed by reinforcing at least the connection portion between the pad and the bonding wire with a reinforcing resin, and then sealing the portion other than the outer lead with a sealing resin. Therefore, no wire flow occurs due to the pressure when the sealing resin is injected. Therefore, even if the semiconductor device has a multi-pin structure, it can be a highly reliable semiconductor device free from short-circuit defects. Specifically, short-circuit failures do not occur even in semiconductor devices with 200 pins or more.

すなわち、第１図或いは第２図に示す半導体装置による
と、ボンディングワイヤとパッドとの接続部分が補強用
樹脂で覆われるので、少なくとも第５図のＡ部に示す半
導体チップ−ボンディングワイヤの短絡が発生しない。That is, according to the semiconductor device shown in FIG. 1 or 2, the connecting portion between the bonding wire and the pad is covered with reinforcing resin, so that at least the short circuit between the semiconductor chip and the bonding wire shown in part A of FIG. 5 is prevented. Does not occur.

また、第３図に示す半導体装置によると、第５図に示す
Ａ部のみならず、Ｂ部、Ｃ部に示すボンディングワイヤ
ーボンディングワイヤ、ボンディングワイヤーインナリ
ードの短絡不良が発生しない。Further, according to the semiconductor device shown in FIG. 3, short-circuit failures do not occur in the bonding wire bonding wire and the bonding wire inner lead shown in not only the A section shown in FIG. 5 but also the B section and C section.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例に係る半導体装置の概略的断
面図、第２図及び第３図は他の実施例に係る半導体装置
の概略的断面図、第４図は従来の半導体装置の概略的断
面図、第５図は従来の半導体装置の問題点を示す模式的
斜視図である。 １０・・・半導体チップ、１１・・・パッド、２０・・
ボンディングワイヤ、３０・・・リードフレーム、３１
・・・リード部、３１１　　・・・アウタリード、３１
２　　・　・　・インナリード、３２・　・　・ダイパ
ッド、４０・・・封止用樹脂、５０・・・補強用樹脂。FIG. 1 is a schematic cross-sectional view of a semiconductor device according to one embodiment of the present invention, FIGS. 2 and 3 are schematic cross-sectional views of semiconductor devices according to other embodiments, and FIG. 4 is a conventional semiconductor device. FIG. 5 is a schematic perspective view showing problems with the conventional semiconductor device. 10... Semiconductor chip, 11... Pad, 20...
Bonding wire, 30...Lead frame, 31
...Lead part, 311 ...Outer lead, 31
2 . . . Inner lead, 32 . . . Die pad, 40 . . . Sealing resin, 50 . . . Reinforcing resin.

Claims (1)

【特許請求の範囲】[Claims] （１）リードフレームのダイパッドにダイボンディング
された半導体チップのパッドと、リードフレームのリー
ド部のインナリードとがボンディングワイヤで接続され
、リード部のアウタリード以外の部分が封止用樹脂で封
止されてなる半導体装置において、少なくとも前記パッ
ドとボンディングワイヤとの接続部分が補強用樹脂で覆
われていることを特徴とする半導体装置。(1) The pad of the semiconductor chip die-bonded to the die pad of the lead frame and the inner lead of the lead part of the lead frame are connected with a bonding wire, and the parts of the lead part other than the outer leads are sealed with a sealing resin. 1. A semiconductor device characterized in that at least a connection portion between the pad and the bonding wire is covered with a reinforcing resin.
JP1209307A 1989-08-10 1989-08-10 Semiconductor device Pending JPH0371660A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1209307A JPH0371660A (en) 1989-08-10 1989-08-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1209307A JPH0371660A (en) 1989-08-10 1989-08-10 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0371660A true JPH0371660A (en) 1991-03-27

Family

ID=16570790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1209307A Pending JPH0371660A (en) 1989-08-10 1989-08-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0371660A (en)

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