JPH0371571U - - Google Patents
Info
- Publication number
- JPH0371571U JPH0371571U JP13251789U JP13251789U JPH0371571U JP H0371571 U JPH0371571 U JP H0371571U JP 13251789 U JP13251789 U JP 13251789U JP 13251789 U JP13251789 U JP 13251789U JP H0371571 U JPH0371571 U JP H0371571U
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wiring pattern
- multilayer board
- chip
- pattern provided
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims 1
- 239000011093 chipboard Substances 0.000 description 1
Landscapes
- Multi-Conductor Connections (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
第1図、第3図は本考案の一実施例を示す斜視
図、第2図は本考案により得たチツプ基板を印刷
配線基板に装着した場合の一部切欠斜視図、第4
図、第5図は従来の配線パターンが交差する場合
に行なう手段の一実施例を示した一部切欠斜視図
である。
3,3′……電極部、4……外層配線パターン
、5……内層配線パターン、6……スルーホール
、9……チツプ形配線部品。
Figures 1 and 3 are perspective views showing one embodiment of the present invention, Figure 2 is a partially cutaway perspective view of the chip board obtained according to the present invention mounted on a printed wiring board, and Figure 4 is a perspective view showing an embodiment of the present invention.
FIG. 5 is a partially cutaway perspective view showing an embodiment of a conventional means for when wiring patterns intersect. 3, 3'...electrode portion, 4...outer layer wiring pattern, 5...inner layer wiring pattern, 6...through hole, 9...chip type wiring component.
Claims (1)
に設けた配線パターンとを互いに交差させて形成
し、これら配線パターンの端部を多層基板の下層
部に設けた電極部に接続し、かつ、多層基板をチ
ツプ形に形成したことを特徴とするチツプ形配線
部品。 The wiring pattern provided on the outer layer of the multilayer board and the wiring pattern provided on the inner layer are formed by crossing each other, and the ends of these wiring patterns are connected to the electrode part provided on the lower layer of the multilayer board, and A chip-shaped wiring component characterized by a substrate formed into a chip shape.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13251789U JPH0371571U (en) | 1989-11-16 | 1989-11-16 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13251789U JPH0371571U (en) | 1989-11-16 | 1989-11-16 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0371571U true JPH0371571U (en) | 1991-07-19 |
Family
ID=31679970
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13251789U Pending JPH0371571U (en) | 1989-11-16 | 1989-11-16 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0371571U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006332415A (en) * | 2005-05-27 | 2006-12-07 | Sharp Corp | Semiconductor device |
WO2010116469A1 (en) * | 2009-03-30 | 2010-10-14 | 富士通株式会社 | Differential path replacement component, printed board, and electronic device |
-
1989
- 1989-11-16 JP JP13251789U patent/JPH0371571U/ja active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006332415A (en) * | 2005-05-27 | 2006-12-07 | Sharp Corp | Semiconductor device |
WO2010116469A1 (en) * | 2009-03-30 | 2010-10-14 | 富士通株式会社 | Differential path replacement component, printed board, and electronic device |
JP5083460B2 (en) * | 2009-03-30 | 2012-11-28 | 富士通株式会社 | Differential path replacement parts, printed circuit boards, and electronic devices |