JPH036901A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH036901A JPH036901A JP1141797A JP14179789A JPH036901A JP H036901 A JPH036901 A JP H036901A JP 1141797 A JP1141797 A JP 1141797A JP 14179789 A JP14179789 A JP 14179789A JP H036901 A JPH036901 A JP H036901A
- Authority
- JP
- Japan
- Prior art keywords
- microstrip line
- integrated circuit
- dielectric
- hybrid integrated
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 21
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 13
- 230000005540 biological transmission Effects 0.000 abstract description 4
- 239000003990 capacitor Substances 0.000 abstract description 4
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 abstract description 2
- 229910002113 barium titanate Inorganic materials 0.000 abstract description 2
- 230000000644 propagated effect Effects 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 239000003989 dielectric material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000001902 propagating effect Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
Landscapes
- Waveguides (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
この発明は、混成集積回路装置に関し、特に小型化に適
した混成集積回路装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a hybrid integrated circuit device, and particularly to a hybrid integrated circuit device suitable for miniaturization.
(従来の技術)
従来の混成集積回路装置では、混成集積回路がアルミナ
誘電体基板上に構成されていた。アルミナの比誘電率は
約10程度と小さいため、伝送波の波長が長くなり、混
成集積回路を構成するマイクロストリップ線路の線路長
を短くることができず、混成集積回路装置を小型化でき
fjかった。(Prior Art) In a conventional hybrid integrated circuit device, a hybrid integrated circuit is constructed on an alumina dielectric substrate. Since the dielectric constant of alumina is as small as about 10, the wavelength of the transmitted wave becomes long, making it impossible to shorten the line length of the microstrip line that makes up the hybrid integrated circuit, making it possible to downsize the hybrid integrated circuit device. won.
第3図はこの種従来の混成集積回路装置のアルミナ訝電
体基板上に構成された混成集積回路の一部を示す上面図
である。FIG. 3 is a top view showing a part of a hybrid integrated circuit constructed on an alumina conductive substrate of this type of conventional hybrid integrated circuit device.
第3図において、トランジスタ2やチップコンデンサ3
は、アルミナ誘電体基板1上に構成されたマイクロスト
リップ線路4により接続されている。In Figure 3, transistor 2 and chip capacitor 3
are connected by a microstrip line 4 formed on an alumina dielectric substrate 1.
上記従来の混成集積回路装置では、第3図において、マ
イクロストリップ線路4の配線領域が、アルミナ誘電体
基板1上の多くの部分を占めている。このため、混成集
積回路装置を小型化することが困難であった。In the conventional hybrid integrated circuit device described above, the wiring area of the microstrip line 4 occupies a large portion of the alumina dielectric substrate 1 in FIG. For this reason, it has been difficult to downsize the hybrid integrated circuit device.
この発明は、上記のような従来の問題点を解消するため
になされたもので、マイクロストリップ線路の配線領域
を縮小することにより、小型化に適した混成集積回路装
置を提供することを目的としている。This invention was made to solve the above-mentioned conventional problems, and aims to provide a hybrid integrated circuit device suitable for miniaturization by reducing the wiring area of the microstrip line. There is.
(i!題を解決するための手段〕
この発明に係る混成集積回路装置は、誘電体基板上にこ
れより大きい誘電率の誘電体基板を部分的に形成し、こ
の部分的に形成された誘電体基板上にマイクロストリッ
プ線路を設けたものである。(Means for solving the i! problem) A hybrid integrated circuit device according to the present invention includes partially forming a dielectric substrate having a larger dielectric constant on a dielectric substrate, and A microstrip line is provided on the body substrate.
この発明においては、誘電体基板上に形成されるマイク
ロストリップ線路が、比誘電率の高い銹電体上に形成さ
れることから、マイクロストリップ線路を伝搬する伝送
波の波長が短縮される。In this invention, since the microstrip line formed on the dielectric substrate is formed on a galvanic material having a high dielectric constant, the wavelength of the transmission wave propagating through the microstrip line is shortened.
以下、この発明の一実施例について説明する。 An embodiment of the present invention will be described below.
第1図および第2図はこの発明の一実施例を示す混成集
積回路装置の上面図および部分断面図である。なお、第
1図では理解の便宜上、封止部材を取り除いた状態の誘
電体基板上の混成集積回路を示しである。1 and 2 are a top view and a partial sectional view of a hybrid integrated circuit device showing an embodiment of the present invention. For convenience of understanding, FIG. 1 shows the hybrid integrated circuit on the dielectric substrate with the sealing member removed.
第1図おいて、アルミナ誘電体基板1上に配置されたト
ランジスタ2やチップコンデンサ3を結ぶマイクロスト
リップ線路4の配線領域の下の部分を、アルミナ誘電体
基板1の厚さの半分程度の、例えば台形状に削って凹部
を形成し、その部分に高い比誘電率をもつ誘電体(例え
ば、チタン酸バリウムε=40)5を埋め込んである。In FIG. 1, the lower part of the wiring area of the microstrip line 4 connecting the transistors 2 and chip capacitors 3 arranged on the alumina dielectric substrate 1 is connected to the alumina dielectric substrate 1 with a thickness of about half the thickness of the alumina dielectric substrate 1. For example, a concave portion is formed by cutting into a trapezoidal shape, and a dielectric material 5 having a high dielectric constant (for example, barium titanate ε=40) is embedded in the concave portion.
第2図は、第1図のA−A線の断面図で、アルミナ誘電
体基板1が厚さ半分程度削られた凹部に高話電率をもつ
誘電体5が埋め込まれ、その上にマイクロストリップ線
路4が形成されている状態を示している。FIG. 2 is a cross-sectional view taken along the line A-A in FIG. A state in which a strip line 4 is formed is shown.
なお、アルミナ誘電体基板1に埋めこまれた高誘電率を
もつ誘電体5上に形成されたマイクロストリップ線路4
の上を、さらに、埋め込まれた誘電体と同種の誘電体で
おおってもよい。これにより、マイクロストリップ線路
4を伝搬する伝送波の波長をより短縮でき、マイクロス
トリップ線路4による配線領域をさらに縮小できる。Note that the microstrip line 4 is formed on a dielectric material 5 with a high dielectric constant embedded in an alumina dielectric substrate 1.
It may be further covered with a dielectric of the same type as the embedded dielectric. Thereby, the wavelength of the transmission wave propagating through the microstrip line 4 can be further shortened, and the wiring area of the microstrip line 4 can be further reduced.
以上説明したように、この発明は、誘電体基板上にこれ
より大きい誘電率の誘電体基板を部分的に形成し、この
部分的に形成された誘電体基板上にマイクロストリップ
線路を設けたので、マイクロストリップ線路を伝搬する
伝送波の波長を短縮でき、このため、マイクロストリッ
プ線路の線路長を短縮でき、マイクロストリップ線路の
配線領域を縮小でき、マイクロストリップ線路による配
線領域を縮小し、混成集積回路装置を小型化することが
できる効果がある。As explained above, in this invention, a dielectric substrate having a larger dielectric constant is partially formed on a dielectric substrate, and a microstrip line is provided on the partially formed dielectric substrate. , the wavelength of the transmission wave propagating through the microstrip line can be shortened, and therefore the line length of the microstrip line can be shortened, the wiring area of the microstrip line can be reduced, the wiring area of the microstrip line can be reduced, and hybrid integration can be achieved. This has the effect of making the circuit device smaller.
第1図はこめ発明の一実施例を示す混成集積回路装置の
上面図、第2図は、第1図のA−A線による断面図、第
3図は従来の混成集積回路装置の上面図である。
図において、1はアルミナ誘電体基板、2はトランジス
タ、3はチップコンデンサ、4はマイクロストリップ線
路、5は高い比誘電率をもつ誘電体である。
なお、各図中の同一符号は同一または相当部分を示す。
第1図
第2図
2FIG. 1 is a top view of a hybrid integrated circuit device showing an embodiment of the invention, FIG. 2 is a sectional view taken along line A-A in FIG. 1, and FIG. 3 is a top view of a conventional hybrid integrated circuit device. It is. In the figure, 1 is an alumina dielectric substrate, 2 is a transistor, 3 is a chip capacitor, 4 is a microstrip line, and 5 is a dielectric material having a high dielectric constant. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 1 Figure 2 Figure 2
Claims (1)
路とが形成された混成集積積回路装置において、前記誘
電体基板上にこれより大きい誘電率の誘電体基板を部分
的に形成し、この部分的に形成された誘電体基板上に前
記マイクロストリップ線路を設けたことを特徴とする混
成集積回路装置。In a hybrid integrated circuit device in which a mixed integrated circuit and a microstrip line are formed on a dielectric substrate, a dielectric substrate having a higher dielectric constant is partially formed on the dielectric substrate, and A hybrid integrated circuit device, characterized in that the microstrip line is provided on a formed dielectric substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1141797A JPH036901A (en) | 1989-06-02 | 1989-06-02 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1141797A JPH036901A (en) | 1989-06-02 | 1989-06-02 | Hybrid integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH036901A true JPH036901A (en) | 1991-01-14 |
Family
ID=15300362
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1141797A Pending JPH036901A (en) | 1989-06-02 | 1989-06-02 | Hybrid integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH036901A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6199292B1 (en) * | 1998-11-04 | 2001-03-13 | Agilent Technologies | Electromechanical dimensioning device |
-
1989
- 1989-06-02 JP JP1141797A patent/JPH036901A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6199292B1 (en) * | 1998-11-04 | 2001-03-13 | Agilent Technologies | Electromechanical dimensioning device |
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