JPH0368423B2 - - Google Patents
Info
- Publication number
- JPH0368423B2 JPH0368423B2 JP55176984A JP17698480A JPH0368423B2 JP H0368423 B2 JPH0368423 B2 JP H0368423B2 JP 55176984 A JP55176984 A JP 55176984A JP 17698480 A JP17698480 A JP 17698480A JP H0368423 B2 JPH0368423 B2 JP H0368423B2
- Authority
- JP
- Japan
- Prior art keywords
- interrupt request
- data
- circuit
- signal
- data bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Information Transfer Systems (AREA)
- Small-Scale Networks (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55176984A JPS57100530A (en) | 1980-12-15 | 1980-12-15 | Serial multiplex data bus system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55176984A JPS57100530A (en) | 1980-12-15 | 1980-12-15 | Serial multiplex data bus system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57100530A JPS57100530A (en) | 1982-06-22 |
| JPH0368423B2 true JPH0368423B2 (enEXAMPLES) | 1991-10-28 |
Family
ID=16023140
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55176984A Granted JPS57100530A (en) | 1980-12-15 | 1980-12-15 | Serial multiplex data bus system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57100530A (enEXAMPLES) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0573491A (ja) * | 1991-09-17 | 1993-03-26 | Nec Corp | バス回路 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5225048B2 (enEXAMPLES) * | 1971-12-15 | 1977-07-05 | ||
| JPS5244494B2 (enEXAMPLES) * | 1972-09-08 | 1977-11-08 | ||
| JPS5337291A (en) * | 1976-09-17 | 1978-04-06 | Yokogawa Hokushin Electric Corp | Tele-monitoring device |
-
1980
- 1980-12-15 JP JP55176984A patent/JPS57100530A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57100530A (en) | 1982-06-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4412326A (en) | Collision avoiding system, apparatus and protocol for a multiple access digital communications system including variable length packets | |
| US4009469A (en) | Loop communications system with method and apparatus for switch to secondary loop | |
| EP0147994B1 (en) | Reconfigurable collision avoiding system, station and protocol for a two path multiple access digital communications system | |
| US3979732A (en) | Asynchronous status interlock circuit for interface adaptor | |
| NZ196850A (en) | Single channel bus communication system:digital data transmitted as short and long pulses for zeros and ones | |
| JPH0638600B2 (ja) | ローカルエリアネットワークシステム | |
| JPS6135587B2 (enEXAMPLES) | ||
| US5884044A (en) | Dedicated DDC integrable multimode communications cell | |
| US6332173B2 (en) | UART automatic parity support for frames with address bits | |
| US4613858A (en) | Error isolator for bi-directional communications buses | |
| JPH0368423B2 (enEXAMPLES) | ||
| US5481753A (en) | I/O device having identification register and data register where identification register indicates output from the data register to be an identifier or normal data | |
| US5550533A (en) | High bandwidth self-timed data clocking scheme for memory bus implementation | |
| JP3459075B2 (ja) | 同期式シリアルバス方式 | |
| JPS61208331A (ja) | シリアルデータ通信方式および装置 | |
| JPS58225756A (ja) | 直列デ−タ通信装置 | |
| JPH05204849A (ja) | 同期式シリアルバス方式 | |
| JPS59147555A (ja) | コンテンシヨン形マルチドロツプ接続方式 | |
| JP2671426B2 (ja) | シリアルデータ転送方法 | |
| JPS62171349A (ja) | 通信制御装置 | |
| JP2624265B2 (ja) | データ伝送装置 | |
| SU1275514A1 (ru) | Устройство дл передачи и приема цифровой информации | |
| JP2820789B2 (ja) | 通信網制御方法 | |
| EP0517492A1 (en) | Data bus systems | |
| JPS60185441A (ja) | システムタイミング同期方式 |