JPH036653A - Memory expansion system for information processor - Google Patents

Abstract

PURPOSE:To always and effectively use a tracer memory as an extension memory by enabling the tracer memory to store successively the bus trace information when no memory extension request is received and to perform the instructed reading/writing jobs by request for the memory extension. CONSTITUTION:When no memory extension request R is received, a process request detecting circuit 4 supplies the information on a bus 3 to a mode control circuit 5 as the bus trace information. A tracer memory 6 is connected to the circuit 5 and controlled to successively store the bus trace information. Meanwhile the request R is received, the circuit 4 decides the information on the bus 3 and detects the process requests given to an extension memory from processors 1-1 - 1-N to supply the read/write information to the circuit 5. Then the memory 6 performs the reading/writing jobs instructed by the circuit 5. As a result, the memory 6 effectively is used as an expanded memory at all times.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a memory expansion method for an information processing device, and in particular to a memory expansion method for an information processing device.
The present invention relates to a memory expansion method for an information processing device having two processors, a processing memory, and a tracer memory.

[Conventional technology]

In the conventional memory expansion method for an information processing device having N processors, processing memory, and tracer memory, the tracer memory always writes bus trace information.
Since tracer memory cannot be used as additional memory, when there is a request for additional memory, processing memory hardware is added.

[Problem to be solved by the invention]

However, the conventional memory expansion method for information processing devices described above takes a long time to become usable due to the hardware expansion of processing memory, and the expansion costs are high, so it is not suitable for urgent situations. It has the following drawbacks.

An object of the present invention is to provide a memory expansion method for an information processing device that allows a tracer memory to be effectively used as an expansion memory at any time in addition to a processing memory when there is a memory expansion request.

[Means to solve the problem]

The memory expansion method of the information processing device of the present invention includes (A) N processors that execute respective processes; (B) a processing memory that stores information necessary to execute the processes of the N processors; , (C) In a memory expansion method for an information processing device including a bus that interconnects the N processors and the processing memory to transfer information, (D) memory that is connected to the bus and When there is no expansion request, the information on the bus is supplied as bus trace information, and when there is a memory expansion request, the information on the bus is judged, so that processing from the N processors to the expansion memory is performed. (E) a processing request detection circuit that detects a request and supplies read/write information; (E) connected to the processing request detection circuit; when there is no memory expansion request;
It enters the trace mode and instructs the write operation of the bus trace information supplied from the processing request detection circuit, and when there is a memory expansion request, it enters the processing mode and performs reading using the read/write information supplied from the processing request detection circuit. (F) A mode control circuit that instructs a write operation; (F) is connected to and controlled by the mode control circuit, and when there is no memory expansion request, sequentially writes bus trace information by performing a write operation instructed by the mode control circuit; The tracer memory serves as an additional memory for the N processors by performing a read/write operation instructed by the mode control circuit when there is a memory expansion request.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a memory expansion method for an information processing apparatus according to the present invention.

The information processing device shown in FIG.
processors 1-1.・・・・・・・・・・L-N and
These processors 1-1.・・・・・・・・・i-N
A processing memory 2 that stores information necessary to execute the processing of these processors 1-1.・・・・・・・・・
. . 1-N and a bus 3 that interconnects the processing memory 2 and transfers information.

When there is no memory expansion request R, the processing request detection circuit 4 is connected to the bus 3 and supplies the information on the bus 3 to the mode control circuit 5 as bus trace information.

Therefore, when there is no memory expansion request R, the mode control circuit 5 connects to the processing request detection circuit 4, enters the trace mode, and transfers the write operation of the bus trace information supplied from the processing request detection circuit 4 to the tracer memory. 6.

Therefore, when there is no memory expansion request R, the tracer memory 6 is connected to and controlled by the mode control circuit 5, and sequentially stores bus trace information by performing a write operation instructed by the mode control circuit 5. ing.

On the other hand, when there is a memory expansion request R, the processing request detection circuit 4 determines the information on the bus 3 to
Processor 1-1. . . . Detects a processing request from 1-N to the additional memory and supplies read/write information to the mode control circuit 5.

Therefore, when there is a memory expansion request R, the mode control circuit 5 enters the processing mode and instructs the tracer memory 6 to perform a read/write operation based on the read/write information supplied from the processing request detection circuit 4.

Therefore, when there is a memory expansion request R, the tracer memory 6 performs the read/write operation instructed by the mode control circuit 5, thereby causing the processor 1-1.・・・・・・
...It will work as an additional memory for 1-N.

As described above, in the memory expansion method of the information processing apparatus of this embodiment, when there is a memory expansion request, the tracer memory can be effectively used as an expansion memory at any time in addition to the processing memory.

〔Effect of the invention〕

As explained above, the memory expansion method of the information processing device of the present invention has the advantage that when there is a memory expansion request, the tracer memory can be effectively used as expansion memory at any time in addition to the processing memory. have.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory expansion method for an information processing apparatus according to the present invention. 1-1. ~1-N...-Processor, 2...
...Processing memory, 3...Bus, 4...
・Processing request detection circuit, 5...Mode control circuit,
6...Tracer memory, R...Memory expansion request.

Claims (1)

[Claims] (A) N processors that execute respective processes; (B) processing memory that stores information necessary to execute the processes of the N processors; (C) N processors. A memory expansion method for an information processing device, comprising: a bus that interconnects the processor and the processing memory to transfer information; (D) when the processor is connected to the bus and there is no memory expansion request; , supplies the information on the bus as bus trace information, and when there is a memory expansion request, detects a processing request from the N processors to the expansion memory by determining the information on the bus. , a processing request detection circuit that supplies read and write information; (E) is connected to the processing request detection circuit, and when there is no memory expansion request, enters the trace mode and reads the bus trace information supplied from the processing request detection circuit; a mode control circuit that instructs a write operation, enters a processing mode when there is a memory expansion request, and instructs a read/write operation based on read/write information supplied from the processing request detection circuit; (F) connected to the mode control circuit; When there is no memory expansion request, the bus trace information is sequentially stored by performing the write operation instructed by the mode control circuit, and when there is a memory expansion request, the bus trace information is stored sequentially by performing the write operation instructed by the mode control circuit. 1. A memory expansion method for an information processing apparatus, comprising a tracer memory that becomes an expansion memory for the N processors by performing read and write operations.