JPH0366170A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make a range of an operating power-supply voltage wide and to enhance an electrical reliability by a method wherein a current-limiting means used to limit an amount of an electric current flowing to a semiconductor region for isolation use is formed and the current-limiting means is constituted by forming a diode element in parallel between a base region of a parasitic bipolar transistor and an electric- current source connected to the region. CONSTITUTION:A current-limiting means used to limit an amount of an electric current flowing to a semiconductor region for isolation use is formed. This current-limiting means is constituted mainly of a parasitic bipolar transistor Q4, a bipolar transistor Q5 to be used as a current mirror and a bias current source 1. Thereby, when an operation of the parasitic bipolar transistor Q4 is started, it is possible to limit an amount of a base current of this transistor and to limit an amount of an electric current flowing between a collector and an emitter. Consequently, a breakdown strength of the parasitic bipolar transistor Q4 can be enhanced. As a result, since a breakdown strength of an output-stage circuit can be regulated not by the parasitic bipolar transistor Q4 but by a vertical-type MOSFET Q1, a range of an operating power-supply voltage of a semiconductor integrated circuit device can be made wide and its application range can be expanded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular to a vertical MO
The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device in which SFETs and bipolar transistors are mounted on the same semiconductor substrate.

[Conventional technology]

2. Description of the Related Art Semiconductor integrated circuit devices, so-called driver ICs, that drive small motors in automobiles, OA equipment, AV equipment, etc. are being developed. This type of semiconductor integrated circuit device has an output stage circuit composed of a power transistor and a driving logic circuit. Power 1 - The transistor directly drives an external device such as a small motor. The driving logic circuit drives the power transistor.

Recently, there has been a trend to use vertical MOSFETs as power transistors. Vertical MOSFETs are capable of high-speed switching operations, and are also excellent in miniaturization and low power consumption. In the case of an n-channel type, the vertical MOSFET is composed of a channel forming region, a gate insulating film, an electrode, a source region, and a drain region. The drain region is n
It consists of a type semiconductor substrate. An operating voltage (drain voltage) of, for example, about 40 [V] is applied to this drain region. The channel forming region is composed of a p-type semiconductor region formed on the main surface of the n-type semiconductor substrate.

The source region is composed of an n-type semiconductor region formed on the main surface of the p-type semiconductor region. Each of the gate insulating film and the gate electrode is sequentially laminated on the channel forming region between the drain region and the sos region.

On the other hand, the driving logic circuit is composed of bipolar transistors capable of high-speed switching operation. A bipolar transistor is a p-type transistor formed on the main surface of an n-type semiconductor substrate.
It is provided on the main surface of the type semiconductor region (semiconductor region for element isolation). The bipolar transistor is a vertical npn type transistor in which operating regions of an n-type emitter region, a p-type base region, and an n-type collector region are sequentially arranged in the depth direction in a region surrounded by the p-type semiconductor region. Consists of.

The lowest potential of the circuit (for example, a ground potential of 0 [V]) is applied to the p-type semiconductor region which is the semiconductor region for element isolation.

The output stage circuit described above commonly connects the source region of a vertical MOSFET which is the power transistor and the collector region of a bipolar transistor which is a driving logic circuit to an output signal terminal.

In other words, the output stage circuit is configured using a source follower output method. An actance load such as a small motor is connected to the output signal terminal.

Regarding the driver IC mentioned above, for example, published by Nikkei McGraw-Hill, Nikkei Mechanical, September 5, 1988.
It is described on pages 46 to 58 of Japan issue.

[Problem to be solved by the invention]

The inventor of the present invention discovered the following problem as a result of failure analysis of the semiconductor integrated circuit device described above.

A parasitic bipolar transistor is formed between the drain power supply terminal of the vertical MOSFET of the output stage circuit and the output signal terminal. This parasitic bipolar transistor is
The collector region of the Vibora transistor of the drive logic circuit is an emitter region, and the semiconductor region for isolation between elements is p.
It is constructed of a vertical npn type, with the semiconductor region serving as the base region and the drain region of the vertical MOSFET serving as the collector region. The parasitic bipolar transistor operates (ON) because its emitter potential becomes a negative voltage due to the back electromotive force generated when the output stage circuit drives a reactive load.
)do. The source-drain breakdown voltage (breakdown voltage BVo,) of the vertical MOSFET is set to a high value of about 60 [V], but the collector-emitter breakdown voltage (breakdown voltage Bvcco) of the parasitic bipolar transistor is set to a high value of about 60 [V]. A value as low as about 30[:V] cannot be secured. That is, since the withstand voltage of the parasitic bipolar transistor is lower than that of the vertical MOSFET, the operating power supply voltage range of the output stage circuit is clamped by the low withstand voltage of the parasitic bipolar transistor. For this reason, there has been a problem that the scope of use of the semiconductor integrated circuit device is limited.

Furthermore, due to the operation of the parasitic bipolar transistor,
When the collector-emitter voltage exceeds the pn junction breakdown voltage, the base-emitter pn junction is permanently destroyed. Therefore, there is a problem in that the electrical reliability of the semiconductor integrated circuit device is reduced.

An object of the present invention is to widen the operating power supply voltage range in a semiconductor integrated circuit device having an output stage circuit in which the source region of a vertical MOSFET and the collector region of a bipolar transistor are commonly connected to an output signal terminal. Our goal is to provide the technology that is possible.

Another object of the present invention is to provide a technique that can improve the electrical reliability of the semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) An output stage circuit in which the source region of a vertical MOSFET and the collector region of a bipolar transistor formed on the main surface of an isolation semiconductor region separated from its drain region by a pn junction are connected to a common output signal terminal. In the semiconductor integrated circuit device, current limiting means is provided for limiting the amount of current flowing through the isolation semiconductor region. This current limiting means includes a parasitic bipolar transistor in which the collector region of the bipolar transistor is an emitter region, the isolation semiconductor region is a base region, and the drain region of the vertical MOSFET is a collector region, and a bipolar transistor that serves as a current mirror. configured. Further, the current limiting means.

A diode element is provided in parallel between the base region of the parasitic bipolar transistor and a current source connected thereto.

(2) Furthermore, the bipolar transistor serving as a current mirror of the current limiting means has substantially the same structure as the bipolar transistor of the output stage circuit.

[For production]

According to the above-mentioned means (1), when the parasitic bipolar transistor starts operating, it is possible to limit the amount of base current and limit the amount of current flowing between the collector and emitter. It is possible to improve pressure resistance.

As a result, the breakdown voltage of the output stage circuit can be regulated by the vertical MOSFET instead of the parasitic bipolar transistor 1 to the transistor, so that the operating power supply voltage range of the semiconductor integrated circuit device can be widened and the range of its applications can be expanded. Furthermore, it is possible to limit the amount of current flowing between the collector and emitter of the parasitic bipolar transistor, and in particular to improve the permanent breakdown voltage of the pn junction between the base and the emitter, thereby improving the electrical reliability of the semiconductor integrated circuit device. can.

According to the above-mentioned means (2), since the bipolar transistor of the current limiting means can be formed in the step of forming the bipolar transistor of the output stage circuit, the step corresponds to the step of forming the bipolar transistor of the current limiting means. Accordingly, the number of manufacturing steps for semiconductor integrated circuit devices can be reduced.

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device in which an output stage circuit is configured with a vertical MOSFET and a bipolar transistor.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

FIG. 2 (equivalent circuit @
).

The output stage circuit of the semiconductor integrated circuit device (driver IC) is constructed of a source follower output type formed by a vertical MO8FET Q1 and a bipolar transistor Q2 as shown in FIG. The vertical M○5FET QI is used as a power transistor and directly drives an external device such as a small motor (reactance load L). This vertical MO8FETQI is composed of n channels. The bipolar transistor Q2 is used as a driving logic circuit element (load element) and drives the vertical MO5FET QI. Bipolar transistor Q2 is configured as a vertical npn type. The source region of the vertical MO8FET QI and the collector region of the bipolar transistor Q2 of this output stage circuit are each connected to a common output signal terminal P out.

The ground potential GND is connected to this output signal terminal P out with an actance load interposed therebetween. Ground potential G
ND is the lowest potential used within the semiconductor integrated circuit device, for example O[V].

The drain region of the vertical MO8FET QI is connected to a power supply voltage VI with a power supply terminal Pvd interposed therebetween. is applied. The power supply voltage vllo is, for example, 40 [V].

A booster circuit c is connected to the gate electrode of the vertical 11M08FETQI.
Each of the m-movement MO8FETQ3 is connected.

The driving MO8FET Q3 is driven by a control signal input from a control signal terminal Pin via an inverter circuit In. This drive MO8FETQ3 is driven by a drive signal boosted by the booster circuit C based on the control signal.
The vertical MO8FETQ1 of the output stage circuit is driven.

The base electrode of the bipolar transistor Q2 is connected to the power supply voltage terminal Pvb, and the emitter electrode is connected to the power supply voltage terminal Pv. The power supply voltage terminal Pvb is a terminal that supplies constant power, and the power supply voltage terminal Pv is, for example, at the lowest potential of 0 [V].

In this semiconductor integrated circuit device, a parasitic bipolar transistor Q4 is formed in parallel with a vertical M08FET Q1 between a power supply terminal Pvd and an output signal terminal P out. This parasitic bipolar transistor Q4 is composed of npnll, has a collector region connected to the power supply terminal Pvd, and has an emitter region connected to the output signal terminal p out. This parasitic bipolar transistor Q4 has a current limiting circuit (
Current limiting means) are provided. This current limit circuit is mainly used.

It is composed of the parasitic bipolar transistor Q4, a bipolar transistor Q5 serving as a current mirror, and a bias current source I. The bipolar transistor Q5, which serves as a current mirror, is constructed of an npn type. - The base 11 of this bipolar transistor Q5 is connected to the base electrode of the parasitic bipolar transistor Q4, as well as to the collector region and the bias current source. The bias current source is configured to flow a minute bias current of, for example, about 0.1 [mA]. The emitter electrode of bipolar transistor Q5 is connected to ground potential GND.

Next, the specific structures of the output stage circuit and current limiting circuit described above will be briefly explained using FIG. 1 (schematic sectional view).

The semiconductor integrated circuit device is composed of an n-type semiconductor substrate (or n-type well region) 1 made of single crystal silicon. This n
A power supply voltage V o o is applied to the type semiconductor substrate 1 .

The vertical MO8FETQI of the output stage circuit is formed on the main surface of the n-type semiconductor substrate 1. This vertical MO8FETQI mainly consists of a channel forming region, a gate insulating film 6. Gate electrode 7
, a drain region, and a source region S. The drain region is formed of an n-type semiconductor substrate. The channel forming region 12- is composed of the p-type semiconductor region 4 provided on the main surface of the n-type semiconductor substrate 1. The source region S is composed of an n-type semiconductor region 5 provided on the main surface of the p-type semiconductor region 4 . n which is the source region S! Electrodes 8 are provided on the main surfaces of each of the two semiconductor regions 5 and the p-type semiconductor region 4, which is a channel forming region.

The bipolar transistor Q2 of the output stage circuit is connected to the n
A p-type semiconductor region (
It is formed on the main surface of the semiconductor region for element isolation (2). This p-type semiconductor region 2 is a bipolar transistor Q2. It is configured to electrically isolate the bipolar transistors (for example, Q5) of other logic circuits. The bipolar transistor Q2 has an n-type emitter region, P
It is constructed of a vertical npn type in which a type base region and an n type collector region are sequentially arranged in the depth direction of the substrate. The n-type collector region is composed of an n-type semiconductor region 3 provided on the main surface of the p-type semiconductor region 2. The p-type base region is separated by the p-type semiconductor region 4 provided on the main surface of the n-type semiconductor region 3. The n-type emitter region is composed of an n-type semiconductor region 5 provided on the main surface of the p-type semiconductor region 4.

The bipolar transistor Q5 of the current limiting circuit has substantially the same structure as the bipolar transistor Q2 of the output stage circuit. That is, the bipolar transistor Q5 is provided on the main surface of the p-type semiconductor region 2, and has an n-type emitter region (5), a p-type base region (4), and an n-type collector region (3) arranged vertically. It is composed of npn type. As described above, this bipolar transistor Q5 has its p-type base region and n-type collector region connected to the bias current source (2) and also to the base region of the parasitic bipolar transistor Q4.

This parasitic bipolar transistor Q4 uses the collector region of the bipolar transistor Q2 of the output stage circuit as an emitter region, the p-type semiconductor region 2 as a base region, and the n-type semiconductor substrate 1, which is the drain region of the vertical MO8FET QI of the output stage circuit, as a collector region. Constructed as. In other words, the parasitic bipolar transistor Q4 is constituted by a vertical npn type transistor in which an n-type emitter region, a p-type base region, and an n-type collector region are sequentially arranged in the depth direction of the substrate. Since the base region of this parasitic bipolar transistor Q4 is constituted by the p-type semiconductor region 2, the bias current source is connected to the p-type semiconductor region 2.

Next, the specific operation of the above-mentioned current limiting circuit will be briefly explained using FIG. 1 and FIG. 2.

First, the reactance load is driven by driving the vertical MO8FETQI in the preceding stage circuit of the output stage circuit.

By driving the reactance load, the emitter region of the parasitic bipolar transistor Q4 becomes a negative voltage due to the back electromotive force, and the parasitic bipolar transistor Q4 attempts to start operating.

When the parasitic bipolar transistor Q4 starts operating, the base potential of the parasitic bipolar transistor Q4 is defined by the emitter potential, and the amount of current injected into the base region is a minute amount flowing from the via 5-input current source I of the current limiting circuit. Only electric current. That is, the base potential of the parasitic bipolar transistor Q4 is equal to the base potential of the bipolar transistor Q5 serving as a current mirror. Therefore, the parasitic bipolar transistor Q
4, since the amount of current flowing between the base and the emitter is limited, the amount of current flowing between the collector and emitter is limited. The amount of current flowing between the collector and emitter is only hFE times the base current. As a result, the collector-emitter breakdown voltage (breakdown voltage) of the parasitic bipolar transistor Q4 is equal to the breakdown voltage Bvc at the start of operation,
, o withstand voltage BV to which a base resistance component is added. It is determined by ER and can be improved to about 65 [V].

In this way, the collector regions of the bipolar transistor 1 to the transistor Q2 formed on the main surface of the isolation semiconductor region (p-type semiconductor region 2) separated from the source region S of the vertical MO8FET QI and its drain region by a pn junction. A semiconductor integrated circuit device 16 (driver IC) having output stage circuits each connected to a common output signal terminal P out is provided with current limiting means for limiting the amount of current flowing through the isolation semiconductor region. This current limiting means mainly consists of the parasitic bipolar transistors 1 to transistor Q.
2 and the bipolar transistor Q5 which acts as a current mirror.
and a bias current source I. With this configuration,
When the parasitic bipolar transistor Q4 starts operating,
It is possible to limit the amount of current flowing between the collector and emitter by keeping the amount of current flowing between the collector and emitter.
The breakdown voltage of the parasitic bipolar transistor Q4 can be improved. As a result, the withstand voltage of the output stage circuit is reduced to vertical MO8FET QI (approximately 6
Since the voltage can be regulated at 0 [V]), the operating power supply voltage range of the semiconductor integrated circuit device can be widened, and the range of its applications can be expanded.

Furthermore, it is possible to limit the amount of current flowing between the collector and emitter of the parasitic bipolar transistor Q4, and in particular to improve the permanent breakdown voltage of the pn junction between the base and the emitter, thereby improving the electrical reliability of the semiconductor integrated circuit device. I can do it.

Further, the bipolar transistor Q5 serving as a current mirror of the current limiting means has substantially the same structure as the bipolar transistor Q2 of the output stage circuit. With this configuration, the bipolar transistor Q5 of the current limiting means can be formed in the step of forming the bipolar transistor Q2 of the output stage circuit, so the semiconductor The number of manufacturing steps for integrated circuit devices can be reduced.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, in the present invention, the base region of the parasitic bipolar transistor Q4 and the bias current source connected thereto are
The current limiting means may include a diode element provided in parallel between the current limiting means and the current limiting means. This diode element has, for example, an anode region formed by an n-type semiconductor region 4 and a cathode region formed by an n-type semiconductor region 5.

Further, the present invention provides the parasitic bipolar transistor Q4
It is also possible to use current limiting means provided with a resistive element in the base region of the circuit.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

The operating power supply voltage range of the semiconductor integrated circuit device (driver IC) can be widened.

Furthermore, the electrical reliability of the semiconductor integrated circuit device can be improved.

Furthermore, the number of manufacturing steps for the semiconductor integrated circuit device can be reduced.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a main part showing a schematic configuration of an output stage circuit of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of the output stage circuit. 19- In the figure, Ql... Vertical MO8FET, Q2... Bipolar transistor, Q4... Parasitic bipolar transistor, Q5... Bipolar transistor (current limiting means), ■... Bias current source (current restriction means), 1...
- Semiconductor substrate, 2... p-type semiconductor region (semiconductor region for isolation between elements), 3, 4.5... semiconductor region. 0-

Claims (1)

[Claims] 1. Connecting the source region of the vertical MOSFET and its drain region to another semiconductor region formed on the main surface of the isolation semiconductor region separated by a pn junction to a common output signal terminal. 1. A semiconductor integrated circuit device having an output stage circuit, further comprising current limiting means for limiting the amount of current flowing through the isolation semiconductor region. 2. Another semiconductor region formed on the main surface of the isolation semiconductor region is a collector region of a bipolar transistor, and the current limiting means uses the collector region of the bipolar transistor as an emitter region and the isolation semiconductor region as a base region. 2. The semiconductor integrated circuit device according to claim 1, wherein said parasitic bipolar transistor whose collector region is the drain region of said vertical MOSFET is provided with a bipolar transistor which serves as a current mirror therewith. 3. The semiconductor integrated circuit device according to claim 2, wherein the bipolar transistor of the current limiting means has substantially the same structure as the bipolar transistor of the output stage circuit. 4. Another semiconductor region formed on the main surface of the isolation semiconductor region is a collector region of a bipolar transistor, and the current limiting means uses the collector region of the bipolar transistor as an emitter region and the isolation semiconductor region as a base region. , wherein a diode element is provided in parallel between a base region of a parasitic bipolar transistor whose collector region is the drain region of the vertical MOSFET and a current source connected thereto. The semiconductor integrated circuit device described in .