JPH0365891B2 - - Google Patents

Info

Publication number
JPH0365891B2
JPH0365891B2 JP59206424A JP20642484A JPH0365891B2 JP H0365891 B2 JPH0365891 B2 JP H0365891B2 JP 59206424 A JP59206424 A JP 59206424A JP 20642484 A JP20642484 A JP 20642484A JP H0365891 B2 JPH0365891 B2 JP H0365891B2
Authority
JP
Japan
Prior art keywords
substrate
semiconductor substrate
protective film
electrode
chlorine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59206424A
Other languages
Japanese (ja)
Other versions
JPS6184834A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP20642484A priority Critical patent/JPS6184834A/en
Publication of JPS6184834A publication Critical patent/JPS6184834A/en
Publication of JPH0365891B2 publication Critical patent/JPH0365891B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は加工プロセス中における半導体基板
の保護方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) This invention relates to a method for protecting a semiconductor substrate during a fabrication process.

(従来の技術) GaAsなどの化合物半導体は高い電子移動度を
利用した高速集積回路または発光特性を利用した
光−電子デバイス用の材料として注目されてい
る。
(Prior Art) Compound semiconductors such as GaAs are attracting attention as materials for high-speed integrated circuits that utilize high electron mobility or opto-electronic devices that utilize light emitting properties.

現在上述のデバイス製造のための結晶成長、エ
ツチング、イオン注入などの各プロセスは殆んど
各独立した装置で行われている。しかし化合物半
導体は基板表面が酸化され易く、大気に曝しただ
けでその表面に酸化膜が生じ、そのためデバイス
特性が低下するなどの基板を加工する上でシリコ
ンにはない問題を有している。例えば、エピタキ
シヤル結晶成長、イオン注入、ドライエツチング
などの加工を行うに際して、化合物半導体の基板
表面には既に数10Å程度の厚さの自然酸化膜が形
成されているため、先ず酸処理により表面クリー
ニングを行わねばならない。また結晶成長、イオ
ン注入、エツチングなどの処理を行つた後にも半
導体基板は大気に曝されるため、基板表面の酸化
は免れない。特に、反応性ガスによるドライエツ
チングではエツチング後の基板表面はエツチング
ガスによつて汚染され、高清浄表面が得られな
い。そこでドライエツチング後に電極付けを行つ
てデバイスを製造する場合、熱処理により基板表
面をクリーニングする方法が行われているが、こ
の熱処理は大気中に設置された装置で行われてい
るため熱処理直後の大気による基板表面の酸化は
避けられないことになる。
Currently, most of the processes such as crystal growth, etching, and ion implantation for manufacturing the above-mentioned devices are performed using independent equipment. However, compound semiconductors have problems that silicon does not have when processing substrates, such as the substrate surface being easily oxidized and an oxide film forming on the surface even when exposed to the atmosphere, resulting in deterioration of device characteristics. For example, when performing processes such as epitaxial crystal growth, ion implantation, and dry etching, a natural oxide film with a thickness of several tens of angstroms has already been formed on the surface of a compound semiconductor substrate, so the surface must first be cleaned with acid treatment. must be carried out. Furthermore, since the semiconductor substrate is exposed to the atmosphere even after crystal growth, ion implantation, etching, etc., oxidation of the substrate surface is inevitable. In particular, in dry etching using a reactive gas, the surface of the substrate after etching is contaminated by the etching gas, making it impossible to obtain a highly clean surface. Therefore, when manufacturing devices by attaching electrodes after dry etching, a method is used in which the substrate surface is cleaned by heat treatment, but since this heat treatment is performed in equipment installed in the atmosphere, Therefore, oxidation of the substrate surface is inevitable.

更に、ドライエツチング後に分子線エピタキシ
ヤル法により結晶成長を行う場合、真空予備室に
て基板を高温ベークして表面クリーニングを行つ
ているが、大気への露出により形成した酸化膜を
除去するには充分ではない。このため最近ではク
リーニング、イオン注入、エピタキシヤル成長な
どの各処理をそれぞれの装置を気密に接続して、
半導体基板を大気中に曝すことなく連続して行う
方法が提案されている。
Furthermore, when crystal growth is performed by molecular beam epitaxial method after dry etching, the substrate is baked at high temperature in a vacuum preparatory chamber to clean the surface, but it is difficult to remove the oxide film formed by exposure to the atmosphere. Not enough. For this reason, recently, various processes such as cleaning, ion implantation, and epitaxial growth are performed by connecting the respective devices airtightly.
A method has been proposed in which the process is performed continuously without exposing the semiconductor substrate to the atmosphere.

(発明が解決しようとする問題点) しかしながら10-9Torrの高真空中でも、エツ
チングされた基板表面は清浄であるが故に残留ガ
スを吸着し易い。そのため、上述の接続された装
置間を半導体基板が移動するとき、たとえ或る程
度の真空下であつても基板の加工表面は汚染、酸
化されることになる。
(Problems to be Solved by the Invention) However, even in a high vacuum of 10 -9 Torr, the etched substrate surface is clean and therefore tends to adsorb residual gas. Therefore, when a semiconductor substrate is moved between the above-mentioned connected devices, the processed surface of the substrate is contaminated and oxidized even under a certain degree of vacuum.

上記は主としてGaAsなどの化合物半導体に対
して複数の加工を異つた装置で行うときに生じる
問題であるが、Siなどの単元素半導体の場合も、
ドライエツチング後の基板表面は化合物半導体と
同様に汚染され易い。
The above is a problem that mainly occurs when multiple processes are performed on compound semiconductors such as GaAs using different equipment, but it also occurs in the case of single-element semiconductors such as Si.
The surface of the substrate after dry etching is susceptible to contamination, as is the case with compound semiconductors.

この発明は上記に鑑みなされたものであつて、
加工処理した半導体を次工程に輸送するときに加
工面の汚染、酸化を防止するようにした半導体基
板の保護方法を提供することを目的としている。
This invention was made in view of the above, and
It is an object of the present invention to provide a method for protecting a semiconductor substrate, which prevents contamination and oxidation of the processed surface when the processed semiconductor is transported to the next process.

(問題点を解決するための手段) 上述の問題点を解決するため、この発明におい
ては第2図の処理工程図に示すように、基板処理
装置Aにおいて、半導体基板をクリーニングした
後に所定の微細加工を行う。加工処理を完了した
半導体基板の表面に直ちに放電プラズマにより発
生した塩素中性ラジカルを250℃以下の温度下で
吸着させて保護膜を形成させ、しかる後に基板処
理装置Bと気密に接続している輸送管Cを介して
基板処理装置Bへ輸送する。基板処理装置Bにお
いては基板の加工面の保護膜を熱処理などにより
除去した後に次工程の加工処理を行う。このよう
にして、半導体基板の加工面に塩素中性ラジカル
による保護膜を形成し、次工程の処理装置へ輸送
する間一時的に半導体基板表面の汚染酸化などを
防止するのである。従つて、この発明の対象とな
る半導体基板は化合物半導体ばかりでなく単元素
半導体にも有効である。
(Means for solving the problem) In order to solve the above-mentioned problem, in the present invention, as shown in the process diagram of FIG. 2, in the substrate processing apparatus A, after cleaning the semiconductor substrate, a predetermined Perform processing. Immediately on the surface of the processed semiconductor substrate, neutral chlorine radicals generated by discharge plasma are adsorbed at a temperature of 250°C or less to form a protective film, and then the substrate is airtightly connected to substrate processing equipment B. It is transported to the substrate processing apparatus B via the transport pipe C. In the substrate processing apparatus B, the next step of processing is performed after removing the protective film on the processing surface of the substrate by heat treatment or the like. In this way, a protective film made of neutral chlorine radicals is formed on the processed surface of the semiconductor substrate, and the surface of the semiconductor substrate is temporarily prevented from being contaminated or oxidized while being transported to the processing equipment for the next step. Therefore, the semiconductor substrate to which the present invention is applied is effective not only for compound semiconductors but also for single element semiconductors.

塩素中性ラジカルを吸着させるときに、半導体
基板表面を250℃以下室温程度の間に保持するの
は基板表面に塩素中性ラジカルを効率良く吸着さ
せ、有効な保護膜を形成するためであり、250℃
以上であると基板表面が塩素中性ラジカルにより
エツチングされる恐れが生ずる。
When adsorbing chlorine neutral radicals, the semiconductor substrate surface is held at a temperature below 250°C or around room temperature in order to efficiently adsorb chlorine neutral radicals on the substrate surface and form an effective protective film. 250℃
If this is the case, there is a risk that the surface of the substrate will be etched by the neutral chlorine radicals.

第2図においてはこの発明の処理工程図を示し
たが、第1図において各工程の具体的な構成装置
を例示し、この発明を詳細に説明する。第1図に
おいて、Aは基板処理装置、Bは次工程基板処理
装置、Cは上記の両基板処理装置を気密に接続し
ている輸送管であつて、管内は10-9Torr程度の
真空度を保つている。基板処理装置Aは図示の実
施例ではプラズマ室1と試料加工室2とから成
り、両室の境界面に穿設された開口部には多数の
通孔を有し、且つ所定の間隔を保つて平行に配設
された二枚のメツシユ電極板7a,7bより構成
された電極7を設ける。試料加工室2の電極7の
下部には支持台6があり、加工処理する半導体基
板3を設置する。
Although FIG. 2 shows a process diagram of the present invention, the present invention will be explained in detail by illustrating specific constituent devices of each step in FIG. 1. In Figure 1, A is a substrate processing device, B is a substrate processing device for the next process, and C is a transport pipe that airtightly connects both substrate processing devices, and the vacuum inside the pipe is approximately 10 -9 Torr. I'm keeping it. In the illustrated embodiment, the substrate processing apparatus A consists of a plasma chamber 1 and a sample processing chamber 2, and an opening formed at the interface between the two chambers has a large number of through holes, and a predetermined interval is maintained between the two chambers. An electrode 7 composed of two mesh electrode plates 7a and 7b arranged in parallel is provided. There is a support stand 6 below the electrode 7 in the sample processing chamber 2, on which a semiconductor substrate 3 to be processed is placed.

次工程基板処理装置は本実施例においては真空
蒸着装置を示し、蒸着室8の下部には蒸発源9が
設けられ、適当な加熱手段により蒸発源9より放
出された気体分子10は半導体試料3上に蒸着さ
れる。
The next process substrate processing apparatus is a vacuum evaporation apparatus in this embodiment, and an evaporation source 9 is provided in the lower part of the evaporation chamber 8. Gas molecules 10 released from the evaporation source 9 by an appropriate heating means are applied to the semiconductor sample 3. is deposited on top.

上記の両基板処理装置A,Bは輸送管Cにより
気密に接続して居り、輸送管には必要に応じてバ
ルブ11が設けられ、また真空ポンプ(図示せ
ず)を接続し、半導体基板3を輸送するとき、そ
の内部を10-9Torr程度の真空度に保持するよう
構成されている。
The above substrate processing apparatuses A and B are airtightly connected by a transport pipe C, and the transport pipe is provided with a valve 11 as necessary, and a vacuum pump (not shown) is connected to the transport pipe, and the semiconductor substrate The structure is designed to maintain a vacuum level of approximately 10 -9 Torr inside the container during transportation.

(作用) 基板処理装置Aの試料加工室2内の支持台6に
加工処理する半導体基板3を設置する。この半導
体基板3の表面は必要に応じて予じめクリーニン
グしておく。
(Operation) The semiconductor substrate 3 to be processed is placed on the support stand 6 in the sample processing chamber 2 of the substrate processing apparatus A. The surface of this semiconductor substrate 3 is cleaned in advance if necessary.

ガス導入管12よりプラズマ室1へClなどのエ
ツチングガスを供給し、マイクロ波電界により放
電し、プラズマ形成する。電極7a及びプラズマ
室に正電位を印加することによりイオン引き出し
電極として作用し、プラズマ中のイオン4は加速
されながら試料加工室2に導かれ、第3図aに示
すように半導体基板3のエツチングが行われる。
プラズマ室1中の塩素中性ラジカル5も電極7に
設けられた多数の孔を通つて試料加工室2に拡散
し、半導体基板3と接触し、イオンと共にエツチ
ングが行われる。
Etching gas such as Cl is supplied to the plasma chamber 1 from the gas introduction pipe 12, and discharge is caused by a microwave electric field to form plasma. By applying a positive potential to the electrode 7a and the plasma chamber, it acts as an ion extraction electrode, and the ions 4 in the plasma are guided to the sample processing chamber 2 while being accelerated, and the semiconductor substrate 3 is etched as shown in FIG. 3a. will be held.
The neutral chlorine radicals 5 in the plasma chamber 1 also diffuse into the sample processing chamber 2 through a number of holes provided in the electrode 7, come into contact with the semiconductor substrate 3, and are etched together with the ions.

半導体基板3に所定量のエツチングが行われた
ら、適当な手段によりイオン基板表面への突入を
阻止し、半導体基板3の温度を250℃以下とする
ことにより、第3図bに示すように半導体基板3
表面に塩素中性ラジカル5が吸着しはじめ、塩素
中性ラジカル堆積層5′が形成される。この発明
ではこの塩素中性ラジカル堆積層を半導体基板加
工面の汚染、酸化などに対する保護膜として用い
る。
After a predetermined amount of etching has been performed on the semiconductor substrate 3, the ions are prevented from entering the surface of the substrate by appropriate means, and the temperature of the semiconductor substrate 3 is kept below 250°C, so that the semiconductor substrate 3 is etched as shown in FIG. Board 3
The chlorine neutral radicals 5 begin to be adsorbed on the surface, and a chlorine neutral radical deposit layer 5' is formed. In this invention, this chlorine neutral radical deposited layer is used as a protective film against contamination, oxidation, etc. of the processing surface of a semiconductor substrate.

放電プラズマ中のイオンの基板表面への突入を
阻止し、塩素中性ラジカルのみを基板と接触させ
る方法は種々あるが、この数列を第4図により説
明すると、第4図aは半導体基板3を支持してい
る支持台6を回転し得るよう適当な回転手段(図
示せず)を設け、イオン4によるエツチングが完
了し、塩素中性ラジカル5による保護膜形成工程
になつたら、支持台6を180度回転させて、支持
台6の裏面を電極7と対向させる。その結果、電
極7より試料加工室2へ引き出されたイオン4は
方向性を有しているため、支持台6の裏面と衝突
し、基板3の表面への突入は阻止される。しか
し、塩素中性ラジカル5は加工室内に拡散されて
いるので支持台6の半導体基板3と接触し、吸着
されて第3図bの如くその表面に保護膜が形成さ
れる。
There are various methods to prevent ions in the discharge plasma from entering the substrate surface and to bring only chlorine neutral radicals into contact with the substrate. An appropriate rotation means (not shown) is provided to rotate the supporting base 6, and when the etching by ions 4 is completed and the step of forming a protective film by chlorine neutral radicals 5 begins, the supporting base 6 is rotated. Rotate 180 degrees so that the back surface of the support base 6 faces the electrode 7. As a result, since the ions 4 extracted from the electrode 7 into the sample processing chamber 2 have directionality, they collide with the back surface of the support base 6 and are prevented from entering the surface of the substrate 3. However, since the chlorine neutral radicals 5 have been diffused into the processing chamber, they come into contact with the semiconductor substrate 3 on the support stand 6 and are adsorbed, forming a protective film on its surface as shown in FIG. 3b.

第4図bは電極7と半導体基板3との間にシヤ
ツター13を介在させて、イオンの方向性を利用
して、半導体基板に向つて直進するイオン4をシ
ヤツター13と衝突させ、半導体基板3への突入
を阻止する。一方、塩素中性ラジカルは上記と同
様に加工室2内を拡散して、半導体基板と接触
し、保護膜を形成する。
In FIG. 4b, a shutter 13 is interposed between the electrode 7 and the semiconductor substrate 3, and the ions 4 traveling straight toward the semiconductor substrate are collided with the shutter 13 by utilizing the directionality of the ions. prevent entry into. On the other hand, the chlorine neutral radicals diffuse within the processing chamber 2 in the same manner as described above, come into contact with the semiconductor substrate, and form a protective film.

上記2例は物理的にイオンの半導体基板への突
入を阻止する方法を示したが、次に電気的に阻止
する方法を第4図cにより説明すると、プラズマ
室1と試料加工室2間に設けた電極7のうち、電
極板7aにアース電位を、電極板7bにはイオン
電流モニター14の電流値が零となるようなバイ
アス電圧を印加する。その結果、プラズマ室1内
のイオンは電極板7aの孔を通過した後に正電位
に保たれた電極板7bにより反発され、試料加工
室2への進入か阻止される。一方、塩素中性ラジ
カルは電荷を持たないため電極7に反射されるこ
となく電極の多数の孔を通つて加工室2へ順次拡
散し、半導体基板表面に吸着、堆積する。第4図
dでは半導体基板3の表面が正電位に保たれ、且
つイオン電流モニター14の電流値が零となるよ
うに基板3とアース電位との間にバイアス電圧を
印加する。従つて、試料加工室2に引き出された
イオン4は基板3が正電位に保たれているため、
反発し、基板3へ突入することができない。一
方、塩素中性ラジカルは上述のように電荷を持た
ないため、基板の正電位、負電位に拘らず、吸着
堆積する。第4図eでは試料加工室2において、
電極7を侠んで一対の電極15a,15bを設
け、電極7a及びプラズマ室内壁には正の電位と
なるように電圧を印加し、更に一対の電極15
a,15bのうち、一方を負の電位となるような
電圧を印加する。このため、電極7はイオン引き
出し電極として作用し、イオンは電極7の多数の
孔を加速して加工室2内へ導かれるが、一対の電
極9a,9bのうち負電位に保持されている電極
側へ偏向され、基板表面への突入は阻止され、塩
素中性ラジカル5のみが、半導体基板表面に堆積
することになる。
The above two examples have shown the method of physically preventing ions from entering the semiconductor substrate, but next we will explain the method of electrically preventing ions from entering the semiconductor substrate using Figure 4c. Of the electrodes 7 provided, a ground potential is applied to the electrode plate 7a, and a bias voltage such that the current value of the ion current monitor 14 becomes zero is applied to the electrode plate 7b. As a result, the ions in the plasma chamber 1 are repelled by the electrode plate 7b kept at a positive potential after passing through the holes in the electrode plate 7a, and are prevented from entering the sample processing chamber 2. On the other hand, since the neutral chlorine radicals have no electric charge, they are not reflected by the electrode 7, but are sequentially diffused into the processing chamber 2 through the many holes of the electrode, and are adsorbed and deposited on the surface of the semiconductor substrate. In FIG. 4d, a bias voltage is applied between the substrate 3 and the ground potential so that the surface of the semiconductor substrate 3 is kept at a positive potential and the current value of the ion current monitor 14 becomes zero. Therefore, since the substrate 3 is kept at a positive potential, the ions 4 extracted into the sample processing chamber 2 are
It is repelled and cannot enter the substrate 3. On the other hand, since neutral chlorine radicals have no charge as described above, they are adsorbed and deposited regardless of the positive or negative potential of the substrate. In Fig. 4e, in the sample processing chamber 2,
A pair of electrodes 15a and 15b are provided next to the electrode 7, and a voltage is applied to the electrode 7a and the plasma chamber wall so as to have a positive potential.
A voltage is applied so that one of a and 15b has a negative potential. For this reason, the electrode 7 acts as an ion extraction electrode, and ions are guided into the processing chamber 2 by accelerating the many holes in the electrode 7, but of the pair of electrodes 9a and 9b, the electrode held at a negative potential is The chlorine neutral radicals 5 are deflected to the side, are prevented from entering the substrate surface, and only the chlorine neutral radicals 5 are deposited on the semiconductor substrate surface.

上述のようにイオンの半導体表面への突入を阻
止し、塩素中性ラジカルにて所定の厚さの保護膜
を半導体基板3表面に形成したら、公知の適当な
方法を用いて基板3を輸送管Cを通つて次工程基
板処理装置Bへ移送する。このときの輸送管C内
の真空度は10-9Torr程度に維持されている。こ
の保護膜を大気中に曝すと大気中の水分により酸
が形成されるため好ましくないが、上述のような
真空度下においては数100〜1000Å厚のラジカル
を堆積させることにより有用な保護膜となる。
After preventing ions from entering the semiconductor surface as described above and forming a protective film of a predetermined thickness on the surface of the semiconductor substrate 3 using neutral chlorine radicals, the substrate 3 is transferred to a transport pipe using a known appropriate method. C, and then transferred to the next process substrate processing apparatus B. At this time, the degree of vacuum within the transport pipe C is maintained at approximately 10 -9 Torr. Exposure of this protective film to the atmosphere is undesirable because acids will be formed by the moisture in the atmosphere, but under the above-mentioned vacuum conditions, radicals with a thickness of several 100 to 1000 Å are deposited, making it a useful protective film. Become.

半導体基板3を基板処理装置Bの所定位置に設
置したら、保護膜の除去を行う。この保護膜の除
去は加熱または荷電ビームの照射等により容易に
行える。即ち、第5図aに示すように基板3の支
持台6内にヒータ或るいは赤外線ランプなどの加
熱手段16を内蔵し、基板3を250℃以上に加熱
することにより基板3表面に堆積した保護膜は蒸
発、除去される。また、第5図bに示すように、
加熱手段16を基板3の上面に配置し、基板を加
熱することにより第5図aの実施例と同様に容易
に保護膜を除去することができる。更に、第5図
cに示すように、基板3の表面を電子ビーム或る
いは低速イオンビーム17を走査して堆積した中
性ラジカル5を除去することもできる。どのよう
な保護膜除去手段を用いるかは、基板処理装置B
の構造などを考慮の上決定すべきであるが、いず
れの除去手段を用いても保護膜は容易に除去する
ことができ、特に第5図cの手段では、半導体基
板の加工処理に必要な領域のみの保護膜を選択的
に除去することができる。
After the semiconductor substrate 3 is installed at a predetermined position in the substrate processing apparatus B, the protective film is removed. This protective film can be easily removed by heating or irradiation with a charged beam. That is, as shown in FIG. 5a, a heating means 16 such as a heater or an infrared lamp is built into the support 6 of the substrate 3, and the substrate 3 is heated to 250° C. or higher, thereby depositing on the surface of the substrate 3. The protective film is evaporated and removed. Also, as shown in Figure 5b,
By disposing the heating means 16 on the upper surface of the substrate 3 and heating the substrate, the protective film can be easily removed as in the embodiment shown in FIG. 5a. Furthermore, as shown in FIG. 5c, the deposited neutral radicals 5 can be removed by scanning the surface of the substrate 3 with an electron beam or a slow ion beam 17. The type of protective film removal means to be used depends on the substrate processing apparatus B.
The protective film should be determined taking into account the structure of the semiconductor substrate, etc., but the protective film can be easily removed using any of the removal methods.In particular, the method shown in Figure 5c removes the protective film necessary for processing the semiconductor substrate. The protective film can be selectively removed only in regions.

上述の如く、半導体基板3上の保護膜を除去し
たら、続いて、クリーニングすることなく、結晶
成長、イオン注入、金属蒸着、エツチングなどの
次工程処理を行う。
As described above, after the protective film on the semiconductor substrate 3 is removed, subsequent processes such as crystal growth, ion implantation, metal vapor deposition, and etching are performed without cleaning.

(実施例) 半導体基板としてGaAsを用い、電界効果型ト
ランジスタのリセス構造のゲート部を形成するプ
ロセスをこの発明の実施例として示す。
(Example) A process of forming a gate portion of a recessed structure of a field effect transistor using GaAs as a semiconductor substrate will be described as an example of the present invention.

使用する装置の基本的構成は第1図に示した構
成と概略同じであつて、処理装置Aの試料加工室
2の支持台6にはゲート部となる位置を開口した
SiO2マスクで被覆したGaAs基板3を設置した。
The basic configuration of the apparatus used is roughly the same as that shown in FIG.
A GaAs substrate 3 covered with a SiO 2 mask was installed.

プラズマ室1にはガス導入管12よりエツチン
グガスとしてCl2ガスを供給してプラズマ発生さ
せ、ガス圧8×10-4Torr、イオン引き出し電極
の印加電圧500V、基板温度室温の条件下で5分
間ドライエツチングを行つた。
Cl 2 gas was supplied as an etching gas from the gas introduction tube 12 to the plasma chamber 1 to generate plasma, and the etching was carried out for 5 minutes under the conditions of a gas pressure of 8 × 10 -4 Torr, an applied voltage of 500 V to the ion extraction electrode, and a substrate temperature of room temperature. Dry etching was performed.

5分経過後、第4図aに示すように、支持台6
を180度回転させ、支持台の裏面を電極7と対向
させてイオンのGaAs基板の突入を中止させると
共にClラジカルの吸着堆積を行つた。反転して10
分経過後、厚さ約500Åの保護膜が基板表面に形
成された。
After 5 minutes, as shown in FIG.
was rotated 180 degrees, and the back surface of the support was placed to face the electrode 7 to stop the ions from entering the GaAs substrate and adsorb and deposit Cl radicals. Flip to 10
After a few minutes, a protective film with a thickness of about 500 Å was formed on the substrate surface.

次いで、基板3を真空度5×10-9Torrに保持
されている輸送管Cを通して基板処理装置Bの蒸
着室8内へ移動した。
Next, the substrate 3 was moved into the vapor deposition chamber 8 of the substrate processing apparatus B through the transport pipe C maintained at a vacuum level of 5×10 −9 Torr.

蒸着室15内では支持台の上方に加熱装置を設
置して、基板3を300℃で30分間加熱して保護膜
を除去し、続いて基板表面に真空蒸着により厚さ
1μmのAl膜を形成し、蒸着室より取り出し、基
板のSiマスク上に形成したAl膜はリフトオフに
より除去した。
In the deposition chamber 15, a heating device is installed above the support stand, and the substrate 3 is heated at 300°C for 30 minutes to remove the protective film, and then the thickness is deposited on the substrate surface by vacuum evaporation.
A 1 μm Al film was formed and taken out from the deposition chamber, and the Al film formed on the Si mask of the substrate was removed by lift-off.

上述のようにしてゲート部をエツチングにより
リセス構造とし、汚染、酸化などにより保護して
ゲート電極を形成した結果、ゲート電極のシヨツ
トキー接合の諸特性が向上した。
As a result of forming the gate electrode by etching the gate portion to form a recessed structure and protecting it from contamination, oxidation, etc. as described above, various characteristics of the Schottky junction of the gate electrode were improved.

(発明の効果) 以上、この発明によれば気密に接続した複数の
装置を用い、半導体基板を各装置間を輸送して加
工処理を行う方法において、半導体基板を各装置
間を輸送する際に半導体表面に放電プラズマ中の
塩素中性ラジカルを吸着、堆積させて保護膜とし
て用いることにより、輸送中の僅かな汚染、酸化
などまでが完全に防止され、形成されるデバイス
の特性が向上する。
(Effects of the Invention) As described above, according to the present invention, in a method for processing a semiconductor substrate by transporting the semiconductor substrate between the devices using a plurality of devices that are airtightly connected, when the semiconductor substrate is transported between the devices, By adsorbing and depositing chlorine neutral radicals in discharge plasma on the semiconductor surface and using it as a protective film, even slight contamination and oxidation during transportation can be completely prevented, improving the characteristics of the formed device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明を実施するための装置の概略
図、第2図はこの発明の工程を示す工程図、第3
図aは基板表面のエツチング処理を示す説明図、
第3図bは基板表面に保護膜が形成したときの説
明図、第4図はこの発明におけるプラズマ中のイ
オンの基板表面への突入を阻止し、中性ラジカル
のみを基板表面へ吸着させる方法を例示し、第4
図aは基板を支持台と共に反転させる方法、第4
図bはシヤツターを用いる方法、第4図cはプラ
ズマ室と試料加工室間に正電位に保持された電極
を設ける方法、第4図dは半導体基板を正電位に
保持させる方法、第4図eは偏向電極を用いた方
法の説明図、第5図は基板表面に形成された保護
膜を除去する方法を例示し、第5図aは基板の支
持台に加熱手段を内蔵する方法、第5図bは基板
の上部に加熱手段を配置する方法、第5図cはビ
ームの照射により除去する方法を示す説明図であ
る。 1……プラズマ室、2……試料加工室、3……
半導体基板、4……イオン、5……中性ラジカ
ル、5′……保護膜、6……支持台、7……電極、
8……蒸着室、A,B……基板処理装置、C……
輸送管。
Fig. 1 is a schematic diagram of an apparatus for carrying out this invention, Fig. 2 is a process diagram showing the steps of this invention, and Fig. 3 is a schematic diagram of an apparatus for carrying out this invention.
Figure a is an explanatory diagram showing the etching process on the substrate surface;
Figure 3b is an explanatory diagram when a protective film is formed on the substrate surface, and Figure 4 is a method according to the present invention for preventing ions in plasma from entering the substrate surface and adsorbing only neutral radicals to the substrate surface. For example, the fourth
Figure a shows the method of inverting the substrate together with the support, the fourth
Fig. 4b shows a method using a shutter, Fig. 4c shows a method of providing an electrode held at a positive potential between the plasma chamber and the sample processing chamber, Fig. 4d shows a method of holding the semiconductor substrate at a positive potential, Fig. 4 5e is an explanatory diagram of a method using a deflection electrode, FIG. 5 is an example of a method for removing a protective film formed on a substrate surface, FIG. FIG. 5b is an explanatory view showing a method of arranging a heating means on the top of the substrate, and FIG. 5c is an explanatory view showing a method of removing by irradiating a beam. 1...Plasma chamber, 2...Sample processing room, 3...
Semiconductor substrate, 4... Ion, 5... Neutral radical, 5'... Protective film, 6... Support base, 7... Electrode,
8... Vapor deposition chamber, A, B... Substrate processing equipment, C...
transport pipe.

Claims (1)

【特許請求の範囲】[Claims] 1 放電プラズマにより発生した塩素中性ラジカ
ルを250℃以下に保たれた半導体基板の表面に吸
着させて保護膜を形成するようにしたことを特徴
とする加工プロセス中の半導体基板の保護方法。
1. A method for protecting a semiconductor substrate during a processing process, characterized by forming a protective film by adsorbing neutral chlorine radicals generated by discharge plasma onto the surface of a semiconductor substrate maintained at 250°C or lower.
JP20642484A 1984-10-03 1984-10-03 Protecting method for semiconductor substrate in process Granted JPS6184834A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20642484A JPS6184834A (en) 1984-10-03 1984-10-03 Protecting method for semiconductor substrate in process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20642484A JPS6184834A (en) 1984-10-03 1984-10-03 Protecting method for semiconductor substrate in process

Publications (2)

Publication Number Publication Date
JPS6184834A JPS6184834A (en) 1986-04-30
JPH0365891B2 true JPH0365891B2 (en) 1991-10-15

Family

ID=16523143

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20642484A Granted JPS6184834A (en) 1984-10-03 1984-10-03 Protecting method for semiconductor substrate in process

Country Status (1)

Country Link
JP (1) JPS6184834A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01289121A (en) * 1988-05-16 1989-11-21 Nec Corp Digital etching process of iii-v compound semiconductor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5140766A (en) * 1974-10-02 1976-04-05 Nippon Electric Co 33v zokukagobutsuhandotaino hyomenshorihoho
JPS5757874A (en) * 1980-07-28 1982-04-07 Fairchild Camera Instr Co Plasma passivation technique for preventing erosion of plasma etched aluminum film after etcing treatment
JPS5961123A (en) * 1982-09-30 1984-04-07 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5140766A (en) * 1974-10-02 1976-04-05 Nippon Electric Co 33v zokukagobutsuhandotaino hyomenshorihoho
JPS5757874A (en) * 1980-07-28 1982-04-07 Fairchild Camera Instr Co Plasma passivation technique for preventing erosion of plasma etched aluminum film after etcing treatment
JPS5961123A (en) * 1982-09-30 1984-04-07 Fujitsu Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS6184834A (en) 1986-04-30

Similar Documents

Publication Publication Date Title
JPH07115062A (en) Method and device for manufacturing thin film
JPH04206719A (en) Apparatus and method for treating substrate
JPH0522379B2 (en)
JPH0365891B2 (en)
JP3394130B2 (en) Method for manufacturing organic electroluminescence element and apparatus for manufacturing organic electroluminescence element
US11575065B2 (en) Tuning of emission properties of quantum emission devices using strain-tuned piezoelectric template layers
JP4091288B2 (en) Processing method of processing object
JPH0542507B2 (en)
JP2694625B2 (en) Method for etching compound semiconductor substrate and method for manufacturing the same
JPH0239523A (en) Method of forming film on semiconductor substrate
JP2003115472A (en) Semiconductor device manufacturing method
JP2523558B2 (en) Processing method
JP2003172949A (en) Manufacturing method for array substrate for display device
JP2617935B2 (en) Atthing method
JPH09270404A (en) Treatment of substrate
JPH05283346A (en) Semiconductor manufacturing device
JPH02166729A (en) Metal depositing method
JPS6266629A (en) Forming method for thin film
JP2558765B2 (en) Method for manufacturing semiconductor device
JPH0461291A (en) Forming method for structure of compound semiconductor
JPH033251A (en) Sample holder
JP2998336B2 (en) Method for etching compound semiconductor and method for forming semiconductor structure
JPH02288333A (en) Method of forming pattern of compound semiconductor
JPH03195071A (en) Method of forming compound semiconductor structure
JPH10289910A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term