JPH0365015A - Abnormal input voltage detecting circuit - Google Patents

Abstract

PURPOSE:To prevent unnecessary detection of abnormality by resetting a counter every time when a specific pulse train memory responds to the rising or falling of a pulse in a pulse train and repeating the counting operation. CONSTITUTION:Input voltage A and CLK are inputted into a DFF 2 and Q output B and Q output C are outputted with delay of single clock. The output B and the CLK are fed to a DFF 3 and Q output D and Q output E are outputted with delay of single clock. The outputs C and D are fed to an AND gate 11 and a logical product is produced as an output F. Outputs B and E are fed to an AND gate 12 to produce a logical product as an output G. The outputs F, G are fed, as signals N, to the reset terminal of a counter 5 through an OR gate 13. The counter 5 produces an alarm if predetermined time, i.e., 20ms, elapses before the counter 5 is reset. When normal input voltage is provided, the counter 5 is reset every 10ms and the count is updated.

Description

[Detailed Description of the Invention] [Summary] Regarding an abnormality detection circuit for input voltage of an AC power source for equipment, a detection circuit that avoids unnecessary abnormality detection when detecting an abnormality by converting the input voltage into a pulse. The present invention aims to provide a pulse generation circuit that converts an input voltage of an AC power supply into pulses, a means for transmitting and storing the output pulses of the pulse generator circuit in synchronization with a predetermined balster IJft clock, and the memory. An input voltage abnormality detection circuit for an apparatus comprising a counter that is reset by an output signal from the means to start counting and detects a multi-failure depending on whether or not a next reset occurs within a predetermined time, comprising: the storage means; A second storage means connected in parallel, which transfers and stores the pulse train according to a clock, and a gate that takes the logical sum of the output signals of the two storage means, and the storage means for the predetermined pulse train The configuration is such that the counter is reset each time in response to either the rise or fall of a pulse in the pulse train, and the count is repeated.

[Industrial application field]

The present invention relates to an abnormality detection circuit for input voltage of an AC power source for equipment.

[Conventional technology]

Conventionally, in order to detect an abnormality in the input voltage of an AC power source that supplies power to electronic devices, a method of converting it into a pulse and checking the state during the rise of the pulse has been frequently used.

FIGS. 4(cL) to 4(a) are explanatory diagrams of an example of this method.

As shown in the configuration diagram in (a) of the same figure and the operating waveform diagram in (b) of the same figure, for example, a 50 Hz AC power source is branched and a known waveform shaping circuit (not shown) is used to generate the waveform A shown in (6) (■) of the same figure. Create a pulse waveform like this. With this waveform A as the input voltage,
Each input is input to a series two-stage D-type flip 70 tube (DF R2.5) driven by the clock CLK ((b) in the same figure) from the clock generator 1. That is, the input voltage At
- Q output B is input to the reset terminal of DFF2 and delayed by 1 clock [(6) ■ in the same figure] is input to the reset terminal of DFF 5, and Q output C is inputted to the reset terminal of DFF 5 and delayed by 1 clock [(Fig.
6) Output ■]. Outputs B and D of these DFF 2
The output C of F)' 3 is input into the AND circuit 4 to remove the logic term, and the output D [(b) (2) in the same figure] is input to the reset terminal of the counter 5 driven by the same CLK. As will be described later in FIG.
One cycle time of 20 mB is counted, and when the tolerance value α is exceeded, an alarm is generated.

Counter 5f shown in (6) ■ in the same figure: Reset signal ■
.

Since @ is generated in response to the rise of one cycle of the input voltage pulse, if the input voltage is normal, it is reset at 20% S cycle, so no alarm is generated. On the other hand, in the case of a power outage including a momentary interruption, a failure, etc., the reset signal after counting is not applied, so an abnormality is detected and an alarm is generated.

An object of the present invention is to provide a detection circuit as described above.

[Problem to be solved by the invention]

In the above configuration, for one cycle of normal waveform, the count @T = 2 is reset by the reset signal ■.
Since the signal 0 is generated within 00%S+α and the counter is reset by the signal @, no alarm is output.

However, in an actual AC power supply, when an unstable voltage condition occurs, for example when the input voltage level suddenly changes, the reset signal @ for the counter is delayed as shown in (6) in the same figure. F)(T'
>T), an alarm will be generated immediately. Although this is certainly abnormal, it can be recovered immediately and does not pose a problem.

Therefore, it is necessary to distinguish this from instantaneous interruptions or power outages of several tens of milliseconds or more, which are actually problematic.

An object of the present invention is to avoid unnecessary abnormality detection when detecting an abnormality by converting input voltage into pulses. a pulse generating circuit that converts an input voltage into pulses; a means for transmitting and storing a predetermined pulse train by a clock in synchronization with the output pulses of the pulse generating circuit; connected in parallel with the storage means, by means of an input voltage abnormality detection circuit of a device comprising a counter that detects an abnormality depending on whether or not the next reset occurs within a predetermined time after starting t; A second storage means that transfers and stores the pulse generator Il by a clock, and a gate that takes the logical interest of the output signals of the two storage means, and the storage means for the predetermined pulse train is configured to store the rising timing of the pulses in the pulse train. , falling and falling, the counter is reset each time and the count is repeated.

[For production]

The principle in Figure 1 i1i! As shown in the figure, in addition to the reset signal indicated by G in ■, which has the same configuration as the conventional one and is detected by the rising clock of the input voltage waveform A in ■, lfr also detects the falling clock in the input voltage waveform A in ■. ■F of the configuration that detects with a clock
Add the reset signal shown in .

As shown by H in ■, for example, when the ti value of the counter is 20m5, a reset (CE) is applied every time IQtx & and the count is updated.

As a result, even if there is a delay at the time of each pulse change, there is sufficient margin, no alarm is generated due to this cause, and instantaneous interruptions or power outages of several tens of al1 or more can be sufficiently detected.

〔Example〕

FIG. 2 is an explanatory diagram of the configuration of the #jAo embodiment of the present invention.

FIG. 5 is an operational waveform diagram of the embodiment.

In both figures, the difference from the conventional example in Figure 4 (,) is D.
The Q and Q outputs are taken from FF2.5, and these outputs are combined to create an AND circuit 11.12 and an OR circuit 13.
The point is that a reset signal is sent to the counter via the counter. The following will be explained in accordance with FIG. 2 and with reference to FIGS.

That is, input voltage A and CLKf are input into DFF2 for 1 clock 2! ! After the delay, Q output B and 4 output C are output [Fig. 3 ■ to ■]. On the other hand, this output B and CIX'tDFF
3 and after one clock delay, Q output D and 4 output E are output [Fig. 3 ■, ■]. The output C and the output Df are put into an AND circuit 11, and the result is a logical product and an output F'fc is output.
(Fig. ■)], and output B and output Et-AND circuit 12 to output the logical product and 9 output G (Ag3 Fig. ■). These outputs JF and G are sent to the counter as a signal H via the OR circuit 13t. Counter 5 outputs an alarm if the reset is not activated within a predetermined period of 20 s, for example.If the input voltage is normal, it will be reset approximately every 10 m, !i. In this case, even if there is a slight pulse -〇 fluctuation, there is enough margin, so an alarm will not be generated, and only in the case of a momentary interruption or power outage of tens of m8 or more, which is the problem in this invention. Generate an alarm.

In the above embodiment, the input voltage is converted into pulses and the state of one cycle of the pulse train is detected, but the state of multiple pulse trains may also be detected, and the count value of the counter in the box until the alarm occurs also takes one reset time. It can be set to an arbitrary time that is larger and has a margin.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an explanatory diagram of the configuration of the embodiment, Fig. 5 is an operation waveform diagram of the embodiment, and Fig. 4 (ω~(6
) is an explanatory diagram of a conventional example. In the figure, 1 is a clock generator, 2 and 3 are D-type flip-flops (DFF), 5 is a counter, 12 is an AND circuit, and 15 is an OR circuit. [Effects of the Invention] As described above, according to the present invention, when the input voltage of an AC power source is converted into pulses, the states of multiple pulse trains are detected, and an abnormality alarm is output, the rising edge of the pulse in the pulse train is The counter is reset in response to both rising and falling υ, and an alarm is output only when the counter has been counted by a total of am, which allows a margin for this one reset time. This ignores the pulse delay caused by level fluctuations, etc., which are not a normal problem, and the tens of m8 as mentioned above.
A stable abnormality detection circuit that responds only to problematic abnormalities such as V# disconnection and power outage is realized.

Claims (1)

[Scope of Claims] A pulse generation circuit that converts the input voltage of an AC power supply into pulses, means for transmitting and storing a predetermined pulse train by a clock in synchronization with the output pulses of the pulse generation circuit, and an output from the storage means. In an input voltage abnormality detection circuit of a device including a counter that is reset by a signal to start counting and detects an abnormality depending on whether or not the next reset occurs within a predetermined time, a second storage means that transfers and stores the pulses using a clock, and a gate that takes the logical sum of the output signals of the two storage means, and the storage means for the predetermined pulse train stores the rising and falling edges of the pulses in the pulse train. An input voltage abnormality detection circuit characterized in that the counter is reset each time in response to any occurrence and the count is repeated.