JPH0364076A - Transparent mold package - Google Patents
Transparent mold packageInfo
- Publication number
- JPH0364076A JPH0364076A JP1200650A JP20065089A JPH0364076A JP H0364076 A JPH0364076 A JP H0364076A JP 1200650 A JP1200650 A JP 1200650A JP 20065089 A JP20065089 A JP 20065089A JP H0364076 A JPH0364076 A JP H0364076A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- die
- recess
- chip
- transparent mold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 239000011347 resin Substances 0.000 claims abstract description 8
- 229920005989 resin Polymers 0.000 claims abstract description 8
- 238000000465 moulding Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 8
- 230000007257 malfunction Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical group C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000009291 secondary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Light Receiving Elements (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は光素子を有する透明モールドパ・１ケージに
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transparent mold package having an optical element.
第５図は従来の透明モールドパッケージの断面図、第６
図は第５図のダイパッドと外部リードフレームのみの斜
視図である。図において、（１）は半導体チップ、（２
）はダイボンド材、（３）はダイパッド、（４）は外部
リードフレーム、（５）は透明モールド樹脂、（６）は
ＡＵ線である。Figure 5 is a sectional view of a conventional transparent mold package, Figure 6 is a cross-sectional view of a conventional transparent mold package.
The figure is a perspective view of only the die pad and external lead frame of FIG. 5. In the figure, (1) is a semiconductor chip, (2
) is a die bonding material, (3) is a die pad, (4) is an external lead frame, (5) is a transparent mold resin, and (6) is an AU wire.
次に構造について説明する。Next, the structure will be explained.
ダイパ・ソド部（３）は半導体チップ＜１）上のポンデ
ィングパッドと外部リードフレーム（４）と高さが近く
なるように、第６図に示すいわゆるダイパッド沈めが施
こされている。このダイパ・ソド（３）上にダイボンド
材【２）により半導体チップ（１）がダイボンドされて
いる。この半導体チ゛１プ〈１）上のボンディングパ・
ソドと外部リードフレーム（４）とをＡｕ線（６）によ
りワイヤボンディングしている。そして、全体を透明モ
ールド樹脂（５）により包み込むようにパッケージジグ
している。The so-called die pad sinking shown in FIG. 6 is performed so that the die pad/sod portion (3) is close in height to the bonding pad on the semiconductor chip <1) and the external lead frame (4). A semiconductor chip (1) is die-bonded onto this die pad (3) using a die-bonding material (2). The bonding pad on this semiconductor chip (1)
The lead frame and the external lead frame (4) are wire-bonded using Au wire (6). Then, a package jig is carried out so that the whole is wrapped in transparent mold resin (5).
従来の透明モールドパッケージは以上のように構成され
ていたので光センサ部を除いてアルミ遮光されている表
向及びフレームで覆われた半導体チップ裏面からの光の
入射はない。しかし、半導体チ′ソプ側面の遮光は施こ
されていないため、光が半導体チップ内部に入射してし
まう。半導体チ・フプ内部に形成されたＰＮ接合部で、
この光の入射にょうリーク電流が発生し、センシティブ
な回路ではこのリーク電流によって誤動作してしまう。Since the conventional transparent mold package is constructed as described above, there is no light incident from the front surface which is shielded from aluminum except for the optical sensor section and the back surface of the semiconductor chip covered by the frame. However, since the side surface of the semiconductor chip is not shielded from light, light enters the inside of the semiconductor chip. A PN junction formed inside a semiconductor chip.
When this light is incident, a leakage current is generated, and sensitive circuits may malfunction due to this leakage current.
さらに、ＳＰＤ等のＰＡオーダでの電流で動作させてい
る領域に、このμＡオーダでも発生するリーク電流が生
じると、全く正常な動作が期待できなくなる。これら内
部回路の誤動作だけでなく、２次的なものとしてこれら
の誤動作を防ぐために、半導体チップ周辺には回路を構
成することができず、面積的にも不利となる。また、光
入射を防止する目的で第７図に示すように、ＩＣ（７）
の周囲を光センサ部を開けて、それ以外は遮光性のケー
スをかぶせて使用せねばならないなどの問題点を有して
いた。Furthermore, if a leakage current that occurs even on the μA order occurs in a region such as an SPD that is operated with a current on the PA order, normal operation cannot be expected at all. In order to prevent not only malfunctions of these internal circuits but also secondary malfunctions, circuits cannot be constructed around the semiconductor chip, which is disadvantageous in terms of area. In addition, as shown in Figure 7, for the purpose of preventing light incidence, an IC (7)
There were problems in that the optical sensor part had to be opened around the area and a light-shielding case had to be placed over the rest of the area.
この発明は上記のような問題点を解決するためになされ
たもので、側面を遮光することにより側面からの光入射
による内部回路の誤動作の生じない透明モールドパッケ
ージを得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a transparent mold package that prevents malfunction of internal circuits due to light incident from the sides by shielding the sides from light.
この発明に係る透明モールドパ・ソケージは、ダイパッ
ド部に半導体チップの大きさ程度のくぼみを設け、この
くぼみの中に半導体チップをダイボンドしたものである
。In the transparent molded package according to the present invention, a recess approximately the size of a semiconductor chip is provided in the die pad portion, and a semiconductor chip is die-bonded into the recess.
この発明における透明モールドパッケージは。 The transparent mold package in this invention is.
半導体チップをダイパ・ソド部に設けたくぼみの中にダ
イボンドすることにより、半導体チップ側面及び裏面が
遮光されるため、アルミ遮光がほどこされていない半導
体チップ表面の光センサ部以外での半導体チップ内部へ
の光入射がなくなるため、その光によって生じる内部回
路の誤動作がなくなるとともに、ダイパッドの沈めの効
果も得られるため、ワイヤボンディングが確実になる。By die-bonding the semiconductor chip into the recess provided in the dieper/sodium part, the side and back surfaces of the semiconductor chip are shielded from light, so the inside of the semiconductor chip is exposed to areas other than the light sensor part on the surface of the semiconductor chip that is not shielded from aluminum light. Since no light is incident on the wire, malfunctions of internal circuits caused by the light are eliminated, and the effect of sinking the die pad is also obtained, making wire bonding more reliable.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例である透明モールドパッケ
ージの断面図、第２図はダイパッドと外部リードフレー
ムのみの斜視図である。図において、（１）は半導体チ
ップ、（２）はダイボンド材、（３）はダイパッド部（
４）は外部リードフレーム、（５）は透明モールド樹脂
、（６）はＡｕ線である。FIG. 1 is a sectional view of a transparent mold package which is an embodiment of the present invention, and FIG. 2 is a perspective view of only a die pad and an external lead frame. In the figure, (1) is the semiconductor chip, (2) is the die bond material, and (3) is the die pad part (
4) is an external lead frame, (5) is a transparent mold resin, and (6) is an Au wire.
次に構造について説明する。Next, the structure will be explained.
ダイパッド部３）には半導体チップ（１）とのダイボン
ド部に、半導体チップ（１）よりわずかに大きいくぼみ
を設けて、このくぼみ内に半導体チ゛ソプ（１）をダイ
ボンドし、半導体チップ（１）の側面及び裏面はこのく
ぼみによって囲まれている。そして、半導体チップ（１
）上のボンディングパ・ソドと、このポンディングパッ
ド部と同程度の高さに設けられた外部リードフレーム（
４）とをＡｕ線（６）によってワイヤボンドし、全体を
透明モールド樹脂（５）により包み込むようにして構成
されている。A recess slightly larger than the semiconductor chip (1) is provided in the die pad part 3) at the die bonding part with the semiconductor chip (1), and the semiconductor chip (1) is die-bonded into this recess. The sides and back are surrounded by this depression. Then, the semiconductor chip (1
) on the bonding pad and the external lead frame (
4) are wire-bonded with an Au wire (6), and the entire body is wrapped in a transparent mold resin (5).
次に、このパッケージの組立工程の一実施例ヲ第３図に
示す。Next, an example of the assembly process of this package is shown in FIG.
第３図はこの発明の一実施例である透明モールドパッケ
ージの組立工程フローの側面図である。FIG. 3 is a side view of an assembly process flow for a transparent mold package according to an embodiment of the present invention.
まず、ダイパッド（３）にパンチングにより半導体チ゛
ソブ（１）よりわずかに大きいめのくぼみを設ける（第
ａ図（ｂ））。次に、そのくぼみ底部にダイボンド材（
２）により半導体チップ（１）とダイパッド（３）との
接着固定を行なう（第３図（Ｃ））。さらに、 Ａｕ線
（６）により半導体チップ（１）上のポンディングパッ
ドと外部リードフレーム（４）とのワイヤボンドを行な
ったあと、最後に、全体を透明モールド樹脂（５）によ
り包み込むように封止する（第３図（ｄ））。First, a recess slightly larger than the semiconductor die pad (1) is formed in the die pad (3) by punching (Fig. a (b)). Next, place the die bond material (
2), the semiconductor chip (1) and the die pad (3) are bonded and fixed (FIG. 3(C)). Furthermore, after wire bonding is performed between the bonding pads on the semiconductor chip (1) and the external lead frame (4) using Au wires (6), the whole is wrapped and sealed with transparent mold resin (5). (Fig. 3(d)).
第４図は第３図の透明モールドパッケージの最終工程に
おける透明斜視図である。FIG. 4 is a transparent perspective view of the transparent mold package of FIG. 3 in the final step.
なお、上記実施例ではダイボンド材（２）をダイパッド
（３）のくぼみ底面にのみ付着した場合を示しているが
、チップ側面にもダイボンド材（２）を充填して構成し
てもよい。Although the above embodiment shows the case where the die bonding material (2) is attached only to the bottom of the recess of the die pad (3), the die bonding material (2) may also be filled on the side surface of the chip.
以上のようにこの発明によれば、半導体チップ全体ヲ、
ダイパッド部に設けたくぼみ内に入れるため、くぼみ側
面により半導体チップ側前の遮光が可能となり、半導体
チップ上の光センサ部以外のアルＺ３ｍ光及びダイパッ
ドによる半導体チップ裏面の遮光と合わせて、不必要な
光の入射を防ぐことができ、その光入射によって生じる
内部回路の誤動作−を防止することができる。さらに、
半導体チ・１プ上のダイパッド部と外部リード部が同じ
高さに設けられているので、ワイヤボンディングが確実
に行なえ、それらの位置の相違から生じるワイヤと半導
体チ′ソプとの接触や、Ａｕ線切れなどの不具合もなく
なる。As described above, according to the present invention, the entire semiconductor chip is
Since it is inserted into the recess provided in the die pad, the side surface of the recess can block light in front of the semiconductor chip side, and together with the Al Z3m light other than the light sensor part on the semiconductor chip and the back side of the semiconductor chip blocked by the die pad, unnecessary It is possible to prevent the incidence of harmful light, and it is possible to prevent malfunctions of internal circuits caused by the incidence of light. moreover,
Since the die pad part and the external lead part on the semiconductor chip 1 are provided at the same height, wire bonding can be performed reliably, and contact between the wire and the semiconductor chip caused by the difference in their positions, and the Au Problems such as line breaks are also eliminated.
さらに２次的な効果として、半導体チップ周辺部にも光
入射による誤動作を心配することなく構成でき、半導体
チップ面積を小さくでき、また、光入射防止用として、
ＩＣ全体を覆っていた遮光性プラスチックケース等が
不要となり、部品点数の低減が可能で、引い′てはコス
ト低減につながる。Furthermore, as a secondary effect, the peripheral area of the semiconductor chip can be configured without worrying about malfunctions due to light incidence, the semiconductor chip area can be reduced, and it can also be used to prevent light incidence.
The light-shielding plastic case that used to cover the entire IC is no longer necessary, making it possible to reduce the number of parts, which ultimately leads to lower costs.
第１図はこの発明の一実施例による透明モールドパ・ソ
ケージを示す断面図、第２図は第１図のダイパッドと外
部リードフレームのみの斜視図、第３図（紘）〜（ｄ）
はこの発明の一実施例による透明モールドパッケージの
組立工程フローを示す側面図、第４図は第３図の透明モ
ールドパ・ソケージの最終工程における透明斜視図、第
５図は従来の透明モールドパッケージを示す断面図、第
６図は第５図のダイパ・ソドと外部リードフレームのみ
の斜視図、第７図は従来のＩＣにおける光入射防止用プ
ラスチ・ソクケースの断面図である。
図において、（１）は半導体チ゛ソプ、（２）はダイボ
ンド材、（３）はダイパ・ソド、（４）は外部リードフ
レーム、（５）は透明モールド樹脂、（６）はＡｕ線を
示す。
なお１図中、同一符号は同一 または相当部分を示す。Fig. 1 is a sectional view showing a transparent molded package according to an embodiment of the present invention, Fig. 2 is a perspective view of only the die pad and external lead frame shown in Fig. 1, and Figs. 3 (Hiro) to (d).
4 is a side view showing the assembly process flow of a transparent mold package according to an embodiment of the present invention, FIG. 4 is a transparent perspective view of the final process of the transparent mold package shown in FIG. 3, and FIG. 5 is a diagram showing a conventional transparent mold package. 6 is a perspective view of only the dieper rod and external lead frame shown in FIG. 5, and FIG. 7 is a sectional view of a plastic sock case for preventing light incidence in a conventional IC. In the figure, (1) is a semiconductor chip, (2) is a die bonding material, (3) is a die bonding material, (4) is an external lead frame, (5) is a transparent mold resin, and (6) is an Au wire. In Figure 1, the same symbols indicate the same or equivalent parts.
Claims (1)
チップとほぼ等しい大きさのくぼみを設け、このくぼみ
内に前記半導体チップをダイボンドし、前記半導体チッ
プ及び前記リードフレームを透明樹脂により包み込むよ
うにして形成したことを特徴とする透明モールドパッケ
ージ。A recess approximately the same size as the semiconductor chip including the light receiving element is provided in the die pad portion of the lead frame, the semiconductor chip is die-bonded into the recess, and the semiconductor chip and the lead frame are wrapped in a transparent resin. A transparent mold package characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1200650A JPH0364076A (en) | 1989-08-02 | 1989-08-02 | Transparent mold package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1200650A JPH0364076A (en) | 1989-08-02 | 1989-08-02 | Transparent mold package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0364076A true JPH0364076A (en) | 1991-03-19 |
Family
ID=16427931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1200650A Pending JPH0364076A (en) | 1989-08-02 | 1989-08-02 | Transparent mold package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0364076A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008097971A (en) * | 2006-10-11 | 2008-04-24 | Mt Picture Display Co Ltd | Imaging device |
| JP2008534383A (en) * | 2005-04-05 | 2008-08-28 | ソシエテ ド テクノロジー ミシュラン | System for locking the mounting ring to the vehicle hub |
| JP2010509759A (en) * | 2006-11-09 | 2010-03-25 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Apparatus for passivating components and method for manufacturing the apparatus |
-
1989
- 1989-08-02 JP JP1200650A patent/JPH0364076A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008534383A (en) * | 2005-04-05 | 2008-08-28 | ソシエテ ド テクノロジー ミシュラン | System for locking the mounting ring to the vehicle hub |
| JP2008097971A (en) * | 2006-10-11 | 2008-04-24 | Mt Picture Display Co Ltd | Imaging device |
| JP2010509759A (en) * | 2006-11-09 | 2010-03-25 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Apparatus for passivating components and method for manufacturing the apparatus |
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