JPH0362602A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0362602A JPH0362602A JP19821789A JP19821789A JPH0362602A JP H0362602 A JPH0362602 A JP H0362602A JP 19821789 A JP19821789 A JP 19821789A JP 19821789 A JP19821789 A JP 19821789A JP H0362602 A JPH0362602 A JP H0362602A
- Authority
- JP
- Japan
- Prior art keywords
- output
- chips
- matching circuit
- package
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 230000000694 effects Effects 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は超高周波帯で動作する半導体装置に利用され、
特に、高出力GaAsMfESF8T (GaAs シ
ョットキ接合型電界効果トランジスタ)および高出力バ
イブリッドICに関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is applied to a semiconductor device operating in an ultra-high frequency band,
In particular, it relates to high-power GaAsMfESF8T (GaAs Schottky junction field effect transistor) and high-power hybrid ICs.
本発明は、パッケージ上に二つの半導体チップを搭載し
並列動作を行わせる高周波高出力用の半導体装置におい
て、
前記二つの半導体チップを中心線が重ならないよう互い
に離れた位置に搭載し、かつ、入力側整金回路および出
力側整合回路を、それぞれ入力側子および出力端子に対
する両半導体チップ間の位相差が、信号の波長をλgと
してλg/4および−λg/4になるように設けること
により、寸法の大きな半導体チップの搭載を可能とし、
高出力特性の向上を図ったものである。The present invention provides a high-frequency, high-output semiconductor device in which two semiconductor chips are mounted on a package and operated in parallel, in which the two semiconductor chips are mounted at positions apart from each other so that their center lines do not overlap, and By providing the input-side matching circuit and the output-side matching circuit so that the phase difference between both semiconductor chips with respect to the input side terminal and the output terminal, respectively, is λg/4 and -λg/4, where the signal wavelength is λg. , making it possible to mount large semiconductor chips,
This is aimed at improving high output characteristics.
従来、高出力GaAsMESFETおよび高出力バイブ
リッドICの終端部においては、素子の高出力化を図る
ため、第3図に示すように、2個のGaAsMESFE
Tチップを並列動作させる構成をとる。この場合、2個
のFETチップ4aおよび4bは半導体チップを搭載す
るパッケージ1の入力側子6もしくは出力端子7から同
位相すなわち同一寸法の位置に置かれていた。なお、第
3図において、2および3はそれぞれ3102基板上に
形成されたストリップ線からなる50Ωの入力側整合回
路および出力側整合回路である。Conventionally, in the terminal section of high-power GaAs MESFETs and high-power hybrid ICs, two GaAs MESFETs were used as shown in Figure 3 in order to increase the output of the device.
The configuration is such that T chips operate in parallel. In this case, the two FET chips 4a and 4b were placed at the same phase, that is, at the same size, from the input terminal 6 or output terminal 7 of the package 1 on which the semiconductor chip is mounted. In FIG. 3, 2 and 3 are a 50Ω input-side matching circuit and an output-side matching circuit, respectively, which are formed on a 3102 substrate and are made of strip lines.
前述した従来の半導体装置の構成においては、一つのF
ETチップ4aまたは4bの横幅寸法は、第3図に示す
ように、パッケージ1の幅のAが限界となる。In the configuration of the conventional semiconductor device described above, one F
As shown in FIG. 3, the width A of the package 1 is the limit for the width of the ET chip 4a or 4b.
従って、素子の高出力化を図るため個々のGaAsME
SFETのゲート幅を増加させるにつれて大型なパッケ
ージが必要となる。パッケージのTEIIOモードの共
振周波数f、は、パッケージ内寸の横幅をa1マイクロ
波伝送方向幅をbとした場合、で決定されるため、パッ
ケージを大型化するにつれ、使用可能周波数が低下して
くる。a=9.5mm。Therefore, in order to increase the output of the device, individual GaAsME
Increasing the gate width of SFETs requires larger packages. The resonant frequency f of the TEIIO mode of the package is determined by where the width of the package internal dimension is a1 and the width in the microwave transmission direction is b, so as the package size increases, the usable frequency decreases. . a=9.5mm.
b=8.9[[1I11のパッケージにおいては、安全
率30%を見込むとf r ’16.5GHzとなり、
半導体搭載時の組立難易性まで考慮した場合、Ku帯で
使用可能な本パッケージでも、ゲート幅4mm以上のG
aAsMESFETチップの搭載は不可能となり、素子
の高出力化に限界を生じる問題点があった。b = 8.9[[In the 1I11 package, assuming a safety factor of 30%, f r '16.5GHz,
Considering the difficulty of assembly when mounting a semiconductor, even with this package that can be used in the Ku band, G with a gate width of 4 mm or more
It became impossible to mount an aAs MESFET chip, and there was a problem that there was a limit to increasing the output of the element.
本発明の目的は、前記の問題点を解消することにより、
小形なパッケージを用いて高出力が得られる半導体装置
を提供することにある。The purpose of the present invention is to solve the above-mentioned problems.
An object of the present invention is to provide a semiconductor device that can obtain high output using a small package.
本発明は、入力側子および出力端子を有するパッケージ
と、このパッケージ上に搭載された二つの半導体チップ
と、これら二つの半導体チップの入力側および出力側と
前記入力側子および出力端子との間にそれぞれ設けられ
た入力側整合回路および出力側整合回路とを備えた半導
体装置において、二つの前記半導体チップはそれぞれ前
記入力側子および前記出力端子からの距離が異なる位置
に搭載され、かつ、前記入力側整合回路および前記出力
側整合回路は、それぞれ前記入力側子および前記出力端
子に対する前記二つの半導体チップ間の位相差が、信号
波長をλgとしてλg/4および−λg/4であるよう
に設けられたことを特徴とする。The present invention provides a package having an input side child and an output terminal, two semiconductor chips mounted on this package, and a connection between the input side and output side of these two semiconductor chips and the input side child and the output terminal. In the semiconductor device, the two semiconductor chips are mounted at different distances from the input terminal and the output terminal, respectively, and The input side matching circuit and the output side matching circuit are configured such that phase differences between the two semiconductor chips with respect to the input side terminal and the output terminal are λg/4 and −λg/4, respectively, where the signal wavelength is λg. It is characterized by the fact that it is provided.
半導体チップは入力側子および出力端子からの距離が互
いに異なる位置、すなわち両半導体チップの中心線がず
れて互いに離れて搭載されるので、パッケージの幅寸法
のA以上のゲート幅のFETチップを搭載できる。かつ
、入力側整合回路および出力側整合回路での両チップの
位相差はλg/4および−λg/4であるので、入出力
側整合回路で生じた位相差は相殺され、整合条件を満足
するよう設定されるので、高周波特性を十分に維持しつ
つ出力を増すことができる。Since the semiconductor chips are mounted at different distances from the input side terminal and the output terminal, that is, the center lines of both semiconductor chips are shifted and separated from each other, it is possible to mount an FET chip with a gate width equal to or larger than the package width dimension A. can. In addition, the phase difference between both chips in the input-side matching circuit and the output-side matching circuit is λg/4 and -λg/4, so the phase difference generated in the input-output side matching circuit is canceled out and the matching condition is satisfied. Therefore, the output can be increased while sufficiently maintaining high frequency characteristics.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
第1図は本発明の一実施例の要部を示す平面図で、パッ
ケージ内部の部品配置を示す。また、第2図はその等価
回路図である。FIG. 1 is a plan view showing the main parts of an embodiment of the present invention, showing the arrangement of parts inside the package. Moreover, FIG. 2 is an equivalent circuit diagram thereof.
本実施例は、入力側子6および出力端子7を有するアル
ミナ基板からなるパッケージ1と、このパッケージ1上
に搭載された二つの半導体チップとしてのGaAsMI
ESFBTからなるFETチップ5aおよび5bと、F
ETチップ5aおよび5bの入力側および出力側と入力
側子6および出力端子7との間のアルミナ基板上にスト
リップ線路として、それぞれ設けられた入力側整合回路
2aおよび出力側整合回路3aとを備えた半導体装置に
おいて、本発明の特徴とするところの、FETチップ5
aおよび5bはそれぞれ入力側子6および出力端子7か
らの距離が異なる位置、すなわち、両チップの間隔がl
になるように搭載され、かつ、入力側整合回路2aおよ
び出力側整合回路3aは、それぞれ入力側子6および出
力端子7に対するFETチップ5aと5b間の位相差が
、信号の波長をλgとしてλg/4および一λg/4で
あるように設けられる。This embodiment includes a package 1 made of an alumina substrate having an input terminal 6 and an output terminal 7, and two GaAsMI semiconductor chips mounted on this package 1.
FET chips 5a and 5b made of ESFBT, and FET chips 5a and 5b made of ESFBT;
An input side matching circuit 2a and an output side matching circuit 3a are provided as strip lines on an alumina substrate between the input side and output side of the ET chips 5a and 5b and the input side terminal 6 and the output terminal 7, respectively. In the semiconductor device, which is a feature of the present invention, the FET chip 5
a and 5b are located at different distances from the input terminal 6 and the output terminal 7, respectively, that is, the distance between both chips is l.
The input side matching circuit 2a and the output side matching circuit 3a are mounted so that the phase difference between the FET chips 5a and 5b with respect to the input side terminal 6 and the output terminal 7, respectively, is λg, where the signal wavelength is λg. /4 and -λg/4.
次に、第2図を用いて本実施例の動作について説明する
。FETチップ5aと5b間の位相差が入力側でλg/
4、出力側で−λg/4になるよう位置させることによ
り、FETチップ5aおよび5bの入力側で反射された
波は第2図A点でλg/2の位相差を生じるため互いに
相殺され、FETチップ5aおよび5bの整合状態によ
らず素子外部から見たインピーダンスは良好なリターン
ロスを得ることが可能となる。しかも、FETチップ5
aおよび5bはそのゲート幅がパッケージ1の幅寸法の
2よりも大きいものを搭載でき、寸法の小さいパッケー
ジを用いて高周波高出力の半導体装置を得ることができ
る。Next, the operation of this embodiment will be explained using FIG. 2. The phase difference between FET chips 5a and 5b is λg/
4. By positioning the FET chips 5a and 5b so that the angle is -λg/4 on the output side, the waves reflected at the input sides of FET chips 5a and 5b produce a phase difference of λg/2 at point A in Fig. 2, so they cancel each other out. Regardless of the matching state of the FET chips 5a and 5b, it is possible to obtain a good impedance return loss when viewed from the outside of the element. Moreover, FET chip 5
A and 5b can be mounted with gate widths larger than 2 of the width dimension of package 1, and a semiconductor device with high frequency and high output can be obtained using a package with small dimensions.
以上説明したように、本発明によれば、高い周波数まで
使用可能な小形な半導体用パッケージを用いた高周波高
出力半導体装置を実現することができ、その効果は大で
ある。As described above, according to the present invention, it is possible to realize a high frequency, high power semiconductor device using a small semiconductor package that can be used up to high frequencies, and the effects thereof are significant.
第1図は本発明の一実施例を示す平面図。
第2図はその等価回路図。
第30図は従来例を示す平面図。
1・・・パッケージ、2.2a・・・入力側整合回路、
3.3a−出力側整合回路、4a、4b、5a、5b・
・・FETチップ、6・・・入力側子、7・・・出力端
子。
1:パ・ノγ−ン
2q:入1′J使j堅合口巧
3q:出n燭整合B路
5a、5b:FET+7プ
6:入ねS−+
7:出月堝吾
1:バ・ノブーン
2;人肉イ則髭合日暦
3:出力)則竪合日斉5
4a、4b: F E T ’r、iプロ:λ力堝千
7:出力隔子
従i!−例の溝底
旨 3 図FIG. 1 is a plan view showing one embodiment of the present invention. Figure 2 is its equivalent circuit diagram. FIG. 30 is a plan view showing a conventional example. 1... Package, 2.2a... Input side matching circuit,
3.3a-Output side matching circuit, 4a, 4b, 5a, 5b・
...FET chip, 6...input side child, 7...output terminal. 1: Pa-no-γ-n 2q: Input 1'J Tsuji Ken Aiguchi Takumi 3q: Out-n candle matching B path 5a, 5b: FET+7 pu 6: Input S-+ 7: Dezuki Gogo 1: B- Noboon 2; human flesh i rule beige match day calendar 3: output) rule 竫諺合日match 5 4a, 4b: F E T 'r, i pro: λ 力堝千 7: output distance separation i! -Example groove bottom effect 3 figure
Claims (1)
入力端子および出力端子との間にそれぞれ設けられた入
力側整合回路および出力側整合回路と を備えた半導体装置において、 二つの前記半導体チップはそれぞれ前記入力端子および
前記出力端子からの距離が異なる位置に搭載され、 かつ、前記入力側整合回路および前記出力側整合回路は
、それぞれ前記入力端子および前記出力端子に対する前
記二つの半導体チップ間の位相差が、信号の波長をλg
として λg/4 および −λg/4 であるように設けられた ことを特徴とする半導体装置。1. A package having an input terminal and an output terminal, two semiconductor chips mounted on this package, and input terminals provided between the input and output sides of these two semiconductor chips and the input and output terminals, respectively. In a semiconductor device including a side matching circuit and an output side matching circuit, the two semiconductor chips are mounted at different distances from the input terminal and the output terminal, and the input side matching circuit and the output side The side matching circuit is arranged so that the phase difference between the two semiconductor chips with respect to the input terminal and the output terminal respectively changes the wavelength of the signal by λg.
λg/4 and -λg/4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19821789A JPH0362602A (en) | 1989-07-31 | 1989-07-31 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19821789A JPH0362602A (en) | 1989-07-31 | 1989-07-31 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0362602A true JPH0362602A (en) | 1991-03-18 |
Family
ID=16387447
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19821789A Pending JPH0362602A (en) | 1989-07-31 | 1989-07-31 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0362602A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10749491B2 (en) | 2015-06-24 | 2020-08-18 | Epcos Ag | Inductive component for a bus bar |
-
1989
- 1989-07-31 JP JP19821789A patent/JPH0362602A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10749491B2 (en) | 2015-06-24 | 2020-08-18 | Epcos Ag | Inductive component for a bus bar |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0798782B1 (en) | Microwave circuit package | |
US5698469A (en) | Method of making a hybrid circuit with a chip having active devices with extra-chip interconnections | |
AU711010B2 (en) | Circuit structure having a flip-mounted matrix of devices | |
US5832376A (en) | Coplanar mixer assembly | |
JP2000500310A (en) | Transition from slotline to coplanar waveguide | |
US6285269B1 (en) | High-frequency semiconductor device having microwave transmission line being formed by a gate electrode source electrode and a dielectric layer in between | |
JP2001185966A (en) | Microwave power amplifier | |
JPH0362602A (en) | Semiconductor device | |
EP0102686B1 (en) | Device for distributing and/or combining microwave electric power | |
US5889297A (en) | High frequency semiconductor device with slots | |
US6100554A (en) | High-frequency semiconductor device | |
GB2255463A (en) | High frequency fet amplifier with harmonic processing | |
JP2001094012A (en) | Semiconductor chip mounting substrate and high- frequency device | |
US20230411316A1 (en) | Doherty amplifier | |
US20230140451A1 (en) | Amplifier device packages incorporating internal couplers | |
JPH0817291B2 (en) | Microwave circuit | |
US10742171B2 (en) | Nested microstrip system and method | |
JPS6322725Y2 (en) | ||
AU694066C (en) | Method for making a circuit structure having a flip-mounted matrix of devices | |
CA2236999C (en) | Circuit structure having a flip-mounted matrix of devices | |
JPH04326201A (en) | Semiconductor device | |
JPS63133701A (en) | Microwave semiconductor device | |
JPH0269002A (en) | Microwave and millimeter wave accumulating equipment | |
JPH04288714A (en) | Bias circuit for high output amplifier | |
JPH03123202A (en) | Field effect transistor |