JPH04288714A - Bias circuit for high output amplifier - Google Patents

Abstract

PURPOSE:To impress the large current of bias to an amplifier without affecting high frequency signals by providing a power distributor/synthesizer equipped with a high frequency terminator and a capacitor for cutting direct current. CONSTITUTION:At an isolation port 13d of a power distributor/synthesizer 13, a high frequency terminator 21 composed of a transmission line 19, which is connected to this port 13d, and a radio wave absorber 20 arranged above or under the transmission line 19 is provided, and a capacitor 22 for cutting direct current is provided at an output port 13c. The direct current bias from a direct current bias source 18 is inputted from the transmission line 19 to the power distributor/synthesizer 13 and transmitted through the power distributor/synthesizer 13 to respective high frequency amplifiers 1 and 1'. At such a time, since no direct current bias appears at the output port 13s and an impedance observed from the isolation port 13d of the power distributor/ synthesizer 13 is a characteristic impedance, high frequency outputs from the respective high frequency amplifiers 1 and 1' are synthesized and outputted from the output port 13c.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to bias circuits for high power amplifiers. Generally, when configuring a microwave band high-power amplifier provided on the transmitting side of a wireless device, a bias circuit for applying a DC bias to the amplification element is required.

0002

2. Description of the Related Art FIG. 8 is a circuit diagram of a conventional balanced high-output amplifier. As shown in FIG. High frequency signal line 2 on each input side of 1 and 1'
, 2' are connected to a direct current (DC) bias circuit, and a DC bias circuit is connected to each output side high frequency signal line 3, 3'.

That is, on the input side, each high frequency signal line 2, 2' is connected to an open stub via a high impedance line 4, 4' as a bias line having a line length of 1/4 wavelength (λg). 6, 6' are connected to each open stub 6, 6', and a power supply line 8, 8' as a DC bias source is connected to each open stub 6, 6', and on the output side, each high frequency signal line 3, 3' are connected to open stubs 7, 7' via high impedance lines 5, 5' as bias lines with a line length of 1/4 wavelength (λg), and each open stub 7, 7' are connected to power supply lines 9 and 9' as DC bias sources.

[0004] The high frequency signal lines 2 and 2' on each input side are connected to two ports of a power distribution combiner 12 having four ports via DC cut capacitors 10 and 10', and each output The side high-frequency signal lines 3 and 3' are also connected to two ports of a power distribution/synthesizer 13 having four ports via DC cut capacitors 11 and 11'.

Furthermore, a 50Ω terminator 14 is connected to one of the remaining two ports of the power distributor/combiner 12, and a high frequency signal is inputted from the other of the remaining two ports of the power distributor/combiner 12. It has become so.

Furthermore, a 50Ω terminator 15 is connected to one of the remaining two ports of the power divider/combiner 13, and a high frequency signal is output from the other of the remaining two ports of the power divider/combiner 13. It has become so.

[0007] With such a configuration, the input high frequency signal is divided in power by the power distribution combiner 12 and distributed to each FE.
After high frequency amplification at T1, 1', power distribution combiner 1
3, the power is combined and output, but at this time, the power line 8
, 8'; 9, 9' is supplied to the FET via high impedance lines 4, 4'; 5, 5'.
1 and 1', each FET 1 and 1' is biased.

[0008]

[Problem to be Solved by the Invention] In recent years, with the increase in the output of devices, it has become necessary to flow a large current into the bias circuit on the output side of the device, but the conventional bias circuit for high-output amplifiers described above , the bias line must have high impedance to eliminate its influence on high-frequency signals,
For this reason, they are made as thin as possible, so only a limited amount of current can flow through them. Furthermore, if the line width is widened to increase the current, high frequency signals will be adversely affected.

Therefore, as shown in FIGS. 9 and 10, a wire with approximately the same width as the high impedance lines 4, 4' (5, 5') is placed on the high impedance lines 4, 4' (5, 5'). There are some devices in which the copper wires 16 (16'), 17 (17'), etc. are bent into the same shape and soldered, etc., so that a large current can flow through them, but this complicates the assembly work.

The present invention was devised in view of the above-mentioned problems, and provides a bias circuit for a high-output amplifier that is capable of applying a large current bias to an amplification element without affecting high-frequency signals. The purpose is to

[0011]

[Means for Solving the Problems] FIG. 1 is a circuit diagram for explaining the principle of the present invention. As shown in FIG. 1, the present invention includes at least two high frequency amplifiers 1, 1' and , at least two input ports 13a receiving outputs from these high frequency amplifiers 1 and 1', respectively;
13b, an output port 13c for combining the outputs of high frequency amplifiers 1 and 1', and an isolation port 13d connected to a DC bias source 18, and these ports are connected in a DC manner. It has 13.

Further, the isolation port 13d of the power distribution combiner 13 has a transmission line 19 connected to the isolation port 13d, and a transmission line 19 connected to the isolation port 13d.
A high frequency terminator 21 consisting of a radio wave absorber 20 disposed above or below 9 is provided.

Furthermore, the output port 13c of the power distribution/synthesizer 13 is provided with a DC cut capacitor 22 (the above is the constituent feature of claim 1).

Furthermore, in the bias circuit for a high-power amplifier of the present invention, as shown by the chain line in FIG. 1, the transmission line 19 constituting the high-frequency terminator 21 is extended, and the extended end is
A terminator 24 is connected via a DC cut capacitor 23 (claim 2).

[0015]

[Operation] The bias circuit for high output amplifier of the present invention (
In claim 1), the DC bias supplied from the DC bias source 18 is inputted from the transmission line 19 to the power distribution/combiner 13 through the isolation port 13d of the power distribution/combiner 13. is applied to each high frequency amplifier 1, 1'.

At this time, since a DC cut capacitor 22 is provided at the output port 13c of the power distribution/combiner 13, the above DC bias is applied to the power distribution/combiner 13.
It never comes out to the output port 13c.

Furthermore, due to the radio wave absorber 20 disposed above or below the transmission line 19, the impedance seen from the isolation port 13d of the power distribution combiner 13 becomes a characteristic impedance, so that each high frequency amplifier 1 , 1' is sent to the power distribution combiner 1.
3 and output port 13 of the power distribution combiner 13.
Output from c.

Furthermore, in the bias circuit for a high-power amplifier of the present invention (claim 2), a terminator 24 is connected to the extended end of the transmission line 19 constituting the high-frequency terminator 21 via a DC cut capacitor 23. Since it is connected, the impedance is sufficiently low in the low frequency range. This provides sufficient termination in the low frequency range.

[0019]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(a) Description of the first embodiment FIG. 2 is a circuit diagram showing the first embodiment of the present invention, and FIG. 3 is a sectional view of the high frequency terminator portion. In the balanced high output amplifier according to this embodiment,
First, a DC bias circuit is connected to high frequency signal lines 2 and 2' on the input sides of two FETs (high frequency amplifiers) 1 and 1'. That is, each high frequency signal line 2, 2' has a 1/
The open stub 6
, 6' are connected to the open stubs 6, 6', and power lines 8, 8' as DC bias sources are connected to each open stub 6, 6'.

Furthermore, the high frequency signal lines 2, 2' on each input side
is connected to two ports of a power distribution combiner 12 having four ports via DC cut capacitors 10 and 10', and one of the remaining two ports of this power distribution combiner 12 is connected to a 50Ω A terminator 14 is connected, and a high frequency signal is input from the other of the remaining two ports of the power distribution/combiner 12.

By the way, the high frequency signal lines 3, 3 on each output side
' are connected to two input ports 13a and 13b of the power distribution/synthesizer 13, which also has four ports.

Here, this power distribution/synthesizer 13 has two input ports 13a and 13b that receive outputs from two FETs 1 and 1', respectively, and also has two input ports 13a and 13b that receive outputs from two FETs 1 and 1', respectively.
It has an output port 13c for synthesizing the outputs of , and an isolation port 13d, and these ports are connected in a direct current manner.

[0024] Furthermore, a high frequency 1 terminator 21 is connected to the isolation port 13d of the power distribution/synthesizer 13, and this high frequency terminator 21 is an isolator as shown in FIGS. 2 and 3. It consists of a 50Ω transmission line 19 connected to the ration port 13d, and a triangular radio wave absorber 20 disposed on the 50Ω transmission line 19.

The radio wave absorber 20 is made of, for example, epoxy iron or ferrite rubber.

By arranging the radio wave absorber 20 on the 50Ω transmission line 19 in this way, it is possible to provide a 50Ω termination at high frequencies.

A DC bias source (power line) 18 is connected to the line end of the 50Ω transmission line 19.

Note that in FIG. 3, 25 is a dielectric substrate;
26 is a housing.

With the above-described configuration, the input high frequency signal is divided in power by the power distribution/synthesizer 12, and the power is distributed to each FET 1.
, 1', the power is combined in the power distribution combiner 13 and output. At this time, the DC bias supplied from the DC bias source 18 is transmitted from the 50Ω transmission line 19 to the power distribution combiner 13. The signal is inputted to the power distribution/combiner 13 through the isolation port 13d of the power distribution/combiner 13, and is applied to each FET 1, 1' via the power distribution/combiner 13.

At this time, since a DC cut capacitor 22 is provided at the output port 13c of the power distribution/combiner 13, the above DC bias is applied to the power distribution/combiner 13.
It never comes out to the output port 13c.

Furthermore, due to the radio wave absorber 20 disposed on the 50Ω transmission line 19, the impedance seen from the isolation port 13d of the power distributor/combiner 13 becomes a characteristic impedance, so that each high frequency amplifier 1
, 1' is sent to the power distribution combiner 13.
output port 13c of the power distribution combiner 13.
is output from.

In this manner, a large current bias can be applied to the FET without affecting the high frequency signal.

(b) Explanation of Second Embodiment FIG. 4 is a circuit diagram showing a second embodiment of the present invention, and FIG. 5 is a sectional view of a high frequency terminator portion.
, as shown in FIG. 5, a triangular radio wave absorber 20 is arranged below a 50Ω transmission line 19. That is,
The dielectric substrate 25 of the substrate is partially removed to accommodate the radio wave absorber 20, and the radio wave absorber 20 is fitted into that portion.

Even in this case, substantially the same effects and advantages as those of the first embodiment described above can be obtained.

Note that the other configurations are almost the same as the first embodiment described above, so a description thereof will be omitted.

(c) Explanation of the third embodiment FIG. 6 is a circuit diagram showing the third embodiment of the present invention, and FIG. 7 is a sectional view of the high frequency terminator portion.
, as shown in FIG. 7, a 50Ω transmission line 19 constituting a high-frequency terminator 21 is extended, and a terminator 24 is connected to the extended end via a DC cut capacitor 23.

As described above, since the terminator 24 is connected to the extended end of the 50Ω transmission line 19 constituting the high frequency terminator 21 via the DC cut capacitor 23, the impedance is sufficiently low in the low frequency region. becomes. As a result, even if the FETs 1 and 1' have a high gain in the low frequency range, the termination in the low frequency range is sufficient, so stable operation in the low frequency range can be ensured.

Note that the other configurations are almost the same as those of the first embodiment described above, so a description thereof will be omitted.

It goes without saying that the third embodiment can also be applied to a configuration in which a triangular radio wave absorber 20 is arranged below the 50Ω transmission line 19 (as in the second embodiment).

[0040]

As described in detail above, according to the bias circuit for a high-output amplifier of the present invention (claim 1), the transmission line connected to the isolation port of the power distribution/combiner is connected to the isolation port of the power distribution combiner. A high-frequency terminator consisting of a radio wave absorber placed above or below the transmission line is provided, and a DC cut capacitor is provided at the output port of the power distribution combiner, so that high-frequency signals are This has the advantage that a large current bias can be applied to the high frequency amplifier without affecting the high frequency amplifier.

Furthermore, in the bias circuit for a high-power amplifier of the present invention (claim 2), the terminator is connected to the extended end of the transmission line constituting the high-frequency terminator via a DC cut capacitor. Therefore, the impedance is sufficiently low in the low frequency range, and even if the high frequency amplifier has high gain in the low frequency range, the termination in the low frequency range is sufficient and stable operation is achieved in the low frequency range. This has the advantage of ensuring that

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

FIG. 3 is a sectional view of a high frequency terminator portion in the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a sectional view of a high frequency terminator portion in a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a third embodiment of the present invention.

FIG. 7 is a sectional view of a high frequency terminator portion in a third embodiment of the present invention.

FIG. 8 is a circuit diagram showing a conventional example.

FIG. 9 is a circuit diagram showing another conventional example.

FIG. 10 is a sectional view taken along the line XX in FIG. 9;

[Explanation of symbols]

1, 1' FET (high frequency amplifier) 2, 2' High frequency signal line 3, 3' High frequency signal line 4, 4' High impedance line 5, 5' High impedance line 6, 6' Open stub 7, 7' Open stub 8 , 8' Power line 9, 9' Power line 10, 10' DC cut capacitor 11, 11'
DC cut capacitors 12, 13 Power distribution combiner 13a, 13b Input port 13c Output port 13d Isolation port 14, 15 50Ω terminator 16, 16' Copper wire 17, 17' Copper wire 18 DC bias source (power supply line) 19 50Ω Transmission line 20 Radio wave absorber 21 High frequency terminator 22 DC cut capacitor 23 DC cut capacitor 24 Terminator 25 Dielectric substrate 26 Housing

Claims (2)

[Claims] Claim 1: At least two high frequency amplifiers (1, 1'
), and at least two input ports (13a, 13b) each receiving an output from the high frequency amplifier (1, 1'
), and an isolation port (13c) that combines the outputs of the DC bias source (18).
The isolation port (13d) is connected to the isolation port (13d) of the power distribution/combiner (13), and these ports are connected in a DC manner. 13d) and a radio wave absorber (20) disposed above or below the transmission line (19).
1), and the power distribution combiner (13)
A bias circuit for a high-output amplifier, characterized in that a DC cut capacitor (22) is provided at the output port (13d). Claim 2: The transmission line (19) constituting the high-frequency terminator (21) is extended, and a terminator (24) is connected to this extended end via a DC cut capacitor (23). A bias circuit for a high output amplifier according to claim 1, characterized in that: