JPH0360381A - Output controller for inverter - Google Patents

Abstract

PURPOSE:To improve the accuracy of the output waveform of a PWM signal by changing the phase voltage data at the changeover of a counter, that is, at both timings of the start and fall of carrier data. CONSTITUTION:This is provided with a first control means 1, which operates phase voltage from frequency data 2, voltage data 3, etc., and designates the data sink, a counter 8, which generates carrier data 8a, comparators 6A-6C, which compare the carrier data 8a with phase voltage data X and Y and output pulse width modulation(PWM) signals, a second control means 1, which outputs the phase voltage data X and Y at the changeover period from the addition to the subtraction of the counter 8 or from the subtraction to the addition, and others. And the phase voltage data X and Y are changed at the changeover of the counter 8, that is, at both timings of the start and fall of carriers. Hereby, the intersection between the carrier data 8 and the phase voltage data X and Y and the intersection between the carrier data 8a and the essential sine wave data are accorded with each other, whereby the waveform of the PWM signal can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention applies pulse width modulation (hereinafter referred to as PW) to the output of an inverter.
This relates to a device controlled by a signal (referred to as M).

[Prior Art] FIGS. 4 to 7 are diagrams showing a conventional inverter output control device disclosed in, for example, Japanese Patent Laid-Open No. 63-1375.
FIG. 4 is a block circuit diagram, FIG. 5 is a diagram explaining the principle of PWM signal generation, and FIG. 6 is a flowchart showing the operation of FIG. 3.
FIG. 7 is an enlarged view of the main part of FIG. 5.

In Figure 4, (1+ is a microcomputer (hereinafter referred to as a microcomputer) which has a memory (ROM) CIAI, a multiplication circuit, a register, etc., and into which 1 frequency data (2), voltage data (3), etc. are input; ) stores basic phase voltage data, and carrier cycle data (la
), phase voltage data X%Y, latch signal (lb) and select signal (lc) are output. (4) is a microcontroller (1
A PWM signal U-W that controls switching elements (not shown) of each phase of the inverter according to commands from 1.
This is a gate circuit that emits , and has the following configuration.

That is, (5A) to (5C) are latch circuits that respectively latch carrier cycle data (la)% phase voltage data X and phase voltage data Y when the latch signal (lb) is input, and (6A) to (6C). ) are latch circuits (5
The outputs of A) to (5C) are compared with the output (8a) of the counter (8) to be output later, and the respective PWM signals (6Ba) (
6Ca), and (7) is a flip-flop (
(hereinafter referred to as F/F), (8) is an addition/subtraction counter that outputs carrier data (8a) that is repeatedly added and subtracted, and emits a reset signal (8b) when the carrier data (8a) is zero. , F/F (7
1. A latch circuit (5^) and a comparator (6A) constitute a carrier data generator. (9) is a microcomputer (1
) by the select signal (lc) from PWM signal (6B
a) A data selector that changes the output destination of (6Ca) and outputs PWM signals U-W of each phase. In this example,
This figure applies to a symmetrical, three-phase AC inverter, and only the phase voltage data in the 60° section is stored in the memory (IA
), and change the output destination for other sections (6
0° data is assigned).

In FIG. 5, PG, P3. P4. P7 is the point where the Y phase is inverted, Pl, P2. P5. PG is the point where the X phase is inverted, Tf
(i=1.2.3.=.) indicates the time required to move from point Pi-1 to point Pi.

A conventional inverter output control device is constructed as described above, and its operation will be explained with reference to FIGS. 5 to 7.

First, as an initial setting of the microcomputer (1), carrier cycle data (la) is written to the latch circuit (5A), phase voltage data X is written to the latch circuit (5B), and phase voltage data γ is written to the latch circuit (5C). . Then, the carrier cycle data (la) latched in the latch circuit (5A)
The value of (actually data in % of the carrier period) and the carrier data (8a) output from the counter (8) are compared by a comparator (6A), and the point where the two match, that is, the point in FIG. At C1, the comparator (6A) issues an output and F/
F(7) is set, the counter (8) starts subtraction, and at the same time, the interrupt control signal lNTl is input to the microcomputer (1), and the interrupt processing shown in the flowchart of FIG. 6 begins.

First, in step (11), the pointer of the basic voltage data in the memory CIA is calculated depending on the position of the 60° interval at which the interrupt occurs. Next, in step (12), phase voltage data X is calculated from the contents of the memory (IA) indicated by the pointer and the voltage parameter Vp. In step (13), phase voltage data Y is calculated from the content of the memory (IA) indicated by the value obtained by adding a certain value to the above pointer and the voltage parameter Vp. Next, point C2 in FIG. 4, that is, At the point where the output (8a) of the counter (8) becomes zero and the reset signal (8b) is output, and the F/F (7) is inverted, the interrupt control signal INT2 is input to the microcomputer (11) and the counter ( 8) starts addition.Then, in step (14), wait for the interrupt control signal INT2 to be input, and when the interrupt control signal INT2 is input, in step (15), phase voltage data X is output to the boat, and in step (15), the phase voltage data Step 16) outputs the phase voltage data Y to the boat, and these data X and Y are written to the latch circuit (5B) (scl).Next, step (17) determines whether the 60' interval has ended, If it has not been completed, the interrupt is allowed in step (18) and the interrupt processing is exited.

When it is determined in step (17) that the 60'' section has ended, the number of carriers is calculated from the frequency data (2) and voltage data (3) in step (19), and the number of carriers is calculated from the frequency data (2) and voltage data (3) in step (19).
Step 20) calculates the carrier period, and step (21) calculates the voltage parameter Vp. Since the interrupt control signal INTI is being input at this point, the interrupt request is cleared in step (22). Step (
23), wait for the interrupt control signal INT2, and proceed to step (
Step 24) outputs phase voltage data X to the boat, and step (
25) outputs the phase voltage data Y to the boat. and,
In step (26), select whether to assign to the X and Y phases,
The carrier period data calculated above in step (27) (
lal is written to the latch circuit (5A). After that, the process moves to step (18).

On the other hand, apart from the operation of the microcomputer (1), the comparator (6Bl)
(6C1 performs PWM by comparing the phase voltage data X, Y already latched in the latch circuits (5B) (5C) and the carrier data (8a) output from the counter (8).
Outputs signals (6Ba) (6Ca). This PWM signal (6Ba) (6Cal specifies which phase is to be switched by the data selector (9), and a PWM signal U-W that drives the inverter is formed. This PWM signal U to W The switching elements of each phase of the inverter are controlled, and AC power of any frequency and voltage is output to a motor or the like.

Now, as shown in FIG. 7, the carrier data (8a
) from the lowest point to the next lowest point (for example, from point CO to point 0
2, etc.), the phase voltage data (phase voltage data Y in FIG. 7) output from the microcomputer (1) does not change.

That is, phase voltage data is inserted stepwise for each carrier.

Therefore, the intersection point PO\, P3' with the carrier data (triangular wave) when the original sine wave data Y° is inserted, and the intersection point PQ, when the phase voltage data Y is inserted.
P3 is shifted by po-poo, P3-P3°.

[Problem to be solved by the invention] In the conventional inverter output control device as described above, stepped phase voltage data X and Y are inserted for each carrier, so it is difficult to insert original sine wave data. There is a problem that there is a slight deviation from the PWM signal obtained in this case, and the accuracy of the output waveform of the inverter decreases, and the motor drive efficiency deteriorates.

This invention was made to solve the above problems, and an object thereof is to provide an inverter output control device that can improve the output waveform accuracy of a PWM signal and improve the motor drive efficiency. shall be.

[Means for Solving the Problems] An inverter output control device according to the present invention includes a first control unit that calculates a phase voltage from frequency data, voltage data, and an output voltage parameter and specifies an output destination of the data. , a counter that generates carrier data, a comparator that compares carrier data and phase voltage data and outputs a PWM signal, a data selector that changes the output destination of the PWM signal, and a counter that changes from addition to subtraction or from subtraction to addition. The control means for the pivot 2 outputs the phase voltage data at the time of switching of the piers.

[Function] In this invention, since the phase voltage data is changed at both the timing of the counter switching, that is, the rising and falling timing of the carrier data, the intersection of the carrier data and the phase voltage data and the carrier data and the original The intersection points of the sine wave data coincide.

[Example] Figures 1 to 3 are diagrams showing an example of the present invention.
The figure is a block circuit diagram, FIG. 2 is a flowchart showing the operation of FIG. 1, and FIG. 3 is a diagram corresponding to FIG.

In FIG. 1, (5D) is a latch circuit that latches the select signal (lc) when the latch signal (lb) is input;
29) is an OR gate that is connected to the comparator (6A) and the counter (8) and generates a latch signal (lb).

Next, the operation of this embodiment will be explained with reference to FIGS. 2 and 3.

First, as an initial setting of the microcomputer (1), carrier cycle data (la) is sent to the latch circuit (5^), phase voltage data X is sent to the latch circuit (5B), phase voltage data Y is sent to the latch circuit (5C), The select signal (lc) is connected to the latch circuit (5
D) respectively. After the subtraction or addition operation of the counter (8), the counter (8) or the comparator (6)
A) is the latch signal (lb) through the OR gate (29)
is output, and the above data and signal are respectively latched. Thereafter, the counter (8) repeats addition and subtraction according to the carrier cycle data (la) latched by the latch circuit (5A), and outputs carrier data (8a). In addition, the counter (8) is carrier data (8a)
When switching between addition and subtraction, an interrupt control signal lNT1. is sent to the microcomputer (1). Outputs INT2. For example, at point GO in FIG.
is input, and at point C1 in FIG. 3, the counter (8) switches to a subtractive operation, and the interrupt control signal
NTl enters.

Interrupt control signal lNTl or interrupt control signal INT2
When entered, it is determined in step (31) whether the 60° interval ends or not, and if it does not end, the basic voltage data in the memory (l^) is Compute the pointer of . Hereinafter, as in the case of FIG. 6, in steps (33) and (34), the phase voltage data
Y is calculated, and in step (351 (36)) they are output to the boat, and in step (37), an interrupt is enabled and the interrupt processing is exited.

When it is determined in step (31) that the 60° section has ended, steps (38) to (
Step 40) calculates the number of carriers, carrier period, and voltage parameter Vp. Then, in step (41), X, Y
,0. X, Y, 1 (0) (7) Output the select signal (lcl) to the latch circuit (5D) to instruct which phase the data is assigned to. Then, in step (42), output the carrier cycle data calculated above. and step (43
), after exchanging the phase voltage data X and Y output in the previous interrupt process, the process moves to step (35).

Here, the series of interrupt processing operations from step (31) to step (37) is performed from point co to point Ct in FIG.
In other words, it ends in half the carrier period.

During this time, the intersection points PO°, P3°, and carrier data (8a) of carrier data (8a) and phase voltage data Y
The intersection point po', p3° of the original sine wave data Y' is
They match as shown in FIG.

[Effects of the Invention] As explained above, in this invention, the phase voltage data is changed at both the timing of counter switching, that is, the rising and falling timing of the carrier, so that the intersection of the carrier data and the phase voltage data and the By matching the intersection of the carrier data and the original sine wave data, it is possible to improve the waveform accuracy of the PWM signal, which has the effect of improving the drive efficiency of the load motor.

[Brief explanation of drawings]

1 to 3 are diagrams showing an embodiment of an inverter output control device according to the present invention, and FIG. 1 is a block circuit diagram;
Fig. 2 is a flowchart showing the operation of Fig. 1, Fig. 3 is a diagram corresponding to Fig. 7, Figs. 4 to 7 are diagrams showing a conventional inverter output control device, and Fig. 4 is a block circuit diagram. , 5th
6 is a flowchart showing the operation of FIG. 4, and FIG. 7 is an enlarged view of the main part of FIG. 5. In the figure, (1) is first and second control means (microcomputer), (2) is frequency data, (3) is voltage data, (6A) to (6C) are comparators, and (8) is a counter. , (8a) is carrier data, (9) is a data selector, X and Y are phase voltage data, and U to W are pulse width modulation signals. Note that the same reference numerals in the figures indicate the same parts.

Claims (1)

[Claims] a first control means that calculates a phase voltage from frequency data, voltage data of an arbitrary basic phase, and an output voltage parameter and specifies an output destination of the data; a counter that generates carrier data that determines the output frequency; A switching element for each phase provided in the inverter, including a comparator that compares the carrier data and the phase voltage data and outputs a pulse width modulation signal, and a data selector that changes the output destination of the pulse width modulation signal. In a control device that outputs alternating current of arbitrary frequency and arbitrary voltage by controlling the above-mentioned pulse width modulation signal with the above-mentioned pulse width modulation signal, the above-mentioned calculated phase voltage data is inputted at the time when the above-mentioned counter switches from addition to subtraction or from subtraction to addition. An inverter output control device comprising a second control means for outputting an output.