JPH0360208B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to parallel A/D converters, particularly those with high precision.

Conventional configuration and its problems Recently, digital processing of video signals has been attracting attention, and A/D converters are a key device therein. When high speed is required, such as in a video signal band, a parallel method is usually adopted. 1st
The figure shows a block diagram of this parallel type 10-bit A/D converter. In Figure 1, A _io is the input, V _RH
~V _RL is a reference voltage, r is a correction resistor, 1 to 8 are amplifiers for applying the correction voltage, C1 to C1024 are comparators, N1 to N1024 are gates, EN is an encoder, CK is a clock, and V _RH and When a voltage of 2 volts is applied between _RL and RL, the reference bias resistor
A reference bias potential divided by 2/1024 volts by R _S is applied to comparators C1 to C1024, and an analog signal is input to each comparator through an analog signal input terminal (A _IN ). The comparator output signal is ANDed with the inverted signal of the output signal of the next stage comparator by gates (N1) to (N102), respectively.
4), passes through the encoder (EN), and is further output to the digital output terminal _D0 via the buffer OB. CK is a clock signal input terminal. Since the 10-bit A/D converter requires high accuracy (error within ±1 millivolt with a dynamic range of 2 volts), a highly accurate correction potential is applied by the trimming resistor r and operational amplifiers 1 to 8.

FIG. 2 shows this parallel type 10-bit A/D converter arranged on an actual plane. This will be explained below with reference to FIG. Since high precision is required, the trimming correction resistor r and the operational amplifier 1 to
8, correction potentials V _R1 to V _R8 are applied.
Since the trimming correction resistor r is corrected to a predetermined voltage range by laser trimming T, the potentials V _R1 to V _R8 at the bending points are fixed to predetermined potentials. However, in the parallel system, many comparators C
1 to C1024 are used, so even though the current flowing into each comparator is small, its accumulation is quite large. On the other hand, as the bit size increases, the accuracy becomes more severe, and the required accuracy is no longer satisfied.

FIG. 3 shows the current flowing in the area surrounded by the broken line circle X in FIG. A main current Im and a minute current ib flowing into each comparator flow through the reference bias resistor Rs, while a minute current ib' flowing into each comparator flows through the signal input side. It is desirable that the wiring resistance on the signal current side is low, but in reality the resistance
It has Ri. The nonlinear error in this case will be calculated. The resistance value of the nth reference bias resistor Rs from the V _RH side is RSn, the current is I(n), and the potential is
Assuming V _R (n), the current I(n) in the K-th column and the (K+1)th column can be expressed by the following equation.

I(n)=I[2 ⁶ × (2K-1)] + [2 ⁶ × (
2K−1)−n]・i _b … 2 ⁷ (K−1)+1≦n<2 ⁷ ×K, however, K=1,
The potential at each point 3, 5, and 7 is V _R (n)=V _R (n-1)-I(n)·R _so . . . However, V _R (o) = V _RH , V _R1 = V _RH +1/16 (V _RH − V _RH ), V _R2 = V _RH +3/16 (V _RL − V _RH ), V _R8 = V _RH +15/16 (V _RL −V _RH ), V _R (1024) = V _RL . Therefore, the actual nonlinear error ΔV _R (n) of the reference bias resistance is ΔV _R (n)=V _R (n)−(V _RL −V _RH )×n/1024 .

Further, the potential difference between the signal input terminal and each comparator input, which is generated by a minute current flowing through the signal wiring, can be obtained as shown in the following equation.

On the odd-numbered column side, [2 ⁷ × (K-1) + 1≦n<2 ⁷ ×
K, K=1, 3, 5, 7] ΔV _io [2 ⁶ × (2K-1) + n] = ΔV _io [2 ⁶ × (2K-
1)+n-1]-R _i ×j'b×(2 ⁶ -n+1)... On the even-numbered column side, [2 ⁷ ×K+1≦n<2 ⁷ ×(K+
1), K=1, 3, 5, 7] ΔV _io [2 ⁶ × (2K+1)−n] = ΔV _io [2 ⁶ × (2K+
1)-n+1]-R _i ×j'b×(2 ⁶ -n+1)...

Therefore, the nonlinear error of the actual A/D converter output is calculated by subtracting the fourth equation from the third equation and by subtracting the fourth equation from the third equation.
It becomes the result of subtracting the expression. Main current I (1024) = 3.5m
Figure 4a shows the nonlinear error when A is a minute current ib = 0.5 μA and RS = Ri. In Figure 3, in the case of odd numbered columns and even numbered columns, the reference bias resistance
Because the direction of the minute current flowing through RS and the signal input resistor Ri is different, a large potential difference occurs at the points of comparator numbers 64, 192, 320...960, and there is a nonlinear error of about 0.8 LSB, which causes A/D conversion. The accuracy required for the device, 0.5LSB, is not satisfied. Furthermore, there may be variations in the process. In a 10-bit A/D converter, the chip size is approximately 9.2 x 9.8 ^mm2 , which is very large, and within the chip, the film thickness variation of the aluminum resistor (the reference bias resistor is made of aluminum) is approximately 3%. In that case, it will be as shown in Figure 4b, and in this case also.
Does not satisfy 0.5LSB.

Purpose of the Invention The present invention provides a parallel type A/
The purpose is to provide a D converter.

Structure of the Invention The parallel A/D converter of the present invention comprises a plurality of comparators and a plurality of series low antibodies that provide a reference potential input to the comparators, and a serial series connected in a bent manner. a resistance line and a signal wiring input to the comparator and arranged in parallel and close to the series resistance line; The present invention is characterized in that current flows in the same direction.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 5 to 7. Components having the same functions as those in FIGS. 1 to 3 are designated by the same reference numerals, and their explanations will be omitted.

FIG. 5 shows the 10-bit A/
The layout diagram of the converter of the D converter is shown. Comparator C1~
C1024, reference bias resistor R, trimming resistor r, operational amplifiers 1 to 8, encoder EN, and buffer OB are arranged in the same manner as in the conventional case. Signal input terminal
A _IN is the bias point of the reference bias resistor V _RH , V _RL ,
They are arranged near the correction bias points V _R1 to V _R8 and on the opposite side as shown in FIG. By doing this, the direction of the minute current is the same in both odd and even columns as shown in Figure 6, and the potential difference △Vi (n) between the signal input terminal and each comparator input is expressed by the following equation. It will be like that.

△Vi (n) = △Vi (n-1) + (2 ⁶ × (2K-
1)-n)i'b・Ri... However, 2 ⁷ × (K-1) + 1≦n<2 ⁷ ×K K=1, 3,
5, 7. Since Rs=Ri and ib=i′b, the second
When the sixth equation is subtracted from the equation, the terms ib and i′b disappear. In other words, it is equivalent to the case where there is no minute current, and the nonlinear error in the calculation result is zero. Furthermore, even when there are process variations, the reference bias resistance Rs and signal input wiring resistance
Since Ri is equal, the nonlinear error could not be confirmed as shown in FIG.

In the above embodiment, it was assumed that the voltage drop due to the current flowing into the comparator input out of the current flowing through the reference bias resistor Rs and the signal wiring is the same between the reference bias resistor Rs and the signal wiring, but this may be approximately the same. For example, nonlinear errors can be reduced compared to the conventional method.

In addition, the state in which the voltage drop due to the current flowing into the comparator input is the same between the reference bias resistor Rs and the signal wiring is that the reference bias resistor Rs and the signal wiring are made of the same material, have the same width, and have the same film thickness. It can be easily obtained by

Effects of the Invention As explained above, according to the parallel A/D converter of the present invention, the signal wiring for supplying an analog signal to the comparator is arranged in parallel and close to the series low voltage antibody that supplies the reference potential to the comparator. Since the current direction flowing through the series low antibody and the signal wiring is the same, the potential difference can be reduced, and even if the number of bits is large, nonlinear errors can be significantly improved compared to the conventional method. In addition, by making the resistance value per unit length of the signal wiring the same as that of the series low-voltage antibody, the minute current flowing into each comparator input can be effectively made unaffected, resulting in nonlinear error. This is a highly accurate A/D converter that can be eliminated.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional parallel type 10-bit A/D converter, Fig. 2 is a plan view of Fig. 1, and Fig. 3 is a block diagram of a conventional parallel type 10-bit A/D converter.
The figure shows the main part current distribution diagram of FIG. 2, FIGS. 4a and 4b show nonlinear error diagrams of a conventional parallel type A/D converter, and FIGS. 5 to 7 show an embodiment of the present invention. FIG. 5 is a plan layout diagram of the parallel A/D converter according to the present invention, FIG. 6 is a current distribution diagram of the main part of FIG. 5, and FIG. 7 is a nonlinear error of the parallel A/D converter according to the present invention. FIG. 3 is a diagram showing measurement results. Rs...Reference bias resistance [series resistor], A _IN
...Analog signal input terminal, C1 to C1024...
... Comparator, N1 to N1024... Gate, 1 to 8
... operational amplifier, r ... trimming correction resistor,
Ri...Signal wiring resistance, ib, i'b...Minute current flowing into each comparator input, EN...Encoder, D ₀ ...
...Digital output terminal.

Claims (1)

[Claims] 1 A plurality of comparators and a plurality of series resistance wires that provide a reference potential input to the comparators are configured, and a series resistance line wired in a bent manner is connected to the comparators. a signal wiring that is inputted and arranged in parallel and close to the series resistance line, and in a region where the series resistance line and the signal wiring are parallel, the direction of current flowing through the series resistance line and the signal wiring is in the same direction. Parallel type A/D converter constructed. 2. Claim 1 is characterized in that the voltage drop due to the current flowing into the comparator input out of the current flowing through the series resistance wire and the signal wiring is the same between the series resistance wire and the signal wiring. parallel type A/D converter. 3. The parallel A/D converter according to claim 1, wherein the series resistance line and the signal wiring are made of the same material, have the same width, and have the same film thickness. 4. The parallel A/D converter according to claim 1, characterized by having a plurality of signal lines. 5. The parallel A/D converter according to claim 1, wherein a plurality of series correction resistors and operational amplifiers are connected to a part of the series resistance line to apply a correction potential.