JP2806547B2 - High-speed AD converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an increase in the speed and accuracy of a track / hold circuit and a digital-to-analog converter of a two-step AD converter.

<Conventional technology> A two-step AD converter is a pre-AD that roughly performs analog / digital exchange (hereinafter abbreviated as “AD conversion”) on an analog signal input and an accurate analog value corresponding to the code of the pre-AD. A digital / analog conversion (hereinafter abbreviated as “DA conversion”) that outputs the analog signal, and a main AD that further finely converts the difference between the analog value after the DA conversion and the analog signal input into a main AD. Is obtained.

 Hereinafter, the related art will be described with reference to the drawings.

FIG. 6 is a block diagram showing the configuration of a two-step AD converter.

FIG. 7 is a structural block diagram showing details of the track hold unit of FIG.

FIG. 8 is a block diagram for explaining the first embodiment, and particularly, is a block diagram showing a configuration of a conventional two-step AD converter which operates in a pipeline in the application example of FIG.

FIG. 9 is a block diagram showing the details of the DA converter in FIG.

FIG. 6 shows a circuit structure for performing subtraction by a resistor using a current output type DA conversion for speeding up, particularly as a method for obtaining a difference from an input. That is, the analog signal input is supplied to a track hold unit (hereinafter abbreviated as “T / H”) 7.
, And is converted into a digital signal by the first AD converter 2 which is a pre-AD via the buffer amplifier 8, and then again by the DA converter (current output type) 3 to this first AD converter And converted into an accurate analog value (analog current signal) corresponding to the code No. 2 and output. The difference between the output of the T / H 7 and the output of the DA converter 3 is calculated by subtracting means including the resistors R _{1 to} R ₃ and the residual amplifier 4. This difference is due to the second AD
The conversion unit 5 converts the digital signal into a digital signal. The digital signal outputs of the first and second AD conversion units 2 and 5 are guided to the correction unit 6 and combined to become digital signal outputs corresponding to analog signal inputs.

Here, the track hall circuit 7 keeps the analog value constant during the AD conversion cycle, and the high-speed T / H generally has a configuration as shown in FIG.

In FIG. 7, an analog signal input is applied to a bridge type diode switch 72 via a buffer amplifier 71. At this time, when the current sources 73 and 74 are turned on by the clock K, the diode switch 72 is turned on, and the capacitor C follows the voltage of the analog signal input. When the current sources 73 and 74 are turned off, the diode switch 7
2 is turned off, and the input analog voltage is held in the capacitor C. The value is output via the buffer amplifier 75.

By the way, the configuration of such a two-step AD converter composed of T / H7 shown in FIG. 6 has an ADA part that performs rough AD conversion at high speed and immediately outputs an analog value corresponding to the result. , The delay time in this part is unchanged AD
There is a problem that conversion time is lost.

Therefore, in order to solve this problem, as a method that can improve the conversion rate even if the conversion time of the entire two-step AD converter is long, a delay line (delay line) between T / H7 and the residual amplifier is used.
In some cases, as shown in FIG. 8, two T / Hs 7a and 7b are used to perform so-called pipeline processing. That is, in the configuration of FIG. 8, after the analog signal input is held at the subsequent T / H 7b, the T / H 7
7a can sample and hold the next analog signal input. As a result, the processing of the next analog signal input can be started before the conversion corresponding to the preceding analog signal input is completed.

Further, as shown in FIG. 9, the DA converter 3 includes a plurality of current switches (K _S w ₁ , K _S w ₂ ,...) For passing an output current according to a digital signal to be converted into an analog signal. A configuration of a constant current source (T ₁ , T ₂ ,...) Having a configuration including a plurality of transistors (Q ₁₀ , Q ₂₀ ,...) Connected thereto is common.

That is, in the FIG. 9, a pair of transistors Q ₁₁ and Q
₁₂ and is a current switch K _S w ₁ where the emitter is arranged in connection, the transistor Q ₁₀ whose emitters are connected the collector to the common connection of the emitter of the transistor Q ₁₁ and Q ₁₂ is connected to the resistor R ₀ A first line is constituted by the constant current source T ₁ having the threshold voltage V _TH applied to the base of the transistor Q ₁₁ , the analog output terminal A _out is connected to the collector, and the collector of the transistor Q ₁₂ 1 bit D digital signal input from the first AD converter 2 and the base connected to the common is connected to the terminal D ₀ is
_in (= D ₀₎ is applied to the base of the transistor Q _10,
Preamplifier U ₀ is made to the circuit arrangement which is connected a reference voltage generating circuit V _ST having a transistor Q ₀₀ which is connected to the base. These are arranged in parallel according to the number of input bits (D ₀ , D ₁ ,...). In such a configuration, for example, the level of the digital signal input is such that the low level is sufficiently lower than the threshold voltage _VTH and the high level is sufficiently high. And in such a case,
The current switch outputs the output current of the connected constant current source to the common terminal when the input digital signal is at a high level, and outputs the output current to the output terminal A _out when the input digital signal is at a low level.
Therefore, if the input digital signal is negative logic,
The value of the current flowing through the output terminal A _out is proportional to the digital signal to be converted. In this way, a digital signal is converted into an analog signal. Note that the output of the DA converter 3 can output capacitance C _out as shown by the broken line, the conversion rate of the DA converter portion 3 is limited by the resistor (subtraction resistor) R ₁ and the output capacitance C _out Therefore, it is needless to say that the output capacity should be as small as possible.

<Problems to be solved by the invention> Such a conventional configuration has the following problems.

(1). The method using the delay line in the above term often uses a coaxial line for higher accuracy.
In order to obtain a delay of 20 ns, in addition to increasing the size to about 4 m,
Since the matching is performed with a low impedance of 50Ω or 75Ω, the frequency characteristics and distortion characteristics of the driving T / H output amplifier deteriorate. In addition, in the case of the circuit configuration of FIG.
By arranging two H7s in series, the number of buffer amplifiers (71, 75) in series increases to four, and as a result,
Since problems such as deterioration of distortion characteristics and mixing of clock noise of the first AD converter 2 occur, for example, a high-speed and high-precision AD converter such as 30 Msps, 12 bits, and a high-frequency signal close to the Nyquist frequency are used. It was difficult to realize a device with high dynamic accuracy.

(2). By the way, in order for the DA converter 3 to have a configuration of 30 Msps, 12 bits, a high-speed conversion speed of about 10 ns and a precision of 12 bits are required. However, as a practical problem, if the potential difference ΔV _BE (Q ₀₀ , Q ₁₀ , Q ₂₀ ,...) Of the bias voltage due to the difference in the analog output current has the same characteristic, it is assumed that twice the output current of Q ₁₀ flows through Q _20. , V _BE0 = V _BE1 , V
_BE2 the _{-V BE1 = (KT / q)} ln2 = ΔV BE. However, V _BE0 : Q
The base emitter voltage of _00, the base emitter voltage of V _BE1 : Q ₁₀ , and the base emitter voltage of V _BE2 : Q ₂₀ ), and the capacitance attached to the emitter of the current switch (dashed lines C ₁ , C ₂ ,…)), It has been difficult to achieve high-speed and high-accuracy 2-step AD.

The present invention has been made to solve these problems, and an object of the present invention is to realize a two-step AD converter that achieves high speed and high accuracy.

<Means for Solving the Problems> For this purpose, according to the first aspect of the present invention, an input analog signal is tracked and held by a track and hold unit, and its output is converted into a digital signal by a first AD conversion unit. The converted digital signal is again converted to an analog signal by the DA converter, and the difference between the analog signal and the output of the track-and-hold unit is taken out by the subtracting means.
The present invention relates to an AD converter that converts a digital signal by an AD converter and obtains a digital signal corresponding to the input analog signal from a digital output of the first and second AD converters. First switch means for turning on and off the input analog signal by the track and hold unit, first capacitor for holding the output voltage of the first switch means, and second switch for inputting the hold voltage of the first capacitor
, A second switch for turning on and off the output of the second buffer amplifier, a second capacitor for holding the output voltage of the second switch, and a holding voltage for the second capacitor. A third buffer amplifier for inputting and outputting to the subtracting means, and a fourth buffer amplifier for inputting the holding voltage of the first capacitor and outputting to the first AD converter, The point is that the pipeline operation is performed by holding the analog signal by the second capacitor after a predetermined time after holding the analog signal by the first capacitor.

According to a second aspect of the present invention, there is provided the A / D converter, wherein the D / A converter includes a current switch for passing an output current according to a digital signal to be converted into an analog signal, and a reference voltage. And a constant current source that supplies a current equal to the reference current to the emitter of the current switch via a resistor using a feedback circuit that keeps the reference current constant based on the current flowing through the reference current determining resistor. It is characterized in that a plurality of circuits are provided, and the reference current determining resistor is selected and each of the reference currents is weighted.

<Operation> In the first aspect, the distortion characteristics can be improved by using the second and fourth buffer amplifiers as holding amplifiers of the first capacitor and reducing the number of buffer amplifiers that are put in series. And the first AD converter can be separated, so that noise interference can be eliminated.

According to a second aspect of the present invention, a weighted current output type configuration in which the number of output transistors is reduced as much as possible to reduce the capacitance is used as the DA converter, so that high-speed and high-precision subtraction is performed. High-speed conversion that suppresses the generated grid and overshoot can be realized.

Embodiment << About Claim 1 >> Hereinafter, the invention of claim 1 will be described in detail with reference to FIG. 1 to FIG. In the following drawings, the same parts as those in FIGS. 6 to 9 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 1 is a configuration block diagram showing details of a main part (T / H of FIG. 2 below) of an embodiment of a high-speed AD converter according to claim 1 of the present invention.

FIG. 2 is a block diagram showing an embodiment of a high-speed AD converter according to claim 1 of the present invention. In FIG. 2, the same parts as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 3 is a time chart showing the operation of the FIG. 2 apparatus.

In FIG. 2, T / H1 has two outputs, receives an analog signal, and receives the residual signal from a different terminal through a residual amplifier 4 and a first amplifier.
Are output to the AD conversion unit 2. The AD converters 2 and 5 use a flash type AD converter with 5-bit accuracy and 8-bit accuracy, respectively, and the DA converter 30 uses a 5-bit resolution and 12-bit accuracy. The details of the DA converter 30 will be described later.

In FIG. 1, reference numeral 11 denotes a first buffer amplifier to which an input analog signal is applied, and reference numeral 12 denotes a first switch means, and the output of the buffer amplifier 11 is connected to one end.
A diode switch similar to, 13 is a positive voltage source Vs at one end
Connect _+, the current source and the other terminal is connected to the anode terminal of the diode switch 12, 14 is a negative voltage source Vs of the end _- connected to a current source the other end is connected to the cathode terminal of the diode switch 12 a first capacitor, 15 a second buffer amplifier FET input for inputting the voltage held by the capacitor C ₁ C ₁ is holding the voltage passing through the diode switch 12, 1
6 is a diode switch similar to 12 in which the output of the buffer amplifier 15 is connected to one end, constituting a second switch means;
Connect one end is the positive voltage source Vs _+, the current source 18 has one end negative voltage source Vs to the other terminal is connected to the anode terminal of the diode switch 16 _- connected the other end has a diode in the switch 16
A current source connected to the cathode terminal side of the second capacitor C ₂ is a second capacitor for holding a voltage passed through the diode switch 16,
19 the third FET input for inputting the voltage held by the capacitor C ₂
A bootstrap buffer circuit 21 which feeds back the analog hold value of the buffer amplifier 19 to the switch 16 when the switch 16 is turned off to make the reverse bias voltage of the diode constant regardless of the hold voltage; 21
Fourth buffer amplifier FET input for inputting the voltage held by the capacitor C ₁ is 22 the analog value held in the buffer amplifier 21, 20 and a similar bootstrap buffer feedback to switch 12 when the switch 12 is turned off Circuit.

The operation of the high-speed AD converter having such a configuration will be described below with reference to the time chart of FIG.

Has switch 12 is turned on first track and hold unit 1, the voltage of the capacitor C ₁ is assumed to follow the input analogue signal via a buffer amplifier 11. current source 13, 14 by the clock K ₁ at timing t ₁ is the switched diode switch 12 from on to off is turned off, the input analog signal is held in the capacitor C ₁ (the sample value S _1). Voltage held in the capacitor C ₁ is AD converted by the first AD converter 2 through a buffer amplifier 21 (t _2). The output digital value of the AD converter 2 is 12 in the DA converter 3.
It is converted to a corresponding analog value by DA conversion with bit precision (t ₃ ). Current source 17 and 18 by the clock K ₂ is switched from ON to OFF, the diode switch 16 is turned off, the voltage of the capacitor C ₁ is held in the capacitor C ₂ (t _4). At the same time diode switch 12 by the clock K ₁
There switched from OFF to ON, then it follows the input analog signal held in the capacitor C ₁ (the sample value S _2), the following AD
Conversion cycle ^{_{(t 1 -, t 2 -}} , t 3 -, ...) starts. The holding voltage of the capacitor C ₂ and the DA converter 3 via the buffer amplifier 19
Is amplified 16 times by the residual amplifier 4 (t ₅ ).
The output of the residual amplifier 4 is AD-converted by the second AD converter 5 (t ₆ ). The correction unit 6 adds the 5-bit output data of the first AD conversion unit 2 and the 8-bit output data of the second AD conversion unit 5 and compensates for the error to obtain a 12-bit digital output (t ₇ ).
In the above operation, the single conversion cycle is a period of _{t 1 ~t 7, t 1 ~t} 1 - interval Tc of determination of conversion rate.

According to the high-speed AD converter having such a configuration, the following can be realized.

: By the first capacitor C ₁ quickly after the input signal is held second capacitor C ₂ is a track and hold the next input signal, the pipeline operation is performed, 1
A conversion rate with a repetition time shorter than the time required for one AD conversion can be realized. For example, T _C = 33.3 ns for an AD conversion time of 58 ns, that is, a conversion rate of 30 Msps can be obtained.

: Since a delay line is unnecessary, miniaturization and high accuracy can be achieved.

: Since the number of buffer amplifiers passing from the input of T / H to the output of the residual amplifier is reduced from 4 in FIG. 8 to 3, the distortion caused by the buffer amplifier is suppressed and high dynamic accuracy can be obtained. .

: Since the first-stage hold amplifiers 15 and 21 are connected in parallel, the clock noise generated by the second-stage switch 16 and the first
Can prevent mutual interference due to kickback noise of the AD conversion clock generated at the input of the A / D converter 2, and high dynamic accuracy can be obtained.

<Other Embodiments of Claim 1> Although a bridge type diode switch is used in the T / H1 in the above embodiment, any other high speed switch can be used. Also, the first AD converter has 5-bit accuracy, and the second AD converter has 8-bit accuracy.
However, the present invention is not limited to this.

 Alternatively, it can be made as shown in FIG.

FIG. 4 is a block diagram showing a main part of another embodiment of the high-speed AD converter according to claim 1 of the present invention (showing one having an impedance conversion circuit).

In FIG. 4, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In Figure 4, the holding voltage of the capacitor C ₁ is connected to a conventional buffer amplifier 15a, 21a not FET input via a first impedance conversion circuit of high input resistance consists of a constant current source 24. and pET23. The holding voltage of the capacitor C ₂ is F
It is connected to a normal buffer amplifier 19a which is not an FET input through a second impedance conversion circuit having a high input resistance composed of the ET 25 and the constant current source 26. With such a configuration, the influence of the input drift of the buffer amplifier can be reduced, and the first impedance conversion circuit is commonly connected to the parallel buffer amplifiers 15a and 21a. The influence of the input drift exerted can be made equal to enable correction.

<< Regarding Claim 2 >> Hereinafter, the invention of claim 2 will be described in detail with reference to FIG. In FIG. 5, the same parts as those in FIGS. 1 to 4 and FIGS. 6 to 9 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 5 is a block diagram showing the configuration of a main part (DA converter 30 in FIG. 2) of one embodiment of the high-speed AD converter according to claim 2 of the present invention.

In FIG. 5, the DA converter 30 has a configuration in which the number of output transistors is reduced as much as possible to reduce the capacity, for example, a weighted current output type configuration with a 5-bit resolution of 15.5 mA full scale (minimum 5 a plurality of current switches K _s w ₁ ~K _s w ₅ to flow the output current in response to a digital signal to be converted into an analog signal described in FIG. 9 set, which are provided corresponding to the plurality of current switches In combination with a constant current source connected to the

Specifically, a 5-bit logic input (each bit D ₀ , D
₁ ,..., D ₅ ), a feedback circuit (hereinafter abbreviated as “FB circuit”) 30FB _{1 to} 30FB ₅ for stabilizing the current value of the analog output with high accuracy is provided, and a constant circuit connected to the current switch is provided. a current source, FB circuit 30FB ₁ ~30FB ₅ and the reference voltage V _ref and the reference current determination resistor (hereinafter abbreviated as "RF resistance") R ₁₁ to R ₅₁ and resistor R ₁₃ to R to be connected to current switch
Composed of _53, the reference voltage and the weighted reference current determined by the RF resistor (I _1a ~I _5a), FB circuit 30FB
_{1 ~30FB 5} control, specifically, the voltage at the operational amplifier U ₁ ~U ₅ flowing in transistor _{Q 13 / R 12 ~Q 53 /} R 52 constituting the FB circuit
By controlling V _{C1 to} V _C5 , the currents I _{1b to} I _5b corresponding to the reference currents flowing through the resistors R _{13 to} R ₅₃ are kept constant to obtain a weighted current output type.

Here, for example, looking at the D ₀ bit, FB circuit 30FB
₁ consists transistor Q ₁₃ and the operational amplifier U ₁ and a resistor R ₁₂ Prefecture, transistor Q ₁₃ is connected to the base of the base threshold voltage V _TH of the transistor Q ₁₁ of the current switch K _SW1 is applied, the collector RF resistor R inverting terminal and the other end of the operational amplifier U ₁ is connected to the reference voltage V _ref
Connected to one end of the _11, the emitter is connected to one end of a resistor R _12, also the operational amplifier U ₁ is connected to the non-inverting terminal to the common connection output terminal to the connection portion of the resistor R ₁₂ and the resistor R ₁₃ doing. Hence the constant current circuit when this is made from the reference voltage V _ref and the RF resistance R ₁₁ Metropolitan include FB circuit 30FB _1, generated at the connection portion between the output terminal of the resistor R ₁₂ and an operational amplifier U ₁ of current I _1a flows By controlling the control voltage V _C1 , the reference current I _1a
It was constant, equal current I to the reference I _1a by the operation of the current switch K _SW1 based on the digital input D ₀ bits
It can flow _1b to the resistor R ₁₃ (same applies to the following other strains).

In the current switches K _{SW1 to} K _SW5 , the analog output terminal A _out is connected to the collector of one of the transistors Q ₁₁ (to Q ₅₁ ) and the logic threshold voltage V _TH is fixed to the base, as in FIG. are, also, the logic input is connected to the base of the other transistor Q ₁₂ (~Q _52),
Collector is grounded. The configuration at this time is a negative logic that turns off the analog output when the voltage of the logic input is higher than the threshold voltage _VTH . Here, the characteristics (V _BE , h _fe at the time of the emitter current I) of the transistors Q ₁₁ and Q ₁₃ (to Q ₅₁ and Q ₅₃ ) and even the resistance values of R ₁₂ and R ₁₃ (to R ₅₂ and R ₅₃ ) If the required accuracy is met, the FB circuit and reference voltage
Based on the reference current I _1a (~ I _5a ) weighted to the 5-bit resolution determined by each constant current source composed of an RF resistor, for example, 0.5 (1,2,4,8mA), respectively, the analog output current is determined by the accuracy Can be obtained.

In this embodiment, each bit has the same configuration except for the resistance value, but the respective resistors R ₁₂ , R ₁₃ / R ₂₂ , R ₂₃ /.
/ R ₅₂ and R ₅₃ are composed of one thin film resistor network,
The RF resistors R ₁₁ , R ₂₁ ,..., R ₅₁ are formed by one thin film resistor network. Of course, it is needless to say that all of these may be used in an integrated manner.

As a result, the current switches K _{sw1 to} K _sw5 output the output current of the connected constant current source to the ground terminal when the input digital signal is at a high level, and output the output current to the output terminal A _out when the input digital signal is at a low level. . Therefore, if the input digital signal is negative logic, the value of the current flowing through the output terminal A _out is proportional to the digital signal to be converted.
In this way, a digital signal is converted into an analog signal.

<Effects of the Invention> As is clear from the above description, according to the present invention,
The following effects are obtained.

According to the first aspect, it is possible to realize a two-step AD converter that achieves high speed and high accuracy, particularly, improved dynamic accuracy with a simple configuration.

According to the second aspect of the present invention, the DA converter is a weighted constant current type, so that the number of output transistors becomes the minimum number of bits required, and the speed can be increased by reducing the output capacitance. Further, the output current accuracy can be increased to a desired level by matching the characteristics and resistance of the transistor. In particular, by using a monolithic transistor array, a network resistor, or the like, for example, high-precision 12-bit accuracy can be easily obtained, and temperature fluctuation can be reduced. Furthermore, since the constant current source is realized by a resistor, the capacitance attached to the emitter of the current switch as shown in FIG. 9 is eliminated, and glitches and overshoots generated by switching transients can be suppressed, thereby realizing high-speed conversion.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of a high-speed AD converter according to claim 1 of the present invention, and FIG. 2 is an embodiment of a high-speed AD converter according to claim 1 of the present invention. FIG. 3 is a time chart showing the operation of the apparatus shown in FIG. 2,
FIG. 4 is a block diagram showing a main part of another embodiment of the high-speed AD converter according to the present invention, and FIG. 5 is a block diagram showing the main parts of one embodiment of the high-speed AD converter according to claim 2 of the present invention. FIG. 6 is a block diagram showing details of a conventional two-step AD converter, FIG. 7 is a block diagram showing details of T / H in FIG. 6, and FIG. 8 is a claim. FIG. 9 for explaining the first embodiment;
The figure is a block diagram showing the details of the DA converter in FIG. 1 ... Track / hold section (T / H), 2 ... First AD
Conversion unit, 3,30 DA conversion unit, 4 subtraction means, 5 second AD conversion unit, 12 first switch means, C ₁ first
.., Second buffer amplifier, 16... Second switch means, C ₂ ... Second capacitor, 19... Third buffer amplifier, 21.

Claims (2)

(57) [Claims] An input analog signal is tracked and held by a track and hold section, an output of the track is converted into a digital signal by a first AD converter, and the converted digital signal is again converted into an analog signal by a DA converter. Then, the difference between the analog signal and the output of the track and hold unit is extracted by a subtraction unit, and the output of the subtraction unit is converted into a digital signal by a second AD conversion unit.
In an AD converter for obtaining a digital signal corresponding to the input analog signal from the digital signals of the first and second AD converters, a first switch means for turning on and off the input analog signal by the track and hold unit; A first capacitor for holding an output voltage of the first switch means, a second buffer amplifier for inputting a hold voltage of the first capacitor, and a second switch means for turning on / off an output of the second buffer amplifier A second capacitor for holding the output voltage of the second switch means; and a third capacitor for inputting the hold voltage of the second capacitor and outputting the voltage to the subtraction means.
And a fourth buffer amplifier for receiving the voltage held by the first capacitor and outputting the voltage to the first AD converter, and holding the input analog signal with the first capacitor in each conversion cycle. A high-speed AD converter configured to perform a pipeline operation by holding a second capacitor after a predetermined time. 2. An A / D converter comprising: a current switch for flowing an output current in accordance with a digital signal to be converted into an analog signal; and a reference current for holding a reference current constant based on a current flowing through a reference current determining resistor by a reference voltage. Using a feedback circuit, a plurality of circuits including a constant current source that supplies a current equal to the reference current to the emitter of the current switch via a resistor, and selecting the reference current determining resistor to select each of the The high-speed AD converter according to claim 1, wherein the reference current is weighted.